U.S. patent application number 09/149882 was filed with the patent office on 2001-08-02 for communication channel and interface devices for bridging computer interface buses.
This patent application is currently assigned to ACQIS TECHNOLOGY, INC.. Invention is credited to CHU, WILLIAM W. Y..
Application Number | 20010011312 09/149882 |
Document ID | / |
Family ID | 27374633 |
Filed Date | 2001-08-02 |
United States Patent
Application |
20010011312 |
Kind Code |
A1 |
CHU, WILLIAM W. Y. |
August 2, 2001 |
COMMUNICATION CHANNEL AND INTERFACE DEVICES FOR BRIDGING COMPUTER
INTERFACE BUSES
Abstract
The present invention encompasses an apparatus for bridging a
first computer interface bus and a second computer interface bus,
where each of the first and second computer interface buses have a
number of parallel multiplexed address/data bus lines and operate
at a clock speed in a predetermined clock speed range having a
minimum clock speed and a maximum clock speed. The apparatus
comprises an interface channel having a clock line and a plurality
of bit lines for transmitting bits; a first interface controller
coupled to the first computer interface bus and to the interface
channel to encode first control signals from the first computer
interface bus into first control bits to be transmitted on the
interface channel and to decode second control bits received from
the interface channel into second control signals to be transmitted
to the first computer interface bus; and a second interface
controller coupled to the interface channel and the second computer
interface bus to decode the first control bits from the interface
channel into third control signals to be transmitted on the second
computer interface bus and to encode fourth control signals from
the second computer interface bus into the second control bits to
be transmitted on the interface channel. In one embodiment, the
first and second interface controllers comprise a host interface
controller (HIC) and a peripheral interface controller (PIC),
respectively, the first and second computer interface buses
comprise a primary PCI and a secondary PCI bus, respectively, and
the interface channel comprises an LVDS channel.
Inventors: |
CHU, WILLIAM W. Y.; (LOS
ALTOS, CA) |
Correspondence
Address: |
RICHARD T. OGAWA
TOWNSEND AND TOWNSEND AND CREW L.L.P
TWO EMBARCADERO CENTER
8 TH FLOOR
SAN FRANCISCO
CA
94111-3834
US
|
Assignee: |
ACQIS TECHNOLOGY, INC.
|
Family ID: |
27374633 |
Appl. No.: |
09/149882 |
Filed: |
September 8, 1998 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60083886 |
May 1, 1998 |
|
|
|
60092706 |
Jul 14, 1998 |
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Current U.S.
Class: |
710/64 |
Current CPC
Class: |
G06F 13/4045
20130101 |
Class at
Publication: |
710/64 |
International
Class: |
G06F 013/12; G06F
013/38 |
Claims
1. In a microprocessor based computer system, an apparatus for
bridging a first computer interface bus and a second computer
interface bus, each of the first and second computer interface
buses having a number of parallel multiplexed address/data bus
lines, each of said bus lines operating at a clock speed in a
predetermined clock speed range having a minimum clock speed and a
maximum clock speed, said apparatus comprising: a first interface
controller coupled to the first computer interface bus to encode
control signals from the first computer interface bus into control
bits; an interface channel coupled to said first interface
controller, said interface channel having a clock channel and a
plurality of bit channels and transmitting said control bits from
said first interface controller; and a second interface controller
coupled to said interface channel and the second computer interface
bus, said second interface controller to decode said control bits
from said interface channel into control signals to be transmitted
on the second computer interface bus.
2. The apparatus of claim 1, wherein said first interface
controller comprises a host interface controller (HIC) and said
second interface controller comprises a peripheral interface
controller (PIC).
3. The apparatus of claim 2, wherein said first computer interface
bus comprises a primary peripheral component interconnect (PCI) bus
within an attached computer module, said second computer interface
bus comprises a secondary PCI bus within a peripheral console, and
said interface channel comprises a low voltage differential signal
(LVDS) channel, further wherein said HIC comprises a first PCI bus
controller coupled to the primary PCI bus, a first translator
coupled to said first PCI bus controller, a first transmitter
coupled to said first translator, and a first receiver coupled to
said first translator, further wherein said PIC comprises a second
PCI bus controller coupled to the secondary PCI bus, a second
translator coupled to said second PCI bus controller, a second
transmitter coupled to said second translator, and a second
receiver coupled to said second translator.
4. The apparatus of claim 1, wherein said interface channel
comprises two sets of unidirectional lines.
5. The apparatus of claim 4, wherein each of said two sets of
unidirectional lines comprises a point-to-point bus.
6. The apparatus of claim 5, wherein each of said two sets of
unidirectional lines comprises a single master bus.
7. The apparatus of claim 1, wherein said interface channel further
comprises a reset line.
8. The apparatus of claim 1, wherein said clock channel of said
interface channel operates at a higher clock speed than the clock
speed of the first and second computer interface buses.
9. The apparatus of claim 1, wherein said plurality of bit channels
are fewer in number than both the number of multiplexed
address/data bus lines in said first computer interface bus and the
number of multiplexed address/data bus lines in said second
computer interface bus.
10. In a computer system having a primary peripheral component
interconnect (PCI) bus, a secondary PCI bus, and an interface
channel interfacing said primary and secondary PCI buses, each of
the primary and secondary PCI buses having a number of parallel
multiplexed address/data lines, each of said bus lines operating at
a clock speed in a predetermined clock speed range having a minimum
clock speed and a maximum clock speed, an interface controller
comprising: a bus controller to interface with one of the primary
and secondary PCI buses and to manage transactions that occur with
said one of the primary and secondary PCI buses; and a translator
coupled to said bus controller to encode control signals from said
one of the primary and secondary PCI buses into control bits and to
decode control bits from the interface channel into control
signals.
11. The interface controller of claim 10 further comprising: a
transmitter coupled to said translator, wherein said transmitter
serializes parallel bits into first serial bit packets and
transmits said first serial bit packets to the interface channel;
and a receiver coupled to said translator, wherein said receiver
receives second serial bit packets from said interface channel and
recovers parallel bits from said second serial bit packets.
12. The interface controller of claim 11 further comprising a reset
control circuit for one of sending a reset signal to and receiving
a reset signal from a second interface controller.
13. The interface controller of claim 11 further comprising a reset
and parity error circuit for sending a parity error signal and a
reset signal.
14. The interface controller of claim 11 further comprising a video
parallel to serial converter to receive video capture data,
including video port control signals and parallel video port data,
convert said video port control signals and said parallel video
port data into serial video data and transmit said serial video
data to a second interface controller.
15. The interface controller of claim 11 further comprising a video
serial to parallel converter to receive serial video data on a
video data line, convert said serial video data to video port
control signals and parallel video port data, and transmit said
video port control signals and said parallel video port data to a
graphics controller.
16. An interface device for interfacing a first peripheral
component interconnect (PCI) bus of a first computer system with a
second PCI bus of a second computer system, said interface device
comprising: a first connector for coupling to the first PCI bus; a
second connector for coupling to the second PCI bus; and a cable
coupled to said first and second connectors, wherein said cable
comprises an interface channel including a clock channel on a pair
of conductive lines and a plurality of bit channels on a plurality
of pairs of conductive lines, for transferring information between
said first and second connectors using low voltage differential
signals (LVDS).
17. The interface device of claim 16, wherein said interface
channel comprises a first subset of channels, including a first
clock channel on a first pair of conductive lines and a first
plurality of bit channels on a first plurality of pairs of
conductive lines, for transferring information from said first
connector to said second connector and a second subset of channels,
including a second clock channel on a second pair of conductive
lines and a second plurality of bit channels on a second plurality
of pairs of conductive lines, for transferring information from
said second connector to said first connector.
18. In a computer system including an attached computer module
(ACM) and a peripheral console, an interface device for interfacing
a primary peripheral component interconnect (PCI) bus of the ACM to
a secondary PCI bus of the peripheral console, said interface
device comprising: a first connector for coupling to the primary
PCI bus; a second connector for coupling to the secondary PCI bus;
and an interface channel coupled to said first and second
connectors, said interface channel including a clock channel and a
plurality of bit channels, wherein said clock channel and said
plurality of bit channels are on a plurality of conductive lines
and further wherein information is transferred on said interface
channel using a protocol different from that of a PCI bus.
19. The interface device of claim 18 further comprising a cable
comprising said interface channel, wherein information is
transferred between said first and second connectors using low
voltage differential signals (LVDS) and further wherein said
interface channel comprises a first subset of channels, including a
first clock channel on a first pair of conductive lines and a first
plurality of bit channels on a first plurality of pairs of
conductive lines, for transferring information from said first
connector to said second connector and a second subset of channels,
including a second clock channel on a second pair of conductive
lines and a second plurality of bit channels on a second plurality
of pairs of conductive lines, for transferring information from
said second connector to said first connector.
20. An apparatus for interfacing first and second subsystems of a
microprocessor based computer system, said apparatus comprising: a
first computer interface bus within said first subsystem, said
first computer interface having a first number of parallel
multiplexed address/data bus lines, wherein each of said bus lines
in said first computer interface bus operates at a clock speed in a
first predetermined clock speed range bounded by a first minimum
clock speed and a first maximum clock speed and further wherein
each of said bus lines in said first computer interface bus
transmits bits in a first predetermined bit rate range bounded by a
first minimum per line bit rate and a first maximum per line bit
rate; a second computer interface bus within said second subsystem,
said second computer interface having a second number of parallel
multiplexed address/data bus lines, wherein each of said bus lines
in said second computer interface bus operates at a clock speed in
a second predetermined clock speed range bounded by a second
minimum clock speed and a second maximum clock speed and further
wherein each of said bus lines in said second computer interface
bus transmits bits in a second predetermined bit rate range bounded
by a second minimum per line bit rate and a second maximum per line
bit rate; and an interface channel including a clock channel and a
plurality of bit channels, wherein said plurality of bit channels
are fewer in number than both said first number and said second
number.
21. The apparatus of claim 20, wherein each of said plurality of
serial bit channels operates at a clock speed higher than both said
first maximum clock speed and said second maximum clock speed.
22. The apparatus of claim 20, wherein each of said plurality of
serial bit channels transmits bits at a bit rate higher than said
first maximum per line bit rate and said second maximum per line
bit rate.
23. An apparatus for interfacing first and second subsystems of a
microprocessor based computer system, said apparatus comprising: a
first computer interface bus within said first subsystem, said
first computer interface having a first number of parallel
multiplexed address/data bus lines, wherein each of said bus lines
in said first computer interface bus operates at a clock speed in a
first predetermined clock speed range bounded by a first minimum
clock speed and a first maximum clock speed; a second computer
interface bus within said second subsystem, said second computer
interface having a second number of parallel multiplexed
address/data bus lines, wherein each of said bus lines in said
second computer interface bus operates at a clock speed in a second
predetermined clock speed range bounded by a second minimum clock
speed and a second maximum clock speed; and an interface channel
including a clock channel and a plurality of serial bit channels,
wherein each of said plurality of serial bit channels operates at a
clock speed higher than both said first maximum clock speed and
said second maximum clock speed.
24. In a computer system having an attached computer module (ACM)
and a peripheral console, an apparatus for interfacing the ACM and
the peripheral console, said apparatus comprising: a first control
signal based computer interface bus within the ACM; a bit based
interface channel coupled to said first control signal based
computer interface bus; and a second control signal based computer
interface bus within the peripheral console, said second control
signal based computer interface bus coupled to said bit based
interface channel.
25. A computer system comprising: an attached computer module (ACM)
including a first control based computer interface bus; a
peripheral console including a second control based computer
interface bus; and a bit based interface channel coupled to said
first control signal based computer interface bus and said second
control based computer interface device for interfacing said ACM
and said peripheral console.
26. The computer system of claim 25, wherein said first control
based computer interface bus comprises a host peripheral component
interconnect (PCI) bus including a first number of bus lines,
operating at a first clock speed, and transferring bits at a first
per line bit rate and said second control based computer interface
bus comprises a secondary PCI bus having a second number of bus
lines, operating at a second clock speed, and transferring bits at
a second per line bit rate.
27. The computer system of claim 26, wherein said bit based
interface channel comprises a clock channel and a plurality of bit
channels.
28. The computer system of claim 27, wherein said bit based
interface channel comprises a first set of unidirectional channels
including a first clock channel and a first plurality of bit
channels and a second set of unidirectional channels including a
second clock channel and a second plurality of bit channels.
29. The computer system of claim 28, wherein said first and second
sets of unidirectional channels comprise low voltage differential
signal (LVDS) lines.
30. The computer system of claim 27, wherein said interface channel
operates at a clock speed higher than said first and second clock
speeds.
31. The computer system of claim 27, wherein each bit channel in
said interface channel transfers bits at a bit rate higher than
said first and second per line bit rates.
32. The computer system of claim 27, wherein said plurality of bit
channels is smaller in number than both said first number of bus
lines and said second number of bus lines.
33. The computer system of claim 26, wherein said interface channel
consists of one clock channel and one bit channel.
34. The computer system of claim 33, wherein said interface channel
is a IEEE 1394 bus.
35. The computer system of claim 25, wherein said first and second
computer interface buses each comprise at least 32 bus lines.
36. The computer system of claim 25 further comprising a video bus
for transferring video capture data from said peripheral console to
said ACM.
37. The computer system of claim 25 further comprising a video bus
for transmitting digital video signals from said ACM to said
peripheral console.
38. The computer system of claim 37, wherein said video bus
comprises a bus for transmitting video signals for flat panel
displays from said ACM to said peripheral console.
39. The computer system of claim 25 further comprising a video bus
for transmitting television (TV) signals from said ACM to said
peripheral console.
40. The computer system of claim 25 further comprising a video bus
for transmitting super video signals from said ACM to said
peripheral console.
41. The computer system of claim 25 further comprising a power bus
for transmitting power at a plurality of voltage levels between
said peripheral console and said ACM.
42. A method of transmitting control signals from a first computer
interface bus to a second computer interface bus via a bit based
interface channel coupled to the first computer interface bus and
the second computer interface bus, said method comprising:
receiving control signals from the first computer interface bus;
encoding the control signals received from the first computer
interface bus into control bits representing the control signals;
transmitting the control bits on the bit based interface channel;
receiving the control bits; decoding the control bits into the
control signals represented by the control bits; and transmitting
the control signals to the second computer interface bus.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims any and all benefits as provided by
law of U.S. Provisional Application No. 60/083,886 filed May 1,
1998 and of U.S. Provisional Application No. 60/092,706 filed on
Jul. 14, 1998.
[0002] This application is being filed concurrently with the
application of William W. Y. Chu for "Personal Computer Peripheral
Console With Attached Computer Module", filed on Sep. 8, 1998 and
incorporates the material therein by reference
BACKGROUND OF THE INVENTION
[0003] The present invention generally relates to computer
interfaces. More specifically, the present invention relates to an
interface channel that interfaces two computer interface buses that
operate under protocols that are different from that used by the
interface channel.
[0004] Interfaces coupling two independent computer buses are well
known in the art. A block diagram of a computer system utilizing
such a prior art interface is shown in FIG. 1. In FIG. 1, a primary
peripheral component interconnect (PCI) bus 105 of a notebook PC
100 is coupled to a secondary PCI bus 155 in a docking system 150
(also referred to as docking station 150) through high pin count
connectors 101 and 102, which are normally mating connectors. The
high pin count connectors 101 and 102 contain a sufficiently large
number of pins so as to carry PCI bus signals between the two PCI
buses without any translation. The main purpose for interfacing the
two independent PCI buses is to allow transactions to occur between
a master on one PCI bus and a target on the other PCI bus. The
interface between these two independent PCI buses additionally
includes an optional PCI to PCI bridge 160, located in the docking
station 150, to expand the add on capability in docking station
150. The bridge 160 creates a new bus number for devices behind the
bridge 160 so that they are not on the same bus number as other
devices in the system thus increasing the add on capability in the
docking station 150.
[0005] An interface such as that shown in FIG. 1 provides an
adequate interface between the primary and secondary PCI buses.
However, the interface is limited in a number of ways. The
interface transfers signals between the primary and secondary PCI
buses using the protocols of a PCI bus. Consequently, the interface
is subject to the limitations under which PCI buses operate. One
such limitation is the fact that PCI buses are not cable friendly.
The cable friendliness of the interface was not a major concern in
the prior art. However, in the context of the computer system of
the present invention, which is described in the present inventor's
(William W. Y. Chu's) application for "Personal Computer Peripheral
Console With Attached Computer Module" filed concurrently with the
present application on Sep. 8, 1998 and incorporated herein by
reference, a cable friendly interface is desired for interfacing an
attached computer module (ACM) and a peripheral console of the
present invention. Furthermore, as a result of operating by PCI
protocols, the prior art interface includes a very large number of
signal channels with a corresponding large number of conductive
lines (and a similarly large number of pins in the connectors of
the interface) that are commensurate in number with the number of
signal lines in the PCI buses which it interfaces. One disadvantage
of an interface having a relatively large number of conductive
lines and pins is that it costs more than one that uses a fewer
number of conductive lines and pins. Additionally, an interface
having a large number of conductive lines is bulkier and more
cumbersome to handle. Finally, a relatively large number of signal
channels in the interface renders the option of using differential
voltage signals less viable because a differential voltage signal
method would require duplicating a large number of signal lines. It
is desirable to use a low voltage differential signal (LVDS)
channel in the computer system of the present invention because an
LVDS channel is more cable friendly, faster, consumes less power,
and generates less noise, including electromagnetic interferences
(EMI), than a PCI channel. The term LVDS is herein used to
generically refer to low voltage differential signals and is not
intended to be limited to any particular type of LVDS
technology.
BRIEF SUMMARY OF THE INVENTION
[0006] The present invention overcomes the aforementioned
disadvantages of the prior art by interfacing two PCI or PCI-like
buses using a non-PCI or non-PCI-like channel. In the present
invention, PCI control signals are encoded into control bits and
the control bits, rather than the control signals that they
represent, are transmitted on the interface channel. At the
receiving end, the control bits representing control signals are
decoded back into PCI control signals prior to being transmitted to
the intended PCI bus.
[0007] The fact that control bits rather than control signals are
transmitted on the interface channel allows using a smaller number
of signal channels and a correspondingly small number of conductive
lines in the interface channel than would otherwise be possible.
This is because the control bits can be more easily multiplexed at
one end of the interface channel and recovered at the other end
than control signals. This relatively small number of signal
channels used in the interface channel allows using LVDS channels
for the interface. As mentioned above, an LVDS channel is more
cable friendly, faster, consumes less power, and generates less
noise than a PCI bus channel, which is used in the prior art to
interface two PCI buses. Therefore, the present invention
advantageously uses an LVDS channel for the hereto unused purpose
of interfacing PCI or PCI-like buses. The relatively smaller number
of signal channels in the interface also allows using connectors
having smaller pins counts. As mentioned above an interface having
a smaller number of signal channels and, therefore, a smaller
number of conductive lines is less bulky and less expensive than
one having a larger number of signal channels. Similarly,
connectors having a smaller number of pins are also less expensive
and less bulky than connectors having a larger number of pins.
[0008] In one embodiment, the present invention encompasses an
apparatus for bridging a first computer interface bus and a second
computer interface bus, in a microprocessor based computer system
where each of the first and second computer interface buses have a
number of parallel multiplexed address/data bus lines and operate
at a clock speed in a predetermined clock speed range having a
minimum clock speed and a maximum clock speed. The apparatus
comprises an interface channel having a clock channel and a
plurality of bit channels for transmitting bits; a first interface
controller coupled to the first computer interface bus and to the
interface channel to encode first control signals from the first
computer interface bus into first control bits to be transmitted on
the interface channel and to decode second control bits received
from the interface channel into second control signals to be
transmitted to the first computer interface bus; and a second
interface controller coupled to the interface channel and the
second computer interface bus to decode the first control bits from
the interface channel into third control signals to be transmitted
on the second computer interface bus and to encode fourth control
signals from the second computer interface bus into the second
control bits to be transmitted on the interface channel.
[0009] In one embodiment, the first and second interface
controllers comprise a host interface controller (HIC) and a
peripheral interface controller (PIC), respectively, the first and
second computer interface buses comprise a primary PCI and a
secondary PCI bus, respectively, and the interface channel
comprises an LVDS channel.
[0010] In a preferred embodiment, the interface channel has a
plurality of serial bit channels numbering fewer than the number of
parallel bus lines in each of the PCI buses and operates at a clock
speed higher than the clock speed at which any of the bus lines
operates. More specifically, the interface channel includes two
sets of unidirectional serial bit channels which transmit data in
opposite directions such that one set of bit channels transmits
serial bits from the HIC to the PIC while the other set transmits
serial bits from the PIC to the HIC. For each cycle of the PCI
clock, each bit channel of the interface channel transmits a packet
of serial bits.
[0011] The HIC and PIC each include a bus controller to interface
with the first and second computer interface buses, respectively,
and to manage transactions that occur therewith. The HIC and PIC
also include a translator coupled to the bus controller to encode
control signals from the first and second computer interface buses,
respectively, into control bits and to decode control bits from the
interface channel into control signals. Additionally, the HIC and
PIC each include a transmitter and a receiver coupled to the
translator. The transmitter converts parallel bits into serial bits
and transmits the serial bits to the interface channel. The
receiver receives serial bits from the interface channel and
converts them into parallel bits.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 is a block diagram of a computer system using a prior
art interface between a primary and a secondary PCI bus.
[0013] FIG. 2 is a block diagram of one embodiment of a computer
system using the interface of the present invention.
[0014] FIG. 3 is a partial block diagram of a computer system using
the interface of the present invention as a bridge between the
north and south bridges of the computer system.
[0015] FIG. 4 is a partial block diagram of a computer system in
which the north and south bridges are integrated with the host and
peripheral interface controllers, respectively.
[0016] FIG. 5 is a block diagram of one embodiment of the host
interface controller and the peripheral interface controller of the
present invention.
[0017] FIG. 6 is a detailed block diagram of one embodiment of the
host interface controller of the present invention.
[0018] FIG. 7 is a table showing how different PCI control signals
are managed in the case where the HIC is a target on the host PCI
bus.
[0019] FIG. 8 is a table showing how different PCI control signals
are managed in the case where the HIC is a master on the host PCI
bus.
[0020] FIG. 9 is a timing diagram of a PCI memory read cycle with
the HIC as a target.
[0021] FIG. 10 is a timing diagram of a PCI memory write cycle with
the HIC as a target.
[0022] FIG. 11 is a detailed block diagram of one embodiment of the
PIC of the present invention.
[0023] FIG. 12 is a table showing how different PCI control signals
are managed in the case where the PIC is a target on the secondary
PCI bus.
[0024] FIG. 13 is a table showing how different PCI control signals
are managed in the case where the PIC is a master on the secondary
PCI bus.
[0025] FIG. 14 shows a schematic diagram of one embodiment of the
connectors used to couple the HIC and PIC.
[0026] FIG. 15 is a schematic diagram of another embodiment of the
connectors used to couple the HIC and PIC.
[0027] FIG. 16 is a schematic diagram of the rear view of an ACM
showing a peripheral connector and a video connector.
[0028] FIG. 17 shows a schematic diagram of the pin out of the
peripheral connector and the video connector shown in FIG. 16.
[0029] FIGS. 18 and 19 are tables including the pin number, symbol,
signal, standard and description for the pins on the peripheral and
video connectors, respectively.
[0030] FIG. 20 is a table showing the symbols, signals, data rate
and description of signals in a first embodiment of the XPBus.
[0031] FIG. 21 is a table showing the information transmitted on
the XPBus during two clock cycles of the XPBus in one embodiment of
the present invention where 10 data bits are transmitted in each
clock cycle of the XPBus.
[0032] FIG. 22 is a table showing the information transmitted on
the XPBus during four clock cycles of the XPBus in another
embodiment of the present invention where 10 data bits are
transmitted in each clock cycle of the XPBus.
[0033] FIG. 23 is a schematic diagram of the signal lines PCK, PD0
to PD3, and PCN. FIG. 24 is a block diagram of another embodiment
of the HIC and PIC of the present invention and the interface
therebetween.
[0034] FIG. 25 is a detailed block diagram of another embodiment of
the HIC of the present invention.
[0035] FIG. 26 is a detailed block diagram of another embodiment of
the PIC of the present invention.
[0036] FIG. 27 is a schematic diagram of the rear view of another
embodiment of the ACM showing a peripheral connector and a
video/extension connector.
[0037] FIG. 28 shows a schematic diagram of the pin out of the
peripheral connector and the video/extension connector of FIG.
27.
[0038] FIG. 29 is a table including the pin number, symbol, signal,
standard and description for the pins on the peripheral connector
shown in FIG. 27.
[0039] FIG. 30 is a table including the pin number, symbol, signal,
standard and description for the pins on the video/extension
connector shown in FIG. 27.
[0040] FIG. 31 is a table showing the symbols, signals, data rate
and description of signals transmitted in a second embodiment of
the XPBus.
[0041] FIG. 32 is a schematic diagram of the signal lines PCK and
PD0 to PD3.
[0042] FIGS. 33 and 34 are tables showing the data packet types
transmitted from HIC 2500 to PIC 2600 and from PIC 2600 to HIC
2500, respectively.
[0043] FIG. 35 is a table showing different types of first nibbles
and their corresponding data packet types.
[0044] FIG. 36 shows the six nibbles of data packet types HMA1/HMD1
and HMA2/HMD2 sent on lines PD0 to PD3 from the HIC to the PIC.
[0045] FIG. 37 is a table that shows the six nibbles of data packet
types PMA1/PMD1 and PMA2/PMD2 sent on lines PD0 to PD3 from the PIC
to the HIC.
[0046] FIG. 38 is a table showing a PCI target read data packet for
both HIC to PIC and PIC to HIC and includes the six nibbles for
data packet types HTD1/PTD1 and HTD2/PTD2.
[0047] FIG. 39 is a table that shows an example of a PCI read data
packet transaction with the HIC as master and the PIC as
target.
[0048] FIG. 40 is a table that shows an example of a PCI write data
packet transaction with the HIC as master and the PIC as
target.
[0049] FIG. 41 is a table that shows PCI target control data
packets sent from the PIC to the HIC on the XPBus with PCI
response.
[0050] FIG. 42 is a table that shows PCI target control data
packets sent from the PIC to the HIC on the XPBus without PCI
response.
[0051] FIG. 43 is a table that shows PCI master control data
packets sent from the PIC to the HIC on the XPBus with PCI
response.
[0052] FIG. 44 is a table that shows PCI master control data
packets sent from the PIC to the HIC on the XPBus without PCI
response.
[0053] FIGS. 45 and 46 are tables that show the HIC to PIC target
control data packet and master control data packet,
respectively.
[0054] FIG. 47 is a table showing the names, types, number of pins
dedicated to, and the description of the primary bus PCI
signals.
[0055] FIG. 48 is a table showing the names, types, number of pins
dedicated to, and the description of the XPBus signals.
[0056] FIGS. 49 and 50 are tables showing the names, types, number
of pins dedicated to, and the description of the XIS bus video port
signals and the video port signals, respectively.
[0057] FIG. 51 is a table showing the names, types, number of pins
dedicated to, and the description of the flash memory interface
signals.
[0058] FIG. 52 is a table showing the names, types, number of pins
dedicated to, and the description of the test port (JTAG)
signals.
[0059] FIG. 53 is a table showing the names, types, number of pins
dedicated to, and the description of the CPU signals.
[0060] FIG. 54 is a table showing the names, types, number of pins
dedicated to, and the description of the north bridge signals.
[0061] FIG. 55 is a table showing the names, types, number of pins
dedicated to, and the description of the GPIO signals.
[0062] FIG. 56 is a table showing the names, types, number of pins
dedicated to, and the description of the error/reset signals.
[0063] FIG. 57 is a table showing the names, types, number of pins
dedicated to, and the description of the power/ground/oscillator
input signals.
DETAILED DESCRIPTION OF THE INVENTION
[0064] FIG. 2 is a block diagram of one embodiment of a computer
system 200 using the interface of the present invention. Computer
system 200 includes an attached computer module (ACM) 205 and a
peripheral console 210, which are described in greater detail in
the application of William W. Y. Chu for "Personal Computer
Peripheral Console With Attached Computer Module" filed
concurrently with the present application on Sep. 8, 1998 and
incorporated herein by reference. The ACM 205 and the peripheral
console 210 are interfaced through an exchange interface system
(XIS) bus 215. The XIS bus 215 includes power bus 216, video bus
217 and peripheral bus (XPBus) 218, which is also herein referred
to as an interface channel. The power bus 216 transmits power
between ACM 205 and peripheral console 210. In a preferred
embodiment power bus 216 transmits power at voltage levels of 3.3
volts, 5 volts and 12 volts. Video bus 217 transmits video signals
between the ACM 205 and the peripheral console 210. In a preferred
embodiment, the video bus 217 transmits analog Red Green Blue (RGB)
video signals for color monitors, digital video signals (such as
Video Electronics Standards Association (VESA) Plug and Display's
Transition Minimized Differential Signaling (TMDS) signals for flat
panel displays), and television (TV) and/or super video (S-video)
signals. The XPBus 218 is coupled to host interface controller
(HIC) 219 and to peripheral interface controller (PIC) 220, which
is also sometimes referred to as a bay interface controller.
[0065] In the embodiment shown in FIG. 2, HIC 219 is coupled to an
integrated unit 221 that includes a CPU, a cache and a north
bridge. In another embodiment, such as that shown in FIG. 3, the
CPU 305 and north bridge 310 are separate rather than integrated
units. In yet another embodiment, such as that shown in FIG. 4, the
HIC and PIC are integrated with the north and south bridges,
respectively, such that integrated HIC and north bridge unit 405
includes an HIC and a north bridge, while integrated PIC and south
bridge unit 410 includes a PIC and a south bridge.
[0066] FIG. 5 is a more detailed block diagram of one embodiment of
an HIC 505 and a PIC 555 of the present invention. HIC 505 includes
a peripheral component interconnect (PCI) bus controller 510, an
XPBus controller 515, a phase lock loop (PLL) clock 520 and an
input/output (IO) control 525. Similarly, PIC 555 includes a PCI
bus controller 560, an XPBus controller 565, a PLL clock 570 and an
IO control 575. PCI bus controllers 510 and 560 are coupled to the
primary and secondary PCI buses 530 and 580, respectively, and
manage PCI transactions on the primary and secondary PCI buses 530
and 580, respectively. Similarly, XPBus Controllers 515 and 565 are
coupled to XPBus 590. XPBus controller 515 drives the PCK line 591
and PD[0::3] and PCN lines 592 while XPBus controller 565 drives
the PCKR lines 593, the PDR[0::3] and PCNR lines 594 and the RESET#
line 595.
[0067] PCI bus controller 510 receives PCI clock signals from the
primary PCI bus 530 and is synchronized to the PCI clock. However,
as indicated in FIG. 5, the XPBus controller 515 is asynchronous
with the PCI bus controller 510. Instead, the XPBus controller
receives a clock signal from the PLL clock 520 and is synchronized
therewith. PLL clock 520 generates a clock signal independent of
the PCI clock. The asynchronous operation of the PCI bus and the
XPBus allows the PCI Bus to change in frequency, for example as in
a power down situation, without directly affecting the XPBus
clocking. In the embodiment shown in FIG. 5, the PLL clock 520
generates a clock signal having a frequency of 66 MHz, which is
twice as large as the 33 MHz frequency of the PCI clock. (The clock
signal generated by the PLL clock may have a clock speed different
from, including lower than, 66 MHz. For example, in another
embodiment, which is discussed in greater detail below, the PLL
clock 520 generates a clock signal having a frequency of 132
MHz.)
[0068] The XPBus 590 operates at the clock speed generated by the
PLL clock 520. Therefore, PCK, the clock signal from the XPBus
controller 515 to XPBus controller 565 has the same frequency as
the clock signal generated by PLL clock 520. XPBus controller 565
receives the PCK signal after it has been buffered and operates at
the clock speed of PCK. The buffered version of the clock signal
PCK is used to generate the clock signal PCKR, the clock signal
form the XPBus controller 565 to XPBus controller 515. Accordingly,
PCKR also has the same frequency as that generated by the PLL clock
520. The synchronous operation of PCK and PCKR provides for
improved reliability in the system. In another embodiment, PCKR may
be generated independently of PCK and may have a frequency
different from that of PCK. It is to be noted that even when PCKR
is generated from PCK, the slew between PCK and PCKR cannot be
guaranteed because of the unknown cable length used for the XPBus.
For a cable that is several feet long, the cable propagation delay
alone can be several nano seconds.
[0069] As indicated in FIG. 5, PLL clock 570 is asynchronous with
the XPBus controller 565. Instead, PLL clock 570 independently
generates a clock signal that is used as a PCI clock signal on the
secondary PCI bus 580. The secondary PCI bus 580 operates at the
same clock speed as the primary PCI bus 530, namely at a frequency
of 33 MHz.
[0070] FIG. 6 is a detailed block diagram of one embodiment of the
HIC of the present invention. As shown in FIG. 6, HIC 600 comprises
bus controller 610, translator 620, transmitter 630, receiver 640,
a PLL 650, an address/data multiplexer (AID MUX) 660, a read/write
controller (RD/WR Cntl) 670, a video serial to parallel converter
680 and a CPU control & general purpose input/output
latch/driver (CPU CNTL & GPIO latch/driver) 690.
[0071] HIC 600 is coupled to an optional flash memory BIOS
configuration unit 601. Flash memory unit 601 stores basic input
output system (BIOS) and PCI configuration information and supplies
the BIOS and PCI configuration information to A/D MUX 660 and RD/WR
Control 670, which control the programming, read, and write of
flash memory unit 601.
[0072] Bus controller 610 is coupled to the host PCI bus, which is
also referred to herein as the primary PCI bus, and manages PCI bus
transactions on the host PCI bus. Bus controller 610 includes a
slave (target) unit 611 and a master unit 616. Both slave unit 611
and master unit 616 each include two first in first out (FIFO)
buffers, which are preferably asynchronous with respect to each
other since the input and output of the two FIFOs in the master
unit 616 as well as the two FIFOs in the slave unit 611 are clocked
by different clocks, namely the PCI clock and the PCK.
Additionally, slave unit 611 includes encoder 622 and decoder 623,
while master unit 616 includes encoder 627 and decoder 628. The
FIFOs 612, 613, 617 and 618 manage data transfers between the host
PCI bus and the XPBus, which in the embodiment shown in FIG. 6
operate at 33 MHz and 66 MHz, respectively. PCI address/data (AD)
from the host PCI bus is entered into FIFOs 612 and 617 before they
are encoded by encoders 622 and 623. Encoders 622 and 623 format
the PCI address/data bits to a form more suitable for parallel to
serial conversion prior to transmittal on the XPBus. Similarly,
address and data information from the receivers is decoded by
decoders 623 and 628 to a form more suitable for transmission on
the host PCI bus. Thereafter the decoded data and address
information is passed through FIFOs 613 and 618 prior to being
transferred to the host PCI bus. FIFOs 612, 613, 617 and 618, allow
bus controller 610 to handle posted and delayed PCI transactions
and to provide deep buffering to store PCI transactions.
[0073] Bus controller 610 also comprises slave read/write control
(RD/WR Cntl) 614 and master read/write control (RD/WR Cntl) 615.
RD/WR controls 614 and 615 are involved in the transfer of PCI
control signals between bus controller 610 and the host PCI
bus.
[0074] Bus controller 610 is coupled to translator 620. Translator
620 comprises encoders 622 and 627, decoders 623 and 628, control
decoder & separate data path unit 624 and control encoder &
merge data path unit 625. As discussed above encoders 622 and 627
are part of slave data unit 611 and master data unit 616,
respectively, receive PCI address and data information from FIFOs
612 and 617, respectively, and encode the PCI address and data
information into a form more suitable for parallel to serial
conversion prior to transmittal on the XPBus. Similarly, decoders
623 and 628 are part of slave data unit 611 and master data unit
616, respectively, and format address and data information from
receiver 640 into a form more suitable for transmission on the host
PCI bus. Control encoder & merge data path unit 625 receives
PCI control signals from the slave RD/WR control 614 and master
RD/WR control 615. Additionally, control encoder & merge data
path unit 625 receives control signals from CPU CNTL & GPIO
latch/driver 690, which is coupled to the CPU and north bridge (not
shown in FIG. 6). Control encoder & merge data path unit 625
encodes PCI control signals as well as CPU control signals and
north bridge signals into control bits, merges these encoded
control bits and transmits the merged control bits to transmitter
630, which then transmits the control bits on the data lines PD0 to
PD3 and control line PCN of the XPBus. Examples of control signals
include PCI control signals and CPU control signals. A specific
example of a control signal is FRAME# used in PCI buses. A control
bit, on the other hand is a data bit that represents a control
signal. Control decoder & separate data path unit 624 receives
control bits from receiver 640 which receives control bits on data
lines PDR0 to PDR3 and control line PCNR of the XPBus. Control
decoder & separate data path unit 624 separates the control
bits it receives from receiver 640 into PCI control signals, CPU
control signals and north bridge signals, and decodes the control
bits into PCI control signals, CPU control signals, and north
bridge signals all of which meet the relevant timing
constraints.
[0075] Transmitter 630 receives multiplexed parallel address/data
(A/D) bits and control bits from translator 620 on the AD[31::0]
out and the CNTL out lines, respectively. Transmitter 630 also
receives a clock signal from PLL 650. PLL 650 takes a reference
input clock and generates PCK that drives the XPBus. PCK is
asynchronous with the PCI clock signal and operates at 66 MHz,
twice the speed of the PCI clock of 33 MHz. The higher speed is
intended to accommodate at least some possible increases in the
operating speed of future PCI buses. As a result of the higher
speed, the XPBus may be used to interface two PCI or PCI-like buses
operating at 66 MHz rather than 33 MHz or having 64 rather than 32
multiplexed address/data lines.
[0076] The multiplexed parallel A/D bits and some control bits
input to transmitter 630 are serialized by parallel to serial
converters 632 of transmitter 630 into 10 bit packets. These bit
packets are then output on data lines PD0 to PD3 of the XPBus.
Other control bits are serialized by parallel to serial converter
633 into 10 bit packets and send out on control line PCN of the
XPBus.
[0077] A 10.times. multiplier 631 receives PCK, multiplies it by a
factor of 10 and feeds a clock signal 10 times greater than PCK
into the parallel to serial converters 632 and 633. The parallel to
serial converters 632 and 633 perform bit shifting at 10 times the
PCK rate to serialize the parallel bits into 10 bit packets. As the
parallel to serial converters 632 and 633 shift bits at 10 times
the PCK rate, the bit rate for the serial bits output by the
parallel to serial converters is 10 times higher than PCK rate,
i.e., 660 MHz. However, the rate at which data packets are
transmitted on the XPBus is the same as the PCK rate, i.e., 66 MHz.
As the PCI buses operate at a clock and bit rate of 33 MHz, the
XPBus has a clock rate that is twice as large and a bit rate per
bit line (channel) that is 20 times as large as that of the PCI
buses which it interfaces.
[0078] Receiver 640 receives serial bit packets on data lines PDR0
to PDR3 and control line PCNR. Receiver 640 also receives PCKR on
the XPBus as well as the clock signal PCK from PLL 650. The
synchronizer (SYNC) 644 of receiver 640 synchronizes the clock
signal PCKR to the locally generated clock signal, PCK, in order to
capture the bits received from the XPBus into PCK clock timing.
[0079] Serial to parallel converters 642 convert the serial bit
packets received on lines PDR0 to PDR3 into parallel address/data
and control bits that are sent to decoders 623 and 628 and control
decoder and separate data path unit 624, respectively. Serial to
parallel converter 643 receives control bit packets from control
line PCNR, converts them to parallel control bits and sends the
parallel control bits to control decoder & separate data path
624.
[0080] A 10.times. multiplier 641 receives PCKR, multiplies it by a
factor of 10 and feeds a clock signal 10 times greater than PCKR
into the serial to parallel converters 642 and 643. Because the
bits on PDR0 to PDR3 and PCNR are transmitted at a bit rate of 10
times the PCKR rate, the serial to parallel converters 642 and 643
perform bit shifting at 10 times the PCKR rate to convert the 10
bit packets into parallel bits. It is to be noted that the rate at
which bit packets are transmitted on the XPBus is the same as the
PCKR rate, i.e., 66 MHz. The parallel data and control bits are
thereafter sent to decoders 623 and 628 by way of the AD[31::0] in
line and to control decoder & separate data path unit 624 by
way of CNTL in lines, respectively.
[0081] Reset control unit 645 of HIC 600 receives the signal
RESET#, which is an independent system reset signal, on the reset
line RESET#. Reset control unit 645 then transmits the reset signal
to the CPU CNTL & GPIO latch/driver unit 690.
[0082] As may be noted from the above, the 32 line host and
secondary PCI buses are interfaced by 10 XPBus lines (PD0, PD1,
PD2, PD3, PCN, PDR0, PDR1, PDR2, PDR3, PCNR). Therefore, the
interface channel, XPBus, of the present invention uses fewer lines
than are contained in either of the buses which it interfaces,
namely the PCI buses. XPBus is able to interface such PCI buses
without backup delays because the XPBus operates at a clock rate
and a per line (channel) bit rate that are higher than those of the
PCI buses.
[0083] In addition to receiving a reset signal, the CPU CNTL &
GPIO latch/driver 690 is responsible for latching input signals
from the CPU and north bridge and sending the signals to the
translator. It also takes decoded signals from the control decoder
& separate data path unit 624 and drives the appropriate
signals for the CPU and north bridge.
[0084] In the embodiment shown in FIG. 6, video serial to parallel
converter 680 is included in HIC 600. In another embodiment, video
serial to parallel converter 680 may be a separate unit from the
HIC 600. Video serial to parallel converter 680 receives serial
video data on line VPD and a video clock signal VPCK from line VPCK
of video bus 681. It then converts the serial video data into 16
bit parallel video port data and the appropriate video port control
signals, which it transmits to the graphics controller (not shown
in FIG. 6) on the video port data [0::15] and video port control
lines, respectively.
[0085] HIC 600 handles the PCI bus control signals and control bits
from the XPBus representing PCI control signals in the following
ways:
[0086] 1. HIC 600 buffers clocked control signals from the host PCI
bus, encodes them into control bits and sends the encoded control
bits to the XPBus;
[0087] 2. HIC 600 manages the signal locally; and
[0088] 3. HIC 600 receives control bits from XPBus, translates the
control bits into PCI control signals and sends the PCI control
signals to the host PCI bus.
[0089] In the default state, the HIC 600 acts as a target on the
host PCI bus. FIG. 7 is a table showing how different PCI control
signals are managed in the case where HIC 600 is a target on the
host PCI bus. However, sometimes, HIC 600 acts as the master on the
host PCI bus. FIG. 8 is a table showing how different PCI control
signals are managed when HIC 600 is a master on the host PCI bus.
In FIGS. 7 and 8, A/C and D/BE are acronyms for address/command and
data/byte enable, respectively, and S. Bus is short hand for
secondary bus. The reset signal RST is described as an independent
signal because it is asynchronous with and independent of other
clocks in the system.
[0090] In both FIGS. 7 and 8, a number of control signals have a
corresponding entry in either the HIC to XPBus or the XPBus to HIC
column but not in both. This is because these signals are
controlled by one of either the target or the master on the bus,
but not both. On the other hand, control signals with entries in
both the HIC to XPBus and XPBus to HIC columns are controlled by
both the target and the master on the bus. The parity signal PAR is
sent from the initiator on the primary PCI Bus one cycle later than
the address or data bits. In order to avoid delay in data
transmission, the appropriate PAR bit is also generated by the HIC
and sent as a control bit in the same clock cycle as the data bits
with which the PAR bit is associated. The reset signal RST is sent
on a dedicated reset line, RESET#, and, therefore, does not need to
be encoded.
[0091] When HIC 600 receives a control signal from the host PCI bus
that it must transmit to the XPBus, it samples the control signal
on the rising edge of the PCI clock, encodes the control signal
into a predesignated control bit and transmits that control bit on
either one of the data lines PD0 to PD3 or the control line PCN of
the XPBus. For example, FRAME# and IRDY# are encoded into bus
status bit 1 (BS1) and bus status bit 0 (BS0), respectively. Other
control signals, including other PCI control signals, CPU control
signals, and north bridge signals, are similarly encoded into the
desired predesignated control bits. Control bits are assigned to
each of these signals such that each signal can be identified by
its corresponding control bits.
[0092] Conversely when HIC 600 receives a bit from the XPBus that
represents a control signal, it decodes the bit into the
predesignated control signal, which may be a PCI control signal, a
CPU control signal or a north bridge signal, and sends the control
signal to the appropriate destination.
[0093] Managing control signals locally involves generating the
appropriate PCI control signal when communicating with the host PCI
bus or generating the appropriate encoded control bit when
communicating with the XPBus. For example, when HIC 600 is a target
and must send a target ready signal to the host PCI bus, i.e., send
a TRDY# signal, HIC locally generates a TRDY# signal meeting PCI
protocols and sends the TRDY# signal to the host PCI bus.
Similarly, in the case where HIC 600 needs to send a target ready
signal to the XPBus it generates the appropriate control bit
corresponding to TRDY# and transmits that control bit to the XPBus.
Thus, when communicating with the host PCI bus or the XPBus as a
target, HIC 600 locally generates a PCI control signal or a control
bit, respectively, and sends that signal to the intended
recipient.
[0094] In addition to the PCI control signals, CPU, north bridge
and south bridge signals, including CPU control signals, are also
transmitted on the XPBus. The CPU, north bridge and south bridge
signals are translated into bits that are transmitted on the XPBus.
Different CPUs may have different CPU signals. Accordingly, the
type of CPU is taken into consideration in assigning control bits
to a CPU signal such that CPU signals of different CPUs are
uniquely identified by their corresponding control bits.
[0095] FIG. 9 is a timing diagram of a PCI memory read cycle with
the HIC as a target. A memory read on the primary PCI bus is
buffered by the HIC as delayed read forwarding. As a delay
transaction, the HIC asserts DEVSEL# and STOP# at the same time to
request a retry. The HIC encodes and forwards the read transaction
through the XPBus to the PIC for processing. After some cable
delay, the PIC receives an encoded bit packet representing the read
transaction, decodes the bit packet into read transaction PCI
signals, and resynchronizes and completes the read transaction on
the secondary PCI bus. Thereafter, the PIC receives data, encodes
the received data and sends it back to the HIC through the XPBus.
When the initiator repeats the read operation on the primary PCI
bus and the data is ready in the HIC, the read operation is
completed. In the example shown in FIG. 9, the primary PCI bus
transaction takes a four clock cycle delay to bridge to the
secondary PCI bus.
[0096] FIG. 10 is a timing diagram of a PCI memory write cycle with
the HIC as a target. A memory write on the primary PCI bus is
buffered by the HIC as posted forwarding. Provided that the address
and data buffers are not full, the HIC asserts DEVSEL#, with medium
timing, and TRDY# at the same time. The TRDY# response may be
asserted by the HIC in the fast mode. The HIC supports positive
decoding with medium response time for the DEVSEL#. The HIC encodes
and forwards the write transaction through the XPBus to the PIC for
processing. After some cable delay, the PIC receives an encoded bit
packet representing the write transaction, decodes the bit packet
into a write transaction PCI signals, and resynchronizes and
completes the delayed write transaction on the secondary PCI
bus.
[0097] FIG. 11 is a detailed block diagram of one embodiment of the
PIC of the present invention. PIC 1100 is nearly identical to HIC
600 in its function, except that HIC 600 interfaces the host PCI
bus to the XPBus while PIC 1100 interfaces the secondary PCI bus to
the XPBus. Similarly, the components in PIC 1100 serve the same
function as their corresponding components in HIC 600. Reference
numbers for components in PIC 1100 have been selected such that a
component in PIC 1100 and its corresponding component in HIC 600
have reference numbers that differ by 500 and have the same two
least significant digits. Thus for example, the bus controller in
PIC 1100 is referenced as bus controller 1110 while the bus
controller in HIC 600 is referenced as bus controller 610. As many
of the elements in PIC 1100 serve the same functions as those
served by their corresponding elements in HIC 600 and as the
functions of the corresponding elements in HIC 600 have been
described in detail above, the function of elements of PIC 1100
having corresponding elements in HIC 600 will not be further
described herein. Reference may be made to the above description of
FIG. 6 for an understanding of the functions of the elements of PIC
1100 having corresponding elements in HIC 600.
[0098] As suggested above, there are also differences between HIC
600 and PIC 1100. Some of the differences between HIC 600 and PIC
1100 include the following. First, receiver 1140 in PIC 1100,
unlike receiver 640 in HIC 600, does not contain a synchronization
unit. As mentioned above, the synchronization unit in HIC 600
synchronizes the PCKR clock to the PCK clock locally generated by
PLL 650. PIC 1100 does not locally generate a PCK clock and
therefore, it does not have a locally generated PCK clock with
which to synchronize the PCK clock signal that it receives from HIC
600. Another difference between PIC 1100 and HIC 600 is the fact
that PIC 1100 contains a video parallel to serial converter 1189
whereas HIC 600 contains a video serial to parallel converter 680.
Video parallel to serial converter 1189 receives 16 bit parallel
video capture data and video control signals on the Video Port Data
[0::15] and Video Port Control lines, respectively, from the video
capture circuit (not shown in FIG. 11) and converts them to a
serial video data stream that is transmitted on the VPD line to the
HIC. The video capture circuit may be any type of video capture
circuit that outputs a 16 bit parallel video capture data and video
control signals. Another difference lies in the fact that PIC 1100,
unlike HIC 600, contains a clock doubler 1182 to double the video
clock rate of the video clock signal that it receives. The doubled
video clock rate is fed into video parallel to serial converter
1182 through buffer 1183 and is sent to serial to parallel
converter 680 through buffer 1184. Additionally, reset control unit
1135 in PIC 1100 receives a reset signal from the CPU CNTL &
GPIO latch/driver unit 1190 and transmits the reset signal on the
RESET# line to the HIC 600 whereas reset control unit 645 of HIC
600 receives the reset signal and forwards it to its CPU CNTL &
GPIO latch/driver unit 690 because, in the above embodiment, the
reset signal RESET# is unidirectionally sent from the PIC 1100 to
the HIC 600.
[0099] Like HIC 600, PIC 1100 handles the PCI bus control signals
and control bits from the XPBus representing PCI control signals in
the following ways:
[0100] 1. PIC 1100 buffers clocked control signals from the
secondary PCI bus, encodes them and sends the encoded control bits
to the XPBus;
[0101] 2. PIC 1100 manages the signal locally; and
[0102] 3. PIC 1100 receives control bits from XPBus, translates
them into PCI control signals and sends the PCI control signals to
the secondary PCI bus.
[0103] PIC 1100 also supports a reference arbiter on the secondary
PCI Bus to manage the PCI signals REQ# and GNT#.
[0104] FIGS. 12 and 13 are tables showing how PCI control signals
are managed in the cases when PIC 600 is a target and master (a
default condition), respectively, on the secondary PCI bus.
[0105] FIG. 14 shows a schematic diagram of the connectors used to
couple the HIC and PIC of the present invention. HIC 1400 has a
male connector 1405 with pins 1410 while PIC 1450 has a female
connector 1455 with pinholes 1460 for accepting pins 1410 when
connectors 1405 and 1455 are engaged. In a preferred embodiment,
the male and female connectors 1405 and 1455 are designed to
withstand numerous engagements and disengagements. In that respect,
the connectors preferably comply with industry standard drive bay
connector specifications. Note that although FIG. 14 shows HIC 1400
and PIC 1450 with a male connector and a female connector,
respectively, in another embodiment, HIC 1400 and PIC 1450 may have
a female connector and a male connector, respectively.
[0106] In the embodiment shown in FIG. 14, the connectors on the
HIC and PIC engage with one another directly. However, in another
embodiment, such as that shown in FIG. 15, the connectors on the
HIC and PIC do not directly engage with one another. In the
embodiment shown in FIG. 15, an extension cord 1580 having cable
1583 and connectors 1581 and 1582 disposed at the ends of cable
1583, is used to couple the connectors 1505 and 1555 on the HIC
1500 and PIC 1550, respectively.
[0107] The interfaces of the present invention comprising an HIC, a
PIC and the link between the HIC and PIC, either with or without an
extension cord such as extension cord 1580 in FIG. 15, may be used
to interface an ACM and a peripheral console. Moreover, the
embodiment of the interface of the present invention having an
extension cord, such as that disclosed in FIG. 15, may be used to
interface two computer systems. Therefore, the interface of the
present invention has broader application than that of interfacing
an ACM and a peripheral console.
[0108] In one embodiment, the connectors may be limited to pins for
transmitting PCI related signals. In such an embodiment, the cable
would consist of conductive lines on the XPBus. In another
embodiment, however, the connectors may include pins for
transmitting video and/or power related signals in addition to the
PCI related signals, in which case, the cable would have conductive
lines for the video bus and/or power bus.
[0109] FIG. 16 is a schematic diagram of the rear view of an ACM
showing both peripheral connector 1605 and video connector 1610.
The peripheral connector 1605 provides peripheral signals whereas
the video connector 1610 provides video signals. Power lines are
provided within both the peripheral connector 1605 and the video
connector 1610.
[0110] FIG. 17 shows a schematic diagram of the pin out of
peripheral connector 1605 and video connector 1610. Pins for lines
PD0 to PD3, PCK and PCN are on the same side of the connector.
Similarly, the pins for lines PDR0 to PDR3, PCKR and PCNR are all
on the same side of the connector. Lines transmitting information
in the same direction are placed on the same side of the connector
in order to match delay between these related lines and to avoid
slew.
[0111] FIGS. 18 and 19 are tables including the pin number, symbol,
signal, standard and description for the pins on the peripheral and
video connectors, respectively. FIG. 20 is a table showing the
symbols, signals, data rate and description of signals on the
XPBus, where RTN indicates a ground (GND) reference. In the above
tables, P&D stands for plug and display and is a trademark of
the Video Electronics Standards Association (VESA) for the Plug and
Display standard, DDC2:SCL and DDC2:SDA stand for the VESA display
data channel (DDC) standard 2 clock and data signals, respectively,
SV stands for super video, V33 is 3.3 volts, and V5 is 5.0 volts.
TMDS stands for Transition Minimized Differential Signaling and is
a trademark of Silicon Images and refers to their Panel Link
technology, which is in turn a trademark for their LVDS technology.
TMDS is used herein to refer to the Panel Link technology or
technologies compatible therewith.
[0112] The video connector 1610 provides 3 types of video output,
DDC2 support, video port, 6 pins of 3.3 volt power, and 14 pins for
ground. The 3 types of video output include (1) analog RGB (Red
Green Blue) for a color monitor, (2) VESA Plug and Display's TMDS
signals for flat panel displays, and (3) signals for TV and S-video
(super video). In one embodiment, the video port is supported with
two LVDS lines, namely VPCK and VPD, which are used for video clock
and video data, respectively.
[0113] FIG. 21 is a table showing the information transmitted on
the XPBus during two clock cycles of the XPBus in one embodiment of
the present invention where 10 data bits are transmitted in each
clock cycle of the XPBus. In FIG. 21, A00 to A31 represent 32 bits
of PCI address A[31::0], D00 to D31 represent 32 bits of PCI data
D[31::0], BS0 to BS3 represent 4 bits of bus status data indicating
the status of the XPBus, CM0# to CM3# represent 4 bits of PCI
command information, BE0# to BE3# represent 4 bits of PCI byte
enable information, and CN0 to CN9 represent 10 bits of control
information sent in each clock cycle. As shown in FIG. 21, for each
of lines PD0 to PD3, the 10 bit data packets contain one BS bit,
one CM/BE bit, and eight A/D bits. For the PCN line, the 10 bit
data packet contains 10 CN bits. The first clock cycle shown in
FIG. 21 comprises an address cycle in which 4 BS bits, 4 CM bits,
32 A bits and 10 CN bits are sent. The second clock cycle comprises
a data cycle in which 4 BS bits, 4 BE bits, 32 D bits and 10 CN
bits are sent. The bits transmitted on lines PD0 to PD3 represent
32 PCI AD[31::0] signals, 4 PCI C/BE# [3::0] signals, and part of
the function of PCI control signals, such as FRAME#, IRDY#, and
TRDY#.
[0114] In the embodiment shown in FIG. 21, BS0 to BS3 are sent at
the beginning of each clock cycle. The bus status bits indicate the
following bus cycle transactions: idle, address transfer, write
data transfer, read data transfer, switch XPBus direction, last
data transfer, wait, and other cycles.
[0115] Bits representing signals transmitted between the CPU and
South Bridge may also be sent on the lines interconnecting the HIC
and PIC, such as lines PCN and PCNR. For example, CPU interface
signals such as CPU interrupt (INTR), Address 20 Mask (A20M#),
Non-Maskable Interrupt (NMI), System Management Interrupt (SMI#),
and Stop Clock (STPCLK#), may be translated into bit information
and transmitted on the XPBus between the HIC and the PIC.
[0116] FIG. 22 is a table showing the information transmitted on
the XPBus during four clock cycles of the XPBus in another
embodiment of the present invention where 10 data bits are
transmitted in each clock cycle of the XPBus. In this embodiment,
the XPBus clock rate is twice as large as the PCI clock rate. This
allows sending data and address bits every other XPBus cycle. As
can be seen in FIG. 22, there are no address or data bits
transmitted during the second or fourth XPBus clock cycle. The fact
that the XPBus clock rate is higher than the PCI clock rate allows
for compatibility of the XPBus with possible future expansions in
the performance of PCI bus to higher data transfer and clock
rates.
[0117] In the embodiment shown in FIG. 22, there are 18 control
bits, CN0 to CN17, transmitted in every two XPBus clock cycles. The
first bit transmitted on the control line in each XPBus clock cycle
indicates whether control bits CN0 to CN8 or control bits CN9 to
CN17 will be transmitted in that cycle. A zero sent at the
beginning of a cycle on the control line indicates that CN0 to CN8
will be transmitted during that cycle, whereas a one sent at the
beginning of a cycle on the control line indicates that CN9 to CN17
will be transmitted during that cycle. These bits also indicate the
presence or absence of data and address bits during that cycle. A
zero indicates that address or data bits will be transmitted during
that cycle whereas a one indicates that no address or data bits
will be transmitted during that cycle.
[0118] In one embodiment, BS0 and BS1 are used to encode the PCI
signals FRAME# and IRDY#, respectively. Additionally, in one
embodiment, BS2 and BS3 are used to indicate the clock speed of the
computer bus interface and the type of computer bus interface,
respectively. For example, BS2 value of zero may indicate that a 33
MHz PCI bus of 32 bits is used whereas a BS2 value of one may
indicate that a 66 MHz PCI bus of 32 bits is used. Similarly, a BS3
value of zero may indicated that a PCI bus is used whereas a BS3
value of one may indicated that another computer interface bus,
such as an Institute of Electronics & Electrical Engineers
(IEEE) 1394 bus, is used.
[0119] FIG. 23 is a schematic diagram of lines PCK, PD0 to PD3, and
PCN. These lines are unidirectional LVDS lines for transmitting
clock signals and bits such as those shown in FIGS. 21 and 22 from
the HIC to the PIC. The bits on the PD0 to PD3 and the PCN lines
are sent synchronously within every clock cycle of the PCK. Another
set of lines, namely PCKR, PDR0 to PDR3, and PCNR, are used to
transmit clock signals and bits from the PIC to HIC. The lines used
for transmitting information from the PIC to the HIC have the same
structure as those shown in FIG. 23, except that they transmit data
in a direction opposite to that in which the lines shown in FIG. 23
transmit data. In other words they transmit information from the
PIC to the HIC. The bits on the PDR0 to PDR3 and the PCNR lines are
sent synchronously within every clock cycle of the PCKR. Some of
the examples of control information that may be sent in the reverse
direction, i.e., on PCNR line, include a request to switch data bus
direction because of a pending operation (such as read data
available), a control signal change in the target requiring
communication in the reverse direction, target busy, and
transmission error detected.
[0120] The XPBus which includes lines PCK, PD0 to PD3, PCN, PCKR,
PDR0 to PDR3, and PCNR, has two sets of unidirectional lines
transmitting clock signals and bits in opposite directions. The
first set of unidirectional lines includes PCK, PD0 to PD3, and
PCN. The second set of unidirectional lines includes PCKR, PDR0 to
PDR3, and PCNR. Each of these unidirectional set of lines is a
point-to-point bus with a fixed transmitter and receiver, or in
other words a fixed master and slave bus. For the first set of
unidirectional lines, the HIC is a fixed transmitter/master whereas
the PIC is a fixed receiver/slave. For the second set of
unidirectional lines, the PIC is a fixed transmitter/master whereas
the HIC is a fixed receiver/slave. The LVDS lines of XPBus, a cable
friendly and remote system I/O bus, transmit fixed length data
packets within a clock cycle.
[0121] The XPBus lines, PD0 to PD3, PCN, PDR0 to PDR3 and PCNR, and
the video data and clock lines, VPD and VPCK, are not limited to
being LVDS lines, as they may be other forms of bit based lines.
For example, in another embodiment, the XPBus lines may be IEEE
1394 lines.
[0122] It is to be noted that although each of the lines PCK, PD0
to PD3, PCN, PCKR, PDR0 to PDR3, PCNR, VPCK, and VPD is referred to
as a line, in the singular rather than plural, each such line may
contain more than one physical line. For example, in the embodiment
shown in FIG. 23, each of lines PCK, PD0 to PD3 and PCN includes
two physical lines between each driver and its corresponding
receiver. The term line, when not directly preceded by the terms
physical or conductive, is herein used interchangeably with a
signal or bit channel which may consist of one or more physical
lines for transmitting a signal. In the case of non-differential
signal lines, generally only one physical line is used to transmit
one signal. However, in the case of differential signal lines, a
pair of physical lines is used to transmit one signal. For example,
a bit line or bit channel in an LVDS or IEEE 1394 interface
consists of a pair of physical lines which together transmit a
signal.
[0123] A bit based line (i.e., a bit line) is a line for
transmitting serial bits. Bit based lines typically transmit bit
packets and use a serial data packet protocol. Examples of bit
lines include an LVDS line, an IEEE 1394 line, and a Universal
Serial Bus (USB) line.
[0124] FIG. 24 is a block diagram of another embodiment of the HIC
and PIC of the present invention and the interface therebetween.
One important difference between the XPBuses shown in FIGS. 5 and
24 is the fact that unlike the XPBus of FIG. 5, the XPBus of FIG.
24 does not have control lines PCN and PCNR. Another difference
lies in the fact that the XPBus of FIG. 24 has two dedicated reset
lines RSTEH# and RSTEP# instead of only one as is the case for the
XPBus of FIG. 5. RSTEH# and RSTEP# are unidirectional reset and
error condition signal lines that transmit a reset and error
condition signal from the host PCI to the peripheral PCI and from
the peripheral PCI to host PCI, respectively.
[0125] In one embodiment, each of reset lines RSTEH#, RSTEP#, and
RESET# (shown in FIG. 5), is preferably a non-differential signal
line consisting of one physical line. In other embodiments, one or
more of the above lines may be a differential signal line having
more than one physical line.
[0126] FIGS. 25 shows a detailed block diagrams of the HIC shown in
FIG. 24. HIC 2500 shown in FIG. 25 is, other than for a few
difference, identical to HIC 600 shown in FIG. 6. Accordingly,
reference numbers for components in HIC 2500 have been selected
such that a component in HIC 2500 and its corresponding component
in HIC 600 have reference numbers that differ by 1900 and have the
same two least significant digits. One of the differences between
HIC 2500 and HIC 600 is the fact that, unlike HIC 600, HIC 2500
does not have a parallel to serial converter or a serial to
parallel converter dedicated exclusively to CNTL out and CNTL in
signals, respectively. This is due to the fact that XPBus for HIC
2500 does not contain a PCN or PCNR line. Another important
difference between HIC 2500 and HIC 600 is the fact that HIC 2500,
unlike HIC 600, has two reset lines, RSTEP# and RSTEH#, instead of
only one reset line. Reset line RSTEP# is coupled to Reset &
XPBus Parity Error Control Unit 2536 which receives, on the reset
line RSTEP#, a reset signal and a parity error signal generated by
the PIC, sends a reset signal to the CPU CNTL & GPIO
latch/driver 2590, and controls retransmission of bits from the
parallel to serial converters 2532. Reset & XPBus Parity Error
Detection and Control Unit 2546 takes bits from serial to parallel
converters 2542, performs a parity check to detect any transmission
error, and sends reset and parity error signals to the PIC on the
reset line RSTEH#. The reset and parity error signals may be
distinguished by different signal patterns and/or different signal
durations. In the two reset line system, the reset and error parity
signals are transmitted on the same line and it is possible to send
a parity error confirmation signal on one line while receiving a
reset signal on the other line. Because HIC 2500 provides for
parity error detection, the parallel to serial converters 2532
include buffers. The buffers in parallel to serial converters 2532
store previously transmitted bits (e.g., those transmitted within
the previous two clock cycles) for retransmission if transmission
error is detected and a parity error signal is received on line
RSTEP#. It is to be noted that parallel to serial converters 632 do
not contain buffers such as those contained in parallel to serial
converters 2532 for purposes of retransmission since HIC 600 does
not provide for parity error signal detection. Yet another
difference between HIC 600 and HIC 2500 is the fact that in HIC
2500 clock multipliers 2531 and 2541 multiply the PCK and PCKR
clocks, respectively, by a factor of 6 rather than 10 because the
XPBus coupled to HIC 2500 transmits six bit packets instead of ten
bit packets during each XPBus clock cycle. Sending a smaller number
of bits per XPBus clock cycle provides the benefit of improving
synchronization between the data latching clock output by clock
multipliers 2531 and 2541 and the XPBus clocks, PCK and PCKR. In
another embodiment, one may send 5 or some other number of bits per
XPBus clock cycle. As mentioned above, the remaining elements in
HIC 2500 are identical to those in HIC 600 and reference to the
description of the elements in HIC 600 may be made to understand
the function of the corresponding elements in HIC 2500.
[0127] FIG. 26 shows a detailed block diagrams of the PIC shown in
FIG. 24. PIC 2600 is, but for the differences discussed above
between HICs 2500 and 600, identical to PIC 1100. Accordingly,
reference numbers for components in PIC 2600 have been selected
such that a component in PIC 2600 and its corresponding component
in PIC 1100 have reference numbers that differ by 1500 and have the
same two least significant digits. Reference may be made to (1) the
description above of PIC 1100 and (2) the discussion above of the
differences between HICs 600 and 2500 for a full understanding of
the elements of PIC 2600. With respect to Reset & XPBus Parity
Error Control Unit 2636 and Reset & XPBus Parity Error
Detection & Control Unit 2646, it is to be noted that they
serve the same type of functions as those performed by Reset &
XPBus Parity Error Control Unit 2536 and Reset & XPBus Parity
Error Detection & Control Unit 2546, respectively, except that
Reset & XPBus Parity Error Control Unit 2636 receives a reset
and parity error signal on reset line RSTEH# instead of RSTEP# and
Reset & XPBus Parity Error Detection & Control Unit 2646
sends a reset and parity error signal on RSTEP# instead of
RSTEH#.
[0128] FIG. 27 is a schematic diagram of the rear view of an ACM
using an HIC, such as HIC 2500, showing both peripheral connector
2705 and video/extension connector 2710. The peripheral connector
2705 provides peripheral signals whereas the video/extension
connector 2710 provides video signals. Power lines are provided
within both the peripheral connector 2705 and the video/extension
connector 2710.
[0129] FIG. 28 shows a schematic diagram of the pin out of
peripheral connector 2705 and video/extension connector 2710. In
FIG. 28, TPA and TPB stand for twisted pair A and twisted pair B,
respectively, which are both IEEE 1394 standards, V12 symbolizes 12
volts, and E pins are extension pins. In embodiments which do not
use a flat panel screen or IEEE 1394 standard buses, the E pins are
not necessary and may be omitted. In cases where E pins are not
necessary, the pins are omitted to reduce cost on a connector or
cabling that would otherwise be needed. The video/extension
connector 2710 provides 3 types of video output, DDC2 support,
video port, 9 pins of 3.3 volt power, 3 pins for 5 volt power, 3
pins for 12 volt power, and 9 pins for ground. The 3 types of video
output include (1) analog RGB (Red Green Blue) for a color monitor,
(2) VESA Plug and Display's TMDS signals for flat panel displays,
and (3) signals for TV and S-video (super video). The video port is
supported with two LVDS lines VPCK and VPD used for video clock and
video data, respectively.
[0130] FIGS. 29 is a table including the pin number, symbol,
signal, standard and description for the pins on the peripheral
connector. FIG. 30 is a table showing the pin number, symbol,
signal, standard and description for the pins on the
video/extension connector. FIG. 31 is a table showing the symbols,
signals, data rate and description of signals on the XPBus.
[0131] FIG. 32 is a schematic diagram of the lines PCK and PD0 to
PD3. These lines are unidirectional LVDS lines for transmitting
signals from HIC 2500 to PIC 2600. Another set of lines, namely
PCKR and PDR0 to PDR3, are used to transmit clock signals and bits
from PIC 2600 to HIC 2500. The lines used for transmitting
information from PIC 2600 to HIC 2400 have the same structure as
those shown in FIG. 33, except that they transmit information in
the opposite direction from that of those shown in FIG. 32. In
other words they transmit information form the PIC to the HIC.
[0132] FIGS. 33 and 34 are tables showing the data packet types
transmitted from HIC 2500 to PIC 2600 and from PIC 2600 to HIC
2500, respectively. Each data packet consists of six nibbles, a
first nibble to a sixth nibble, where each nibble consists of four
bits. The four bits in a nibble transmitted from the HIC to the PIC
are simultaneously transmitted on lines PD0 to PD3. Similarly, the
four bits in a nibble transmitted from the HIC to the PIC are
simultaneously transmitted on lines PDR0 to PDR3. The first and
second nibbles in each data packet carry control information while
the third to sixth nibbles carry address, data and/or control
information. For example, data packet type HMA1/HMD1 (host master
address first segment/host master data first segment), has XX00
(where X represents an either a 0 or a 1 bit) and C/BE in the first
and second nibbles, respectively, and PCI A/D first segment in the
third to sixth nibbles. Similarly, data packet type HTD1 (host
target data first segment) has XX00 and BE in the first and second
nibbles, respectively, and PCI D first segment in the third to
sixth nibbles.
[0133] Each of lines PD0 to PD3 and PDR0 to PDR3 transmits 6 bits
in a clock cycle of 132 MHz. For each 32 bit address or data PCI
bus transmission, two consecutive data packets are used. A total of
12 control bits, 4 C/BE bits, and 32 address/data bits are sent in
the two consecutive data packets. For an address cycle, each packet
includes 4 bits of Bus Status information, 4 bits of Command
information, and 32 bits of address information. For a data cycle,
each packet includes 4 bits of Bus Status information, 4 bits of
Byte Enable information, and 32 bits of data information. The bits
transmitted on lines PD0 to PD3 represent 32 PCI AD[31::0] signals,
4 PCI C/BE# [3::0] signals, and part of the function of PCI control
signals, such as FRAME#, IRDY#, and TRDY#.
[0134] Since PCK and PCKR have a clock rate of 132 MHz and two
clock cycles are used for transmitting the bits representing each
PCI bus transmission, the XPBus transmits the bits representing
each PCI bus transmission at twice the speed of a 33 MHz PCI bus.
This allows for using the XPBus with future expansions to either
higher performance PCI bus or other data transfer modes.
[0135] HMA1 and HMA2 stand for host master address first segment
and host master address second segment, respectively; HMD1 and HMD2
stand for host master data first segment and host master data
second segment, respectively; HMC1 and HMC2 stand for host master
control first segment and host master control second segment,
respectively; HTD1 and HTD2 stand for host target data first
segment and host target data second segment, respectively; HTC1 and
HTC2 stand for host target control first segment and host target
control second segment, respectively; PMA1 and PMA2 stand for
peripheral master address first segment and peripheral master
address second segment, respectively; PMD1 and PMD2 stand for
peripheral master data first segment and peripheral master data
second segment, respectively; PMC1 and PMC2 stand for peripheral
master control first segment and peripheral master control second
segment, respectively; PTD1 and PTD2 stand for peripheral target
data first segment and peripheral target data second segment,
respectively; PTC1 and PTC2 stand for peripheral target control
first segment and peripheral target control second segment,
respectively; Resvd stands for reserved; and NOOP stands for
no-operation. HMA1/HMD1, HMA2/HMD2, HTD1, HTD2, PMA1/PMD1,
PMA2/PMD2, PTD1, and PTD2 each contain PCI control information in
the first and second nibbles and PCI A/D in the third to sixth
nibbles. Similarly, HMC1, HMC2, HTC1, HTC2, PMC1, PMC2, PTC1, and
PTC2 each contain either PCI or non-PCI control information, such
as CPU control signals, GPIO control signals, north bridge signals,
etc., in all six nibbles, first nibble to sixth nibble. The
reserved data packet types can be used to support non-PCI bus
transactions, e.g., USB transactions. The NOOP data packet type
indicates that there is no new information being transferred on the
XPBus. In a preferred embodiment, the NOOP data packet type is
transmitted when the control bits do not change from one clock
cycle to the next. When the control bits change between clock
cycles, then some data packet type other than NOOP is transmitted
on the XPBus.
[0136] The bits sent in the first nibble of each data packet
indicate the type of that data packet. FIG. 35 is a table showing
different types of first nibbles and their corresponding data
packet types.
[0137] FIG. 36 shows the six nibbles of data packet types HMA1/HMD1
and HMA2/HMD2 sent on lines PD0 to PD3 from the HIC to the PIC. In
a preferred embodiment, the XPBus PCI master data packets occur in
pairs as HMA1 and HMA2 or HMD1 and HMD2. The XPBus PCI master data
packet is identified with the bits sent on lines PD2 and PD3 of the
1st control/ID nibble. The XPBus PCI master data packet definition
is the same for HIC to PIC and PIC to HIC transfers. The first
nibble in HMA1/HMD1 includes FRAME#, IRDY#, 0 (signifying a first
address/data segment), and 0 or 1 (where 0 signifies PCI and 1
signifies some other bus), which are sent on lines PD0, PD1, PD2,
and PD3, respectively. The second nibble in HMA1/HMD1 includes
C/BEO#, C/BE1#, C/BE2#, and C/BE3#, which are sent on lines PD0,
PD1, PD2, and PD3, respectively. The third nibble in HMA1/HMD1
includes A/D0, A/D8, A/D16, and A/D24, which are sent on lines PD0,
PD1, PD2, and PD3, respectively. The fourth nibble in HMA1/HMD1
includes A/D1, A/D9, A/D17, and A/D25, which are sent on lines PD0,
PD1, PD2, and PD3, respectively. The fifth nibble in HMA1/HMD1
includes A/D2, A/D10, A/D18, and A/D26, which are sent on lines
PD0, PD1, PD2, and PD3, respectively. The sixth nibble in HMA1/HMD1
includes A/D3, A/D11, A/D19, and A/D27, which are sent on lines
PD0, PD1, PD2, and PD3, respectively. Similarly, the first nibble
in HMA2/HMD2 includes PAR(PCI), LOCK#, 1 (signifying a second
address/data segment), and 0 or 1 (where a 0 signifies PCI and 1
signifies some other bus), which are sent on lines PD0, PD1, PD2,
and PD3, respectively. The second nibble in HMA2/HMD2 includes
GNT#, a first reserved bit, a second reserved bit, and Cntl PAR
(XIS), which are sent on lines PD0, PD1, PD2, and PD3,
respectively. The third nibble in HMA2/HMD2 includes A/D4, A/D12,
A/D20, and A/D28, which are sent on lines PD0, PD1, PD2, and PD3,
respectively. The fourth nibble in HMA2/HMD2 includes A/D5, A/D13,
A/D21, and A/D29, which are sent on lines PD0, PD1, PD2, and PD3,
respectively. The fifth nibble in HMA2/HMD2 includes A/D6, A/D14,
A/D22, and A/D30, which are sent on lines PD0, PD1, PD2, and PD3,
respectively. The sixth nibble in HMA2/HMD2 includes A/D7, A/D15,
A/D23, and A/D 31, which are sent on lines PD0, PD1, PD2, and PD3,
respectively.
[0138] FIG. 37 is a table that shows the six nibbles of data packet
types PMA1/PMD1 and PMA2/PMD2 sent on lines PD0 to PD3 from the PIC
to the HIC. In response to receiving the data packet types shown in
FIG. 37 from a master, the target has to send back a read data
packet to the master. FIG. 38 is a table showing a PCI target read
data packet for both HIC to PIC and PIC to HIC and includes the six
nibbles for data packet types HTD1/PTD1 and HTD2/PTD2.
[0139] FIG. 39 is a table that shows an example of a PCI read data
packet transaction with the HIC as master and the PIC as target.
FIG. 40 is a table that shows an example of a PCI write data packet
transaction with the HIC as master and the PIC as target.
[0140] After a PCI master data packet is sent from the HIC to the
PIC, only one of two control packets needs to be sent from the PIC
to the HIC as a PCI target response. If any control bit within the
control packet has changed, then the control packet must be sent.
If no control bit within the control packet has changed, the
default data packet to be sent will alternate between the first
control segment and the second control segment. FIG. 41 is a table
that shows PCI target control data packets sent from the PIC to the
HIC on the XPBus with PCI response. FIG. 42 is a table that shows
PCI target control data packets sent from the PIC to the HIC on the
XPBus without PCI response. In FIGS. 41 and 42, ID (PTC1) and ID
(PTC2) indicate a first target control segment and a second target
control segment, respectively.
[0141] Similarly, after a PCI target data packet is sent from the
HIC to the PIC, only one of two control packets needs to be sent
from the PIC to the HIC as a PCI master response. If any control
bit within the control packet has changed, then the control packet
must be sent. If no control bit within the control packet has
changed, then the default data packet to be sent will be the first
control segment. FIG. 43 is a table that shows PCI master control
data packets sent from the PIC to the HIC on the XPBus with PCI
response. FIG. 44 is a table that shows PCI master control data
packets sent from the PIC to the HIC on the XPBus without PCI
response. In FIGS. 43 and 44, ID (PMC1) and ID (PMC2) indicate a
first master control segment and a second master control segment,
respectively.
[0142] FIGS. 45 and 46 are tables that show the HIC to PIC target
control data packet and master control data packet,
respectively.
[0143] FIG. 47 is a table showing the names, types, number of pins
dedicated to, and the description of the primary bus PCI signals.
The pins represent those between the host PCI bus and the HIC. FIG.
48 is a table showing the names, types, number of pins dedicated
to, and the description of the XPBus signals. The pins in this case
are those between the HIC and the PIC. FIGS. 49 and 50 are tables
showing the names, types, number of pins dedicated to, and the
description of the XIS bus video port signals and the video port
signals, respectively. The pins for the XIS bus video port signals
are features that are optionally supported between the HIC and the
PIC whereby the video port signals are bridged between the
peripheral console and the ACM. FIG. 51 is a table showing the
names, types, number of pins dedicated to, and the description of
the flash memory interface signals. There are pins for the flash
memory interface between the flash memory unit for the HIC and the
HIC as well as some between the flash memory unit for the PIC and
the PIC. FIG. 52 is a table showing the names, types, number of
pins dedicated to, and the description of the test port Joint Test
Access Group (JTAG) signals. JTAG is herein used as a shorthand for
the IEEE JTAG/1149.1 Standard. The JTAG pins are connected to
devices which support JTAG, e.g., the CPU, to test those devices
during the process of manufacturing a system comprising such
devices. As the JTAG pins are used only for testing during the
manufacturing process, they are not shown in the other figures that
deal with post testing situations. FIG. 53 is a table showing the
names, types, number of pins dedicated to, and the description of
the CPU signals. The CPU signal pins are between the CPU and the
HIC. FIG. 54 is a table showing the names, types, number of pins
dedicated to, and the description of the north bridge signals. The
north bridge signal pins are between the north bridge and the HIC.
FIG. 55 is a table showing the names, types, number of pins
dedicated to, and the description of the GPIO signals. The GPIO
signal pins are between the GPIO and the HIC. FIG. 56 is a table
showing the names, types, number of pins dedicated to, and the
description of the error/reset signals. The pins for the
error/reset signals are between the HIC and the PIC and are part of
the XPBus. They are shown separately from the XPBus signals shown
in FIG. 48 because they serve a considerably different purpose than
those in FIG. 48. FIG. 57 is a table showing the names, types,
number of pins dedicated to, and the description of the
power/ground/oscillator input signals. The pin for OSCin is between
a reference clock and the PLL. The pins GND(PLL) and VCC(PLL) are
for the phase lock loop. The pins VCC (core) and GND(core) are for
the core circuitry of the HIC. The pins VCC(LVDS) and GND(LVDS) are
for the LVDS lines (PD0 to PD3, PCN, PDR0 to PDR3, and PCNR lines).
The pin VCC(VP) is for the video port. The pins VCC(PCI) and
GND(PCI) are for the PCI lines. The pins VCC(flash) and GND(flash)
are for the flash memories. It is to be noted that the video port
does not have a dedicated ground pin. The video port may share a
ground pin with other devices to reduce the number of pins used.
For example, it may share GND(flash) with the flash memories. The
PCI lines and flash memories are driven by devices that source
current from VCC(PCI) and VCC(flash), respectively, and which sink
current to GND(PCI) and GND(flash), respectively.
[0144] While the present invention has been particularly described
with respect to the illustrated embodiments, it will be appreciated
that various alterations, modifications and adaptations may be made
based on the present disclosure, and are intended to be within the
scope of the present invention. While the invention has been
described in connection with what are presently considered to be
the most practical and preferred embodiments, it is to be
understood that the present invention is not limited to the
disclosed embodiments but, on the contrary, is intended to cover
various modifications and equivalent arrangements included within
the scope of the appended claims.
* * * * *