U.S. patent application number 09/115652 was filed with the patent office on 2001-07-26 for integrated circuit device and method and apparatus for inspecting the same.
Invention is credited to SATOH, SHUJI.
Application Number | 20010010083 09/115652 |
Document ID | / |
Family ID | 16270729 |
Filed Date | 2001-07-26 |
United States Patent
Application |
20010010083 |
Kind Code |
A1 |
SATOH, SHUJI |
July 26, 2001 |
INTEGRATED CIRCUIT DEVICE AND METHOD AND APPARATUS FOR INSPECTING
THE SAME
Abstract
An integrated circuit device can be inspected in various ways
while it is being installed on a circuit board. A bus control unit
connects an external memory to a central processing unit in a
normal mode. In an inspection mode, the bus control unit connects
an inspection control circuit, which has a plurality of registers
for temporarily storing instruction codes and data to be processed
from an external circuit inspection device, to the central
processing unit at a suitable time. When the instruction codes and
data from the external circuit inspection are stored in the
registers of the inspection control circuit, the central processing
unit can be inspected while it is effecting a desired data
processing operation.
Inventors: |
SATOH, SHUJI; (TOKYO,
JP) |
Correspondence
Address: |
MCGINN & GIBB
1701 CLARENDON BOULEVARD SUITE 100
ARLINGTON
VA
22209
|
Family ID: |
16270729 |
Appl. No.: |
09/115652 |
Filed: |
July 15, 1998 |
Current U.S.
Class: |
714/30 ; 714/35;
714/38.13; 714/E11.168 |
Current CPC
Class: |
G06F 11/261
20130101 |
Class at
Publication: |
714/30 ; 714/35;
714/38 |
International
Class: |
G06F 011/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 16, 1997 |
JP |
191209/1997 |
Claims
What is claimed is:
1. An integrated circuit device comprising: a central processing
unit for reading instruction codes and data to be processed and
executing data processing tasks based on the read instruction codes
and data to be processed; an external bus for being connected to an
external information storage medium which stores instruction codes
and data to be processed; an inspection information interface for
detachable connection to an external circuit inspection device; an
inspection control circuit connected to said inspection information
interface and having a plurality of registers for temporarily
storing instruction codes and data to be processed which are
supplied from said external circuit inspection device; and a bus
control unit for selectively connecting said external bus and said
inspection control circuit to said central processing unit; said
bus control unit having an operation mode switchable between a
normal mode and an inspection mode, and means for connecting said
external bus continuously to said central processing unit in the
normal mode and switching a destination to be connected to said
central processing unit from said external bus to said inspection
control circuit in said inspection mode when the address of an
access destination issued by said central processing unit agrees
with the predetermined address of one of the registers of said
inspection control circuit.
2. An integrated circuit device according to claim 1, wherein said
registers of the inspection control circuit include: an instruction
code register for temporarily storing an instruction code for
instructing said central processing unit to effect a predetermined
data processing operation; a data register for temporarily storing
data to be processed by said central processing unit based on said
instruction code stored by said instruction code register; and a
return instruction code register for temporarily storing an
instruction code to return an access destination for said central
processing unit to said instruction code register.
3. An integrated circuit device according to claim 1, wherein said
registers of the inspection control circuit include: an instruction
code register for temporarily storing an instruction code for
instructing said central processing unit to effect a predetermined
data processing operation; a data register for temporarily storing
data to be processed by said central processing unit based on said
instruction code stored by said instruction code register; and a
return instruction code register permanently storing a
predetermined instruction code to return an access destination for
said central processing unit to said instruction code register.
4. A method of inspecting an integrated circuit device according to
claim 2, comprising the steps of: storing the instruction code for
the predetermined data processing operation in said instruction
code register; storing the data to be processed by said central
processing unit in said data register; storing the instruction code
to return the access destination in said return instruction code
register; updating the instruction code stored in said instruction
code register and the data stored in said data register when said
central processing unit effects the predetermined data processing
operation based on said instruction code stored in said instruction
code register and said data stored in said data register; and
returning the access destination of said central processing unit to
said instruction code register based on said instruction code
stored in said return instruction code register.
5. A method of inspecting an integrated circuit device according to
claim 3, comprising the steps of: storing the instruction code for
the predetermined data processing operation in said instruction
code register; storing the data to be processed by said central
processing unit in said data register; updating the instruction
code stored in said instruction code register and the data stored
in said data register when said central processing unit effects the
predetermined data processing operation based on said instruction
code stored in said instruction code register and said data stored
in said data register; and returning the access destination of said
central processing unit to said instruction code register based on
said instruction code stored in said return instruction code
register.
6. An apparatus for an inspecting an integrated circuit device
according to claim 2, comprising: a connector detachably connected
to said inspection information interface; instruction code storing
means for storing said instruction code for instructing said
central processing unit to effect the predetermined data processing
operation from said connector through said inspection information
interface into said instruction code register; data storing means
for storing the data to be processed from said connector through
said inspection information interface into said data register; and
return instruction code storing means for storing said instruction
code to return the access destination from said connector through
said inspection information interface into said return instruction
code register.
7. An apparatus for an inspecting an integrated circuit device
according to claim 3, comprising: a connector detachably connected
to said inspection information interface; instruction code storing
means for storing said instruction code for instructing said
central processing unit to effect the predetermined data processing
operation from said connector through said inspection information
interface into said instruction code register; and data storing
means for storing the data to be processed from said connector
through said inspection information interface into said data
register.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to an integrated circuit
device comprising at least a central processing unit, a bus control
circuit, and an inspection control circuit, and a method of and an
apparatus for inspecting such an integrated circuit device.
[0003] 2. Description of the Related Art
[0004] Heretofore, a system called an ICE (In-Circuit Emulator) has
been used to inspect internal operations of integrated circuit
devices constructed as single chips. The ICE system reads all input
and output signals of an integrated circuit device to emulate
internal operations thereof. Therefore, the ICE system is capable
of debugging an integrated circuit device while it is in a
development stage.
[0005] The ICE system is required to connect its connection
terminals individually to all the input and output terminals of an
integrated circuit device to be inspected, it is difficult to use
the ICE system with respect to an integrated circuit device as it
is mounted on a circuit board. To eliminate such a drawback, there
has been proposed an integrated circuit device incorporating a
built-in inspection control circuit which is capable of debugging
the integrated circuit device while it is mounted on a circuit
board.
[0006] One conventional integrated circuit device with such a
built-in inspection control circuit will be described below with
reference to FIG. 1 of the accompanying drawings. FIG. 1 shows in
block form an internal structure of the integrated circuit device.
As shown in FIG. 1, the integrated circuit device, generally
designated by 100, has a CPU (Central Processing Unit) core 1
connected by a dedicated internal bus 2 to a BCU (Bus Control Unit)
3 which is connected to a main bus 4.
[0007] The integrated circuit device 100 also has various
peripheral circuits 5 connected to the main bus 4. A number of lead
terminals 7 are connected through the main bus 4 to the CPU core 1,
the BCU 3, and the peripheral circuits 5. The integrated circuit
device 100 further includes a DCU (Debug Control Unit) 6 as an
inspection control circuit independent of the main bus 4. The DCU 6
has a plurality of boundary scan cells 8 connected respectively to
a plurality of lead terminals 10 serving as an inspection
information I/F (Interface) 9 of JTAG (Joint Test Action
Group).
[0008] Boundary scan cells 8 are also connected individually to the
lead terminals 7. The boundary scan cells 8 connected to the lead
terminals 7 are connected in a loop pattern from one of the
boundary scan cells 8 of the DCU 6 to the other boundary scan cell
8 of the DCU 6.
[0009] The integrated circuit device 100 of the above structure,
even when it is mounted on a circuit board (not shown) desired by
the user, can be debugged by a boundary scan test. For debugging
the integrated circuit device 100, a debugging connector is mounted
on the circuit board, and the inspection information I/F 9 of the
integrated circuit device 100 mounted on the circuit board is
connected to the debugging connector.
[0010] The lead terminals 7 other than the inspection information
I/F 9 of the integrated circuit device 100 are connected
respectively to necessary leads on the circuit board. When an
ordinary mode is established as an operation mode of the integrated
circuit device 100, since the boundary scan cells 8 connected
individually to the lead terminals 7 pass communication data
without changing it, the CPU core 1, etc. of the integrated circuit
device 100 can communicate with the leads on the circuit board
through the lead terminals 7.
[0011] When the connector of a circuit inspection device (not
shown) is connected to the connector on the circuit board and the
operation mode of the integrated circuit device 100 is switched to
a test mode, bus cycles of the CPU core 1 are stopped at a certain
time, and the boundary scan cells 8 form a shift register.
[0012] Now, communication data including addresses and commands
which the CPU core 1, etc. communicate through the lead terminals 7
can be replaced and acquired by the DCU 6 through the shift
register made up of the boundary scan cells 8. Because the boundary
scan cells 8 are connected to the circuit inspection device through
the inspection information I/F 9, the circuit inspection device can
inspect internal operations of the integrated circuit device
100.
[0013] Another conventional integrated circuit device with such a
built-in inspection control circuit will be described below with
reference to FIG. 2 of the accompanying drawings. FIG. 2 shows in
block form an internal structure of the integrated circuit device.
Those parts shown in FIG. 2 which are identical to those of the
conventional integrated circuit device shown in FIG. 1 are
identically referred to, and will not be described in detail
below.
[0014] The integrated circuit device, generally designated by 200,
has a CPU core 21 connected by a dedicated internal bus 22 to a BCU
23 which is connected to a main bus 24. To the main bus 24, there
are connected various peripheral circuits 25 and a DCU 26 as an
inspection control circuit. A number of lead terminals 27 are
connected through the main bus 24 to the CPU core 21, the BCU 23,
and the peripheral circuits 25.
[0015] Unlike the integrated circuit device 100, the DCU 26 has a
DMA (Direct Memory Access) controller 28 that is directly connected
to the main bus 24. To the DCU 26, there are connected a plurality
of lead terminals 30 as an inspection information I/F 29 of JTAG,
which are connected to the DMA controller 28.
[0016] The DCU 26 has no boundary scan cells, and the lead
terminals 27 have no boundary scan cells either. Various I/O
(Input/Output) ports 31 and a memory 32 as an information storage
medium on a circuit board (not shown) are connected to the lead
terminals 27 which are connected directly to the BCU 23. The memory
32 stores, for example, instruction codes and processed data which
are to be read by the integrated circuit device 200.
[0017] A debugging connector is mounted on a circuit board prepared
by the user, and the inspection information I/F 29 of the
integrated circuit device 200 mounted on the circuit board is
connected to the debugging connector. In an ordinary mode, data
communications with the peripheral circuits 25 through the main bus
24 are controlled by the CPU core 21 through the BCU 23.
[0018] When the connector of a circuit inspection device (not
shown) is connected to the connector on the circuit board and a
test mode is started for the integrated circuit device 200, the DCU
26 can directly access the peripheral circuits 25 from the main bus
24 without being routed through the BCU 23 due to a DMA function of
the DMA controller 28. Therefore, the circuit inspection device can
inspect internal operations of the integrated circuit device
200.
[0019] Consequently, the integrated circuit devices 100, 200 can be
inspected for their internal operations while being mounted on the
circuit board that the user has prepared.
[0020] However, the integrated circuit device 100 with the boundary
scan cells cannot easily be controlled because bus cycles of the
CPU core 1 need to be stopped at an appropriate time for inspecting
internal operations of the integrated circuit device 100, and
communication data is replaced and acquired through the shift
register made up of the boundary scan cells 8.
[0021] Because the boundary scan cells 8 which make up the shift
register need to be connected individually to the lead terminals 7,
the integrated circuit device 100 is relatively complex in
structure and large in size. The boundary scan cells 8 connected
individually to the lead terminals 7 cannot basically be used only
for the boundary cell test, and hence are not highly versatile in
nature.
[0022] With the integrated circuit device 200 based on the DMA
principles, the DCU 26 directly accesses the peripheral circuits 25
and the BCU 23 without being routed through the CPU core 21 due to
a DMA function of the DMA controller 28. It is difficult for the
DCU 26 to access an internal register of the CPU core 21. If the
DCU 26 is to be allowed to access the internal register of the CPU
core 21, then it is necessary to modify the CPU core 21
extensively. Such a modification process is tedious and
time-consuming, and the modified CPU core 21 would have lowered
compatibility with the peripheral circuits and other circuits.
SUMMARY OF THE INVENTION
[0023] It is an object of the present invention to provide an
integrated circuit device whose internal operations can easily be
inspected while being mounted on a circuit board, and a method of
and an apparatus for inspecting such an integrated circuit
device.
[0024] According to the present invention, an integrated circuit
device has an inspection information interface for detachable
connection to an external circuit inspection device, an inspection
control circuit connected to the inspection information interface
and having a plurality of registers for temporarily storing
instruction codes and data to be processed which are supplied from
the external circuit inspection device, and a bus control unit for
selectively connecting the external bus and the inspection control
circuit to the central processing unit.
[0025] The bus control unit has an operation mode switchable
between a normal mode and an inspection mode. The bus control unit
connects the external bus continuously to the central processing
unit in the normal mode, and switches a destination to be connected
to the central processing unit from the external bus to the
inspection control circuit in the inspection mode when the address
of an access destination issued by the central processing unit
agrees with the predetermined address of one of the registers of
the inspection control circuit.
[0026] In the normal mode, the bus control unit connects the
external bus continuously to the central processing unit. The
central processing unit reads the instruction codes and data to be
processed from an external information storage medium, and executes
various data processing tasks. When the external circuit inspection
device is connected to the inspection information interface to
switch the operation mode of the bus control unit from the normal
mode to the inspection mode, the bus control circuit switches a
destination to be connected to the central processing unit from the
external bus to the inspection control circuit at a given time.
[0027] The central processing unit then reads the instruction codes
and data to be processed from the inspection control circuit at a
predetermined time. Therefore, if desired instruction codes and
data to be processed are stored into the registers of the
inspection control circuit by the circuit inspection device, the
central processing unit can perform a desired data processing
operation in the inspection mode.
[0028] Consequently, it is possible to inspect the integrated
circuit device while the integrated circuit device is being
installed on a circuit board. The integrated circuit device can
effect various data processing tasks, and the process of inspecting
the integrated circuit device is not limited to the boundary scan
test. Thus, an internal register of the central processing unit can
also be inspected.
[0029] The registers of the inspection control circuit may include
an instruction code register for temporarily storing an instruction
code for instructing the central processing unit to effect a
predetermined data processing operation, a data register for
temporarily storing data to be processed by the central processing
unit based on the instruction code stored by the instruction code
register, and a return instruction code register for temporarily
storing an instruction code to return an access destination for the
central processing unit to the instruction code register.
[0030] The inspection control circuit has at least those three
registers for temporarily storing an instruction code for
instructing the central processing unit to effect a predetermined
data processing operation, data to be processed by the central
processing unit, and an instruction code to return an access
destination for the central processing unit to the instruction code
register. When the central processing unit reads the instruction
code to return the access destination after having effected the
data processing operation based on the instruction code and the
data to be processed, since the access destination is returned to
the instruction code register, the central processing unit effects
a next data processing operation by updating the instruction codes
and the data to be processed when the data processing operation has
been carried out. Consequently, a number of data processing
operations for inspection can be carried out by the central
processing unit with a minimum required number of registers.
[0031] Alternatively, the registers of the inspection control
circuit may include an instruction code register for temporarily
storing an instruction code for instructing the central processing
unit to effect a predetermined data processing operation, a data
register for temporarily storing data to be processed by the
central processing unit based on the instruction code stored by the
instruction code register, and a return instruction code register
for permanently storing an instruction code to return an access
destination for the central processing unit to the instruction code
register.
[0032] The inspection control circuit has at least those three
registers for temporarily storing an instruction code for
instructing the central processing unit to effect a predetermined
data processing operation, and data to be processed by the central
processing unit, and permanently storing an instruction code to
return an access destination for the central processing unit to the
instruction code register. When the central processing unit reads
the instruction code to return the access destination after having
effected the data processing operation based on the instruction
code and the data to be processed, since the access destination is
returned to the instruction code register, the central processing
unit effects a next data processing operation by updating the
instruction codes and the data to be processed when the data
processing operation has been carried out.
[0033] Consequently, a number of data processing operations for
inspection can be carried out by the central processing unit with a
minimum required number of registers. In addition, the circuit
inspection device does not need to store an instruction code to
return the access destination in a register.
[0034] According to the present invention, a method of inspecting
an integrated circuit device comprises the steps of storing an
instruction code for a predetermined data processing operation in
an instruction code register, storing data to be processed by a
central processing unit in a data register, storing an instruction
code to return an access destination in a return instruction code
register, updating the instruction code stored in the instruction
code register and the data stored in the data register when the
central processing unit effects the predetermined data processing
operation based on the instruction code stored in the instruction
code register and the data stored in the data register, and
returning the access destination of the central processing unit to
the instruction code register based on the instruction code stored
in the return instruction code register.
[0035] The instruction code for the predetermined data processing
operation is stored in the instruction code register, the data to
be processed by the central processing unit is stored in the data
register, and the instruction code to return the access destination
is stored in the return instruction code register. The access
destination of the central processing unit is returned to the
instruction code register after the central processing unit has
effected the data processing operation based on the instruction
codes and the data to be processed. Therefore, the central
processing unit effects a next data processing operation by
updating the instruction codes and the data to be processed when
the data processing operation has been carried out.
[0036] According to the present invention, furthermore, a method of
inspecting an integrated circuit device comprises the steps of
storing an instruction code for a predetermined data processing
operation in an instruction code register, storing data to be
processed by a central processing unit in a data register, updating
the instruction code stored in the instruction code register and
the data stored in the data register when the central processing
unit effects the predetermined data processing operation based on
the instruction code stored in the instruction code register and
the data stored in the data register, and returning the access
destination of the central processing unit to the instruction code
register based on the instruction code stored in the return
instruction code register.
[0037] The instruction code for the predetermined data processing
operation is stored in the instruction code register, and the data
to be processed by the central processing unit is stored in the
data register. The access destination of the central processing
unit is returned to the instruction code register after the central
processing unit has effected the data processing operation based on
the instruction codes and the data to be processed. Therefore, the
central processing unit effects a next data processing operation by
updating the instruction codes and the data to be processed when
the data processing operation has been carried out.
[0038] According to the present invention, an apparatus for an
inspecting an integrated circuit device comprises a connector
detachably connected to an inspection information interface,
instruction code storing means for storing an instruction code for
instructing a central processing unit to effect a predetermined
data processing operation from the connector through the inspection
information interface into an instruction code register, data
storing means for storing data to be processed from the connector
through the inspection information interface into a data register,
and return instruction code storing means for storing an
instruction code to return an access destination from the connector
through the inspection information interface into a return
instruction code register.
[0039] The connector is connected to the inspection information
interface. The instruction code for the predetermined data
processing operation is stored in the instruction code register,
the data to be processed by the central processing unit is stored
in the data register, and the instruction code to return the access
destination is stored in the return instruction code register. The
access destination of the central processing unit is returned to
the instruction code register after the central processing unit has
effected the data processing operation based on the instruction
codes and the data to be processed. Therefore, the central
processing unit effects a next data processing operation by
updating the instruction codes and the data to be processed when
the data processing operation has been carried out.
[0040] According to the present invention, furthermore, an
apparatus for an inspecting an integrated circuit device comprises
a connector detachably connected to the inspection information
interface, instruction code storing means for storing the
instruction code for instructing the central processing unit to
effect the predetermined data processing operation from the
connector through the inspection information interface into the
instruction code register, and data storing means for storing the
data to be processed from the connector through the inspection
information interface into the data register. The connector is
connected to the inspection information interface. The instruction
code for the predetermined data processing operation is stored in
the instruction code register, and the data to be processed by the
central processing unit is stored in the data register. The access
destination of the central processing unit is returned to the
instruction code register after the central processing unit has
effected the data processing operation based on the instruction
codes and the data to be processed. Therefore, the central
processing unit effects a next data processing operation by
updating the instruction codes and the data to be processed when
the data processing operation has been carried out.
[0041] The above and other objects, features and advantages of the
present invention will become apparatus from the following
description with reference to the accompanying drawings which
illustrate an example of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0042] FIG. 1 is a block diagram showing an internal structure of a
conventional integrated circuit device;
[0043] FIG. 2 is a block diagram showing an internal structure of
another conventional integrated circuit device;
[0044] FIG. 3 is a block diagram showing an internal structure of
an integrated circuit device according to the present
invention;
[0045] FIG. 4 is a block diagram showing an internal structure of a
DCU as an inspection control circuit; and
[0046] FIG. 5 is a diagram of a circuit inspection device connected
to a target board which is a circuit board with the integrated
circuit device mounted thereon.
DESCRIPTION OF THE PREFERRED EMBODIMENT
[0047] As shown in FIG. 3, an integrated circuit device 300
according to the present invention has a CPU core 41 connected by a
dedicated internal bus 42 to a BCU 43 which is connected to a main
bus 44. To the main bus 44, there are connected various peripheral
circuits 45. A number of lead terminals 46 are connected through
the main bus 44 to the CPU core 41, the BCU 43, and the peripheral
circuits 45.
[0048] Those parts shown in FIG. 3 which are identical to those of
the conventional integrated circuit device 200 shown in FIG. 2 are
identically referred to, and will not be described in detail
below.
[0049] Various I/O (Input/Output) ports 49 and a memory 49 as an
information storage medium on a target board 48 (see FIG. 5) as a
circuit board are connected to an external bus 47 that comprises
the lead terminals 46 which are connected directly to the BCU 43.
The memory 50 stores instruction codes and processed data which are
to be read by the CPU core 41 of the integrated circuit device
300.
[0050] A plurality of lead terminals 53 which make up a debugging
I/F 52 of JTAG as an inspection information I/F are connected to a
DCU 51 serving as an inspection control circuit. The DCU 51 has a
register unit 54. The DCU 51 is connected to the BCU 43 by a
dedicated internal bus 55. The BCU 43 selectively connects the
memory 50 and the DCU 51 to the CPU core 41.
[0051] As shown in FIG. 4, the DCU 51 comprises, in addition to the
register unit 54, a TAP (Test Access Port) controller 60, an
instruction register 61, an IR (Instruction Register) decoder 62, a
bus controller 63, a pair of selectors 64, 65, and a pair of
buffers 66, 67. The register unit 54 comprises a plurality of
registers 68-71.
[0052] The instruction register 61 and the register unit 54 are
connected respectively to a pair of input terminals of the selector
64, whose output terminal is connected to the buffer 66. The buffer
66 has a control terminal to which the TAP controller 60 is
connected.
[0053] The registers 68-71 of the register unit 54 includes a
single debug status register 68 for storing debug status data, a
single debug control register 69 for storing debug control data, a
plurality of monitor registers 70 for storing instruction codes for
the CPU core 41, and a single access data register 71 for storing
data to be processed by the CPU core 41.
[0054] The monitor registers 70 and the access data register 71 are
connected to respective input terminals of the selector 65, whose
control terminal is connected to the bus controller 63. The
selector 65 has an output terminal connected to the buffer 67,
whose control terminal is connected to the bus controller 63.
[0055] The debugging I/F 52 of JTAG is connected to the TAP
controller 60, the instruction register 61, the register unit 54,
and the IR decoder 62, and carries input data "TRST", "TCK", "TMS",
"TDI", etc. and output data "TDO", etc.
[0056] The internal bus 55 which interconnects the DCU 51 and the
BCU 43 is connected to the monitor registers 70 and the access data
register 71 of the register unit 54, and the bus controller 63. The
internal bus 55 carries input/output data "Data", output data
"Ready", "Holdrq", etc., and input data "Address", "Status",
etc.
[0057] Debug status data stored by the debug status register 68,
debug control data stored by the debut control register 69,
instruction codes for and data to be processed by the CPU core 41,
which are stored by the monitor registers 70, and data to be
processed by the CPU core 41, which is stored by the access data
register 7, will be described below.
[0058] 1. Debug status data DBG_STATUS Debugging I/F 52: RO, CPU
core 41: x DBM Debug Mode Status
[0059] This indicates an execution mode for the CPU core 41. A
normal mode thereof is an ordinary mode for executing a user
program. A debug mode thereof is an inspection mode for executing a
highest-priority interrupt/exception process. In order to shift
from the normal mode to the debug mode, these methods are
available:
[0060] 1. A BRI bit is set to "1" to generate a debut interrupt
request.
[0061] 2. A breakpoint instruction BRKPNT is executed.
[0062] In order to return from the debug mode to the normal mode,
these methods are available:
[0063] 1. A return instruction BRPRET from the debug mode is
executed.
[0064] 2. An RST bit is set to "1" to reset the CPU core 41.
[0065] 1: Debug mode
[0066] 0: Normal mode
[0067] EED Monitor Operation End Status
[0068] This indicates that a monitoring process of the CPU core 41
is ended and the CPU core 41 is in a pending state. In order to
place the CPU core 41 in a pending state when the monitoring
process thereof is ended, these methods are available:
[0069] 1. When the monitoring process is ended, a bus hold request
is generated to place the CPU core 41 in a bus hold state. By
setting an EST bit to "1", the bus hold request is canceled,
resuming the monitoring process of the CPU core 41.
[0070] 2. When the monitoring process is ended, a ready signal is
not returned in a next instruction fetch cycle, thereby putting bus
cycles in a BUSY state. By setting the EST bit to "1", a ready
signal is returned to finish a fetch cycle, resuming the monitoring
process of the CPU core 41.
[0071] 3. When the monitoring process is ended, a next instruction
is set to a loop instruction (a branch instruction for the CPU core
41), causing the CPU core 41 to execute fetch and branch
instructions repeatedly. By setting the EST bit to "1", an
instruction to be fetched by the CPU core 1 is changed from an
endless loop instruction to an instruction set to EM_MONn, resuming
the monitoring process of the CPU core 41.
[0072] 1: The monitoring process is ended.
[0073] 0: The monitoring process is not ended.
[0074] TRS Reset Input Status
[0075] This indicates the status of a reset input signal entered
from an external source. The reset input signal entered from the
external source is masked when an MTR bit is set to "1". The reset
input signal entered from the external source is always masked in
the debug mode irrespective of the MTR bit.
[0076] 1: A reset input signal entered from an external source is
active.
[0077] 2: A reset input signal entered from an external source is
inactive.
[0078] 2. Debug control data DBG_CONTROL Debug I/F52: R/W, CPU core
41: x EST Monitor Operation Start Request
[0079] The monitoring process which has been ended by the CPU core
41 when an EED bit is "1" can be resumed when the EST bit is set to
"1". While the monitoring process is being ended, when a new
instruction or data is established in the registers 70, 71 of
EM_MONn/AC_ADDT and then the EST bit is set to "1", the CPU core 41
executes a new monitoring process.
[0080] 1: Start of a monitoring process is requested.
[0081] 2: Nothing is done (default).
[0082] BRI Break Interrupt Request
[0083] This is used in order to shift the CPU core 41 from the
normal mode to the debug mode. A debug interrupt is a
highest-priority interrupt at the CPU core 41.
[0084] 1: A debug interrupt is requested.
[0085] 0: A debug interrupt is canceled (default).
[0086] REE Reset Handler Emulation Enable
[0087] This is used for the DCU to substitute for a reset handler
area. Since a substitute area is accessed after the CPU core 41 is
reset by setting REE to "1", the CPU core 41 can be shifted into
the debug mode immediately after the CPU core 41 is started by:
[0088] 1. executing a breakpoint instruction BRKPNT in the
substitute area, or
[0089] 2. executing a loop instruction in the substitute area and
setting the BRI bit to "1" to generate a debug interrupt request.
Since a RAM, rather than a ROM, is often used in a development
stage, this control data is indispensable for downloading a
development program.
[0090] 1: A reset handler area is substituted for.
[0091] 0: A reset handler area is not substituted for
(default).
[0092] RST Force Reset Request
[0093] This is used to reset the CPU core 41 irrespective of the
status of a reset input signal entered from an external source.
When a debugging tool is connected to the debugging I/F 52, the
default value immediately after the power supply is turned on can
be changed by changing the terminal processing to a condition
different from the condition in which no debugging tool is
connected to the debugging I/F 52.
[0094] 1: The CPU core 41 is forcibly reset (when a debugging tool
is connected).
[0095] 0. The CPU core 41 is not forcibly reset (when no debugging
tool is connected).
[0096] MTR Reset Mask Request
[0097] This is used to mask a reset input signal entered from an
external source. When the CPU core 41 enters the debug mode, a
reset input signal entered from an external source is always masked
irrespective of the MTR bit in order to carry out a monitoring
process.
[0098] 1: A reset input signal entered from an external source is
masked.
[0099] 0: A reset input signal entered from an external source is
not masked (default).
[0100] 3. Instruction code EM_MONn(n=0-6) Debugging I/F 52: R/W,
CPU core 41: RO EM_MONn[31:0] Monitor Instruction Code (/Access
Address/Data)
[0101] This sets an instruction code for an instruction executed in
a monitoring process with the debugging I/F 52, and sets data to be
processed, such as an address to be accessed in a monitoring
process with the debugging I/F 52.
[0102] 4. Data to be processed AC_ADDT Debugging I/F 52: R/W, CPU
core 41: R/W AC_ADDT[31:0] Access Address/Data
[0103] This sets data to be processed, such as an address to be
accessed in a monitoring process with the debugging I/F 52, and is
established from the CPU core 41 when the result of an executed
monitoring process is to be received from the CPU core 41.
[0104] The integrated circuit device 300 according to the present
invention is installed on the target board 48 prepared by the user,
and the external bus 47 of the integrated circuit device 300 is
connected to the I/O ports 49 and the memory 50 which are mounted
on the target board 48 by printed interconnections. As shown in
FIG. 5, an inspection connector 51 is mounted on the target board
48, and the debugging I/F 52 of the integrated circuit device 300
is connected to the connector 81.
[0105] The BCU 43 has a normal mode and a debug mode its operation
modes that can be switched from one to the other. In the normal
mode, the BCU 43 connects the external bus 47 continuously to the
CPU core 41. In the debug mode, the BCU 43 switches the CPU core 41
from the external bus 47 to the DCU 51 when the address of an
access destination issued by the CPU core 41 agrees with the
address, which has been established beforehand, of the register
unit 54 of the DCU 51.
[0106] The connector 81 on the target board 48 is used only when
the integrated circuit device 300 is inspected. A debugging system
40 as a circuit inspection device can detachably be connected to
the connector 81. The debugging system 400 has an ICE 83 that can
detachably be connected to the connector 81 by a connector 82. To
the ICE 83, there are connected a power supply unit 84 and a
communication module 85 which is connected to a communication line
86 connected to a host computer 87.
[0107] Each of the ICE 83 and the host computer 87 comprises a
computer system which has various logic functions as various
corresponding means that can be performed to achieve various data
processing tasks according to an appropriate program which has been
loaded beforehand. The debugging system 400 has a mode switching
means, an instruction storing means, a data storing means, and a
return storing means, provided as logic functions.
[0108] The mode switching means changes the operation mode of the
BCU 43 from the normal mode to the debug mode when an operation
mode switching flag for the BCU 43 is issued by the ICE 84 and
supplied through the connectors 82, 81 to the debugging I/F 52 of
the integrated circuit device 300.
[0109] When an instruction code for enabling the CPU core 41 to
execute certain data processing is issued from the ICU 84, the
instruction storing means supplies the instruction code from the
connectors 82, 81 to the debugging I/F 52, and stores the
instruction code in the monitor registers 70.
[0110] When data required by data processing executed by the CPU
core 41 is issued by the ICE 83, the data storing means supplies
the data from the connectors 82, 81 to the debugging I/F 52, and
stores the data in the registers 70, 71.
[0111] When an instruction code for returning an access destination
to be accessed by the CPU core 41 is issued by the ICE 84, the
return storing means supplies the instruction code from the
connectors 82, 81 to the debugging I/F 52, and stores the
instruction code in the monitor registers 70.
[0112] The program which realizes the above various means as the
various functions is stored beforehand as software in an
information storage medium in the debugging system 400. When a
monitoring process is to be executed, the program is copied into
the DCU 51, and then read by the CPU core 41 and the BCU 43.
[0113] When a debug interrupt occurs, the CPU core 41 branches to a
debug handler area whose addresses are "Oxffffffef-Oxffffffef" of a
cache area. When the debug handler area is accessed, the BCU 43
switches the CPU core 41 from the external bus 47 to the DCU 51 in
the debug mode.
[0114] After the integrated circuit device 300 is reset, the CPU
core 41 branches to a reset handler area whose addresses are
"OxfffffffO-Oxffffffff" of the cache area. When the reset handler
area is accessed only while "REE" of the debug control data
"DBG_CONTROL" is being set to "1" in the debug mode, the BCU 43
switches the CPU core 41 from the external bus 47 to the DCU
51.
[0115] Since a monitoring process is carried out by successively
replacing an instruction at the same address, when the monitoring
process is to be carried out in the cache area, it is necessary to
clear the cache area before and after replacing an instruction, or
to execute the monitoring process in an uncache area.
[0116] In the integrated circuit device 300, the CPU core 41
branches from the debug handler area to the uncache area according
to the latter method, and then executes the monitoring process at
addresses 0x61000000 - 0x600001f. When this area is accessed, the
BCU 43 switches the CPU core 41 from the external bus 47 to the DCU
51 in the debug mode.
[0117] After the monitoring process, the execution by the CPU core
41 may be brought into a pending state using a bus hold request
"Holdrq". The bus hold request "Holdrq" generated from the DCU 51
for the BCU 43 by reading (ld.w 0.times.1c[rXX],r0) a certain area
"0x6100001l c" during the debug mode.
[0118] A specific example of a program for performing the above
various functions when the debugging system 40 monitors the
integrated circuit device 300 will be described below.
[0119] (1) Initial codes:
[0120] Prior to a transition to a first debug mode, instruction
codes for a monitoring start process and a monitoring end process
are established in advance in the registers 70, 71 of EM_MONn,
AC_DDT. Monitoring process area (uncache area).fwdarw.monitoring
end process
1 -- 0x61000000 EM_MON0 ld.w 0 x lc[rXX],r0 -- 0x61000004 EM_MON1
br +2 -- 0x61000006 EM_MON1 ld.w 0 x 18[rXX],rXX -- 0x61000008
EM_MON2 (continued from ld.w instruction code) -- 0x6100000A
EM_MON2 brkret
[0121] Debug handler area (cache area)/monitoring process area
(uncache area) ->monitoring start process
2 0xFFFFFFE0 0x6100000C EM_MON3 st.w rXX,0xffffffec[r0] 0xFFFFFFE4
0x61000010 EM_MON4 movhi 0x6100,r0,rXX 0xFFFFFFE8 0x61000014
EM_MON5 jmp[rXX] 0xFFFFFFEA 0x61000016 EM_MON5 nop 0xFFFFFFEC
0x61000018 AC_ADDT (nop) 0xFFFFFFEE 0x6100001A AC_ADDT (nop) --
0x6100001C fixed nop instruction code -- 0x6100001E fixed nop
instruction code
[0122] Reset handler area (cache area) (when the REE bit of the
DBG_CONTROL register is "1")
3 0xFFFFFFF0 -- fixed instruction code br +0 0xFFFFFFF2 -- fixed
instruction code nop 0xFFFFFFF4 -- fixed instruction code br +0
0xFFFFFFF6 -- fixed instruction code nop 0xFFFFFFF8 -- fixed
instruction code br +0 0xFFFFFFFA -- fixed instruction code nop
0xFFFFFFFC -- fixed instruction code br +0 0xFFFFFFFE -- fixed
instruction code nop
[0123] (2) Monitoring start process:
[0124] Since a debut handler is in a cache area, it branches to an
uncache area. At this time, the value of a general register rXX
used in a monitoring process is saved to the access data register
71 of AC_DDT.
4 0xFFFFFFE0 EM_MON3 st.w rXX,0xFFFfffec[r0] The value of rXX is
saved to AC_DDT 0xFFFFFFE4 EM_MON4 movhi 0x6100,r0,rXX 0x61000000
is set to rXX QxFFFFFFE8 EM_MON5 jmp[rXX} Branching to 0x61000000
0xFFFFFFEA EM_MON5 nop Nothing done 0xFFFFFFEC AC_ADDT (nop) The
value of rXX is saved 0xFFFFFFEE AC_ADDT (nop) The value of rXX is
saved 0x61000000 EM_MON0 ld.w 0 x lc[rXX],rp Pending after loading
is executed 0x61000004 EM_MON1 br + 2 Branching for re-fetching
0x61000006 EM_MON1 (ld.w 0 x 18[rXX],rXX)
[0125] (By generating a bus hold request during a data read access
from a certain area due to the execution of an instruction to
load.fwdarw.EM_MONO, the CPU core 41 is brought into a bus hold
state, holding the execution of instructions in a pending state
after the end of a read cycle. In the integrated circuit device
300, the CPU core 41 has a write buffer as an internal register.
Since the execution of a write cycle is further delayed even when
the CPU core 41 finishes the execution of a store instruction, it
is possible to ensure the sequence of data accesses by holding the
execution of instructions in a pending state with reading of data
from an uncache area, and the exchange of data using the access
data register 71 of AC_ADDT is reliably finished. After the bus
holding is canceled, because the execution of instructions is
resumed from a branch instruction of EM_MON1, pipeline is flushed
by branching, and a new instruction code of EM_MON1 is re-fetched
and executed.)
[0126] (2) Monitoring end process:
[0127] The value of the general register rXX is returned to the
original value, and a return instruction from the debug mode is
executed. For a next transition to the debug mode, initial codes
are established in the monitor registers 70 of EM-MONn.
5 0x61000004 EM_MON1 br + 2 Branching for re-fetching 0x61000006
EM_MON1 ld.w 0 x 18[rXX],rXX The value of rXX is returned to the
original value 0x61000008 EM_MON2 Continued from ld.w instruction
code 0x6100000A EM_MON2 brkret Returned from the debug mode
0x6100000C EM_MON3 st.w rXX,0xFFFfffec[r0] (Code prior to
monitoring start process) 0x61000010 EM_MON4 movhi 0x6100,r0,rXX
(Code prior to monitoring start process) 0x61000014 EM_MON5 jmp
[rXX] (Code prior to monitoring start process) 0x61000016 EM_MON5
nop (Code prior to monitoring start process) 0x61000018 AC_DDT
(saved value of rXX) Saved value is established
[0128] (4) Example of reading the value of a general register
(Example of reading the value of a general register rYY:
6 0x61000004 EM_MON1 br + 2 Branching for re-fetching 0x61000006
EM_MON1 nop Nothing done 0x61000008 EM_MON2 st.w rYY,0 x 18[rXX]
rYY value is stored in AC_DDT 0x6100000C EM_MON3 jmp [rYY] Return
to 0x61000000 0x6100000E EM_MON3 nop Nothing done -- 0x61000018
AC_DDT -- rYY value is written 0x61000000 EM_MON0 ld.w 0 x
1c[rXX],r0 Pending after loading is executed 0x61000004 EM_MON1 br
+ 2 Branching for re-fetching 0x61000006 EM_MON1 (nop)
[0129] (.fwdarw.the monitoring process is ended. AC_DDT is read to
obtain the value of rYY.)
[0130] (5) For establishing a designated value in a general
register (Example of a designated value in a general register
rYY):
7 0x61000004 EM_MON1 br + 2 Branching for re-fetching 0x61000006
EM_MON1 nop Nothing done 0x61000008 EM_MON2 ld.w 0 x 18[rXX],rYY
The designated value is established in rYY 0x6100000C EM_MON3 jmp
[rXX]0x Return to 61000000 -- 0x6100000E EM_MON3 nop Nothing done
-- 0x61000018 AC_DDT (The value to be The value to established in
rYY) be established in rYY 0x61000000 EM_MON0 ld.w 0 x 1c[rXX],r0
Pending after loading is executed 0x61000004 EM_MON1 br + 2
Branching for re-fetching 0x61000006 EM_MON1 (nop)
[0131] (.fwdarw.the monitoring process is ended.)
[0132] (6) For reading the value of a system register (Example of
reading the value of a system register sXX):
8 0x61000004 EM_MON1 br + 2 Branching for re-fetching 0x61000006
EM_MON1 stsr sXX,RYY sXX value is copied to rYY 0x61000008 EM_MON2
st.w rYY,0 x 18[rXX] rYY value is stored in AC_DDT 0x6100000C
EM_MON3 jmp [rXX] Return to 0x61000000 0x6100000E EM_M0N3 nop
Nothing done -- 0x61000018 AC_ADDT -- sXX value is written
0x61000000 EM_M0N0 ld.w 0 x lc[rXX],r0 Pending after loading is
executed 0x61000004 EM_M0N1 br + 2 Branching for re-fetching
0x61000006 EM_M0N1 (stsrSySx,rYY)
[0133] (.fwdarw.the monitoring process is ended. AC_DDT is read to
obtain the value of sXX.)
[0134] (7) For establishing a designated value in a general
register (Example of a designated value in a general register
sxX):
9 0x61000004 EM_MON1 br + 2 Branching for re-fetching 0x61000006
EM_MON1 nop Nothing done 0x61000008 EM_MON2 ld.w 0 x 18[rXX],rYY
The designated value is established in rYY 0x6100000C EM_MON3 ldsr
rYY,sXX rYY value is copied to sXX 0x6100000E EM_MON3 jmp [rXX]
Return to 0x61000000 -- 0x61000018 AC_DDT (The value to be The
value to established in sXX) be established in sXX 0x61000000
EM_MON0 ld.w 0 x 1c[rXX],r0 Pending after loading is executed
0x61000004 EM_MON1 br + 2 Branching for re-fetching 0x61000006"
(nop)
[0135] (.fwdarw.the monitoring process is ended.)
[0136] (8) Reading data from a designated address space (Example of
reading words from a memory):
10 0x61000004 EM_MON1 br + 2 Branching for re-fetching 0x61000006
EM_MON1 nop Nothing done 0x61000008 EM_MON2 ld.w 0 x 18[rXX],rYY A
load address is established in rYY 0x6100000C EM_MON3 ld.w 0 x
00[rYY],rZZ Loading from a designated address 0x61000010 EM_MON4
st.w rZZ 0 x 18[rXX] rZZ value is written in AC_DDT 0x61000014
EM_MON5 jmp [rXX] Return to 0x61000000 0x61000016 EM_MON5 nop
Nothing done 0x61000018 AC_ADDT (load address) A load address is
established (load data) Load data is written -- 0x61000000 EM_MON0
ld.w 0 x 1c[rXX],r0 Pending after loading is executed 0x61000004
EM_MON1 br + 2 Branching for re-fetching 0x61000006 EM_MON1
(nop)
[0137] (.fwdarw.the monitoring process is ended. AC_ADDT is read to
obtain the value of load data.)
[0138] (9) Writing data in a designated address space (Example of
writing words from a memory): In this case, a monitoring process of
the following two steps is carried out.
[0139] 1. An address at which data is to be written is
established.
[0140] 2. Data to be written is established, and designated data is
written in the designated address.
11 [1st step] 0x61000004 EM_MON1 br + 2 Branching for re-fetching
0x61000006 EM_MON1 nop Nothing done 0x61000008 EM_MON2 1d.w 0
.times. 18[rXX],rYY A load address is established in rYY 0x6100000C
EM_MON3 jmp [rXX] Return to 0x61000000 0x6100000E EM_MON3 nop
Nothing done 0x61000018 AC_ADDT (store address) A store address is
established 0x61000000 EM_MON0 1d.w 0 .times. 1c[rXX],r0 Pending
after loading is executed 0x61000004 EM_MON1 br + 2 Branching for
re-fetching 0x61000006 EM_MON1 nop Nothing done
[0141] (.fwdarw.the monitoring process is ended. A second
instruction code is established in EN_MONn, and store data is
established in AC_ADDT, after which the monitoring process is
started.)
12 [2nd step] 0x61000004 EM_MON1 br + 2 Branching for re-fetching
0x61000006 EM_MON1 nop Nothing done 0x61000008 EM_MON2 1d.w 0
.times. 18[rXX],rZZ A load address is established in rZZ 0x6100000C
EM_MON3 st.w rZZ, 0 .times. 00[rYY] Data is stored at a designated
address 0x61000010 EM_MON5 jmp [rXX] Return to 0x61000000
0x61000012 EM_MON5 nop Nothing done 0x61000018 AC_ADDT (store data)
store data is written 0x61000000 EM_MON0 1d.w 0 .times. 1c[rXX],r0
Pending after loading is executed 0x61000004 EM_MON1 br + 2
Branching for re-fetching 0x61000006 EM_MON1 (nop)
[0142] (.fwdarw.the monitoring process is ended.)
[0143] In use, the integrated circuit device 300 according to the
present invention is installed on the target board 48 prepared by
the user. A program composed of various instruction codes and data
to be processed is loaded as software in the memory 50 on the
target board 48. The integrated circuit device 300 reads
instruction codes and data to be processed from the memory 50 on
the target board 48.
[0144] At this time, the operation mode of the integrated circuit
device 300 is the normal mode by default. Since the BCU 43 connects
the memory 50 continuously to the CPU core 41, the CPU core 41
executes various data processing tasks based on instruction codes
and data read from the memory 50.
[0145] The program stored in the memory 50 for controlling the
integrated circuit device 300 to process data needs to be debugged
when the integrated circuit device 300 is in its development stage.
For debugging the program, as shown in FIG. 5, the debugging system
400 is connected to the integrated circuit device 300 installed on
the target board 48.
[0146] Specifically, since the debugging I/F 52 of the integrated
circuit device 300 is connected to the connector 81 on the target
board 48, the connector 82 of the debugging system 400 is joined to
the connector 81. As shown FIGS. 6 and 7, the integrated circuit
device 300 carries out a data processing operation according to the
program stored in the memory 50 on the target board 48, and while
the integrated circuit device 300 is carrying out the data
processing operation, the debugging system 400 accesses the DCU 51
via the debugging I/F 52.
[0147] The DCU 52 effects an interrupt process on the BCU 43 to
change the operation mode of the integrated circuit device 300 from
the normal mode to the debug mode which is an inspection mode. The
integrated circuit device 300 will subsequently process data in the
debug mode. Specifically, the debugging system 400 stores a
plurality of instruction codes and data to be processed into the
registers 70, 71 of the DCU 51, and stores an instruction code for
returning an access destination for the CPU core 41 to their
initial position into the final monitor register 70.
[0148] Inasmuch as the CPU core 41 is connected to the memory 50 on
the target board 48 by the BCU 43, the CPU core 41 executes the
data processing operation according to the program stored in the
memory 50. In the debug mode, the BCU 43 compares addresses issued
by the CPU core 41 in the data processing operation with a given
address which has been established beforehand for debugging. When
an address from the CPU core 41 agrees with the given address, the
BCU 43 changes a destination to be connected to the CPU core 41
from the memory 50 to the DCU 51.
[0149] The CPU core 41 then reads instruction cores and data to be
processed from the registers 70, 71 of the DCU 51, so that the
integrated circuit device 300 carries out a desired data processing
operation for debugging. As the CPU core 41 successively reads
instruction codes and data to be processed from the registers 70,
71 and carries out the data processing operation, the CPU core 41
returns an access destination to the initial position of the
monitor registers 70 depending on the instruction code in the final
monitor register 70.
[0150] For example, the bus controller 63 of the DCU 51 causes the
CPU core 41 to wait via the BCU 43. Therefore, when the debugging
system 400 updates instruction codes and data to be processed which
are stored in the registers 70, 71 of the DCU 51, the debugging
system 400 can cause the CPU core 41 to effect a next data
processing operation for debugging. At this time, the debugging
system 400 may temporarily store and collect data processed by the
CPU core 41, which executes the data processing operation for
debugging, in the registers 70, 71.
[0151] As described above, the debugging system 400 causes the CPU
core 41 to effect a data processing operation for debugging while
updating the debugging program in the registers 70, 71. When this
data processing operation is completed, the debugging system 400
returns the operation mode of the integrated circuit device 300
from the debug mode to the normal mode.
[0152] In the integrated circuit device 300 according to the
present invention, as described above, the DCU 51 is connected to
the BCU 43, which switches a destination to be connected to the CPU
core 41 between the memory 50 on the target board 48 and the
registers 70, 71 of the DCU 51 at predetermined times.
[0153] If the debugging system 400 stores desired instruction codes
and data to be processed in the registers 70, 71, then the
debugging system 400 is capable of causing the CPU core 41 to
execute a desired data processing operation for debugging.
Consequently, it is possible to inspect the integrated circuit
device 300 while it is being mounted on the target board 48 desired
by the user.
[0154] Since the registers 70, 71 can freely store various
instruction codes and data to be processed for enabling the CPU
core 41 to execute various data processing tasks, the process of
inspecting the integrated circuit device 300 is not limited to the
boundary scan test.
[0155] In the debug mode, the CPU core 41 processes data in the
same manner as in the normal mode. Accordingly, the debugging
system 400 can inspect various parts of the integrated circuit
device 300. Unlike the conventional DMA process described above,
the internal register of the CPU core 41 can also be inspected
without the need for a substantial modification of the CPU core
41.
[0156] With the integrated circuit device 300 and the debugging
system 400, when instruction codes and data to be processed are
stored in the registers 70, 71 and the CPU core 41 executes a data
processing operation for debugging based on the stored instruction
codes and data to be processed, an access destination for the CPU
core 41 is returned to the initial position of the monitor
registers 70 depending on the instruction code in the final monitor
register 70. Therefore,. the number of registers 70, 71, which are
devices dedicated for debugging and not required in the normal
mode, may be small, and hence the circuit scale of the integrated
circuit device 300 may be of a minimum required.
[0157] In the above embodiment, the debugging system 400 stores an
instruction code for returning an access destination for the CPU
core 41 to the initial position in the final monitor register 70.
However, this instruction code may fixedly be stored in the final
monitor register 70, rather than being stored by the debugging
system 400.
[0158] While a preferred embodiment of the present invention has
been described using specific terms, such description is for
illustrative purposes only, and it is to be understood that changes
and variations may be made without departing from the spirit or
scope of the following claims.
* * * * *