U.S. patent application number 09/805872 was filed with the patent office on 2001-07-26 for interleaved signal trace routing.
Invention is credited to Ball, Zane A., Clark, Lawrence T., Gutman, Aviram.
Application Number | 20010009782 09/805872 |
Document ID | / |
Family ID | 22256635 |
Filed Date | 2001-07-26 |
United States Patent
Application |
20010009782 |
Kind Code |
A1 |
Ball, Zane A. ; et
al. |
July 26, 2001 |
Interleaved signal trace routing
Abstract
A multi-layer electronic device package includes first and
second outer layers and at least one signal layer disposed between
the outer layers. The signal layer includes signal traces and
ground traces interleaved with the signal traces. A method of
routing signal traces in an electronic device package includes the
acts of disposing a plurality of signal traces in at least one
substrate layer, and interleaving a plurality of ground traces with
the signal traces.
Inventors: |
Ball, Zane A.; (Portland,
OR) ; Gutman, Aviram; (Haifa, IL) ; Clark,
Lawrence T.; (Phoenix, AZ) |
Correspondence
Address: |
BLAKELY SOKOLOFF TAYLOR & ZAFMAN
12400 WILSHIRE BOULEVARD, SEVENTH FLOOR
LOS ANGELES
CA
90025
US
|
Family ID: |
22256635 |
Appl. No.: |
09/805872 |
Filed: |
March 14, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09805872 |
Mar 14, 2001 |
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09096276 |
Jun 11, 1998 |
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6246112 |
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Current U.S.
Class: |
438/129 ;
257/E23.062 |
Current CPC
Class: |
H01L 23/49822 20130101;
H01L 2224/16225 20130101; H05K 2201/09236 20130101; H05K 1/0219
20130101; H05K 1/0298 20130101; H05K 2201/09672 20130101 |
Class at
Publication: |
438/129 |
International
Class: |
H01L 021/82 |
Claims
What is claimed is:
1. A multi-layer electronic device package comprising: first and
second outer layers; and a plurality of signal layers disposed
between the outer layers, the signal layers including signal traces
and ground traces interleaved with the signal traces.
2. The multi-layer electronic device package of claim 1 wherein the
first outer layer defines a ground layer.
3. The multi-layer electronic device package of claim 1 wherein the
second outer layer defines a power source layer.
4. The multi-layer electronic device package of claim 1 wherein the
plurality of signal layers comprises three signal layers.
5. The multi-layer electronic device package of claim 1 wherein the
ground traces are interleaved with signal traces within the signal
layer.
6. The multi-layer electronic device package of claim 1 wherein the
ground traces are interleaved with signal traces between signal
layers.
7. The multi-layer electronic device package of claim 1 wherein the
outer layers and the signal layers define a plurality of vias.
8. The multi-layer electronic device package of claim 1 wherein the
signal traces are configured to route at least 250 signals.
9. The multi-layer electronic device package of claim 1 wherein the
signal traces are adapted to interconnect a processor and a memory
device.
10. The multi-layer electronic device package of claim 9 further
comprising a processor and a memory device coupled to the
multi-layer electronic device package such that the signal traces
interconnect the processor and the memory device.
11. A multi-layer electronic device package comprising: a ground
layer; a power layer; a plurality of signal layers, each signal
layer including a plurality of signal traces; and means for
shielding the signal traces from each other.
12. A method of routing signal traces in an electronic device
package comprising the acts of: disposing a plurality of signal
traces in at least one substrate layer; and interleaving a
plurality of ground traces with the signal traces.
13. The method of claim 12 wherein the disposing act further
comprises disposing the signal traces in at least one substrate
layer situated between a ground layer and a power layer.
14. The method of claim 12 wherein the disposing act further
comprises disposing the signal traces in three substrate
layers.
15. The method of claim 12 wherein the interleaving act comprises
interleaving the ground traces with the signal traces within at
least one of the substrate layers.
16. The method of claim 12 wherein the interleaving act comprises
interleaving the ground traces with the signal traces between the
substrate layers.
17. The method of claim 12 wherein the disposing the signal traces
act further comprises disposing the signal traces so as to route at
least 250 signals.
18. The method of claim 12 wherein the disposing the signal traces
act further comprises coupling the signal traces between a
processor and a memory device.
19. A semiconductor device comprising: a first semiconductor die; a
second semiconductor die; and a multi-layer package, the first die
and the second die being mounted on the multi-layer package; the
multi-layer package defining at least one signal layer, each signal
layer including signal traces and ground traces interleaved
therewith, the signal traces interconnecting the first die and the
second die.
20. The semiconductor device of claim 19 wherein the first
semiconductor die is disposed in a first component package that is
mounted on the multi-layer package.
21. The semiconductor device of claim 20 wherein the second
semiconductor die is disposed in a second component package that is
mounted on the multi-layer package.
22. The semiconductor device of claim 19 wherein the at least one
signal layer comprises three signal layers.
23. The semiconductor device of claim 19 wherein the first
semiconductor die comprises a processor.
24. The semiconductor device of claim 19 wherein the second
semiconductor die comprises at least one memory device.
25. The semiconductor device of claim 24 wherein the at least one
memory device comprises two memory devices.
26. The semiconductor device of claim 25 wherein the memory devices
are situated on opposite sides of the processor.
27. The semiconductor device of claim 25 wherein the memory devices
are situated on one side of the processor.
28. The semiconductor device of claim 19 wherein the ground traces
are interleaved with the signal traces within at least one of the
signal layers.
29. The semiconductor device of claim 19 wherein the ground traces
are interleaved with the signal traces between signal layers.
30. The semiconductor device of claim 19 further comprising a
plurality of vias that couple the signal traces to the first
semiconductor die and the second semiconductor die.
31. A multi-layer electronic device package comprising: a plurality
of signal traces; and a plurality of ground traces interleaved with
the plurality of signal traces.
32. The multi-layer electronic device package of claim 31 wherein
the signal traces and the ground traces are incorporated in at
least one substrate layer.
33. The multi-layer electronic device package of claim 32 wherein
the ground traces are interleaved with the signal traces within at
least one substrate layer.
34. The multi-layer electronic device package of claim 32 wherein
the ground traces are interleaved with the signal traces between
substrate layers.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates generally to multi-layer electronic
device packages, and more particularly, to routing signal traces in
a multi-layer package.
[0003] 2. Description of Related Art
[0004] Multi-layer electronic device packages, such as multi-layer
printed circuit boards ("PCBs") and multi-chip modules ("MCMs"),
are well known in the art. Multi-layer packages include a plurality
of substrate layers, with at least one of the outer substrate
layers of the multi-layer package typically adapted to have
electronic components mounted thereon. One or more of the substrate
layers has conductive traces incorporated therewith that act as
wires to interconnect the components mounted on the package. Other
layers may provide power and ground connections to the
components.
[0005] Incorporating conductive traces in multiple substrate layers
allows circuit designers to lay out complex circuit designs using
numerous interconnections between components, while minimizing the
required surface area of the package. Electrical connections
between the various substrate layers of the package, and between
layers of the package and components mounted on the package, is
achieved using "vias." Basically, a via is a hole extending through
substrate layers that is filled with conductive material to form an
electrical connection.
[0006] Multi-layer packages are used extensively in computer
systems and other semiconductor applications. The conductive traces
of the multi-layer package may be used to route signals between
components coupled to the package. Routing a high number of signals
in a small area--especially high-speed signals--creates problems
with parasitic noise generated from the signals routed through
adjacent traces. This is especially problematic when multiple
signal layers are employed for routing signals. This parasitic
noise, sometimes also called "cross-talk," may result in spurious
logic errors.
[0007] The present invention addresses some of the above mentioned
and other problems of the prior art.
SUMMARY OF THE INVENTION
[0008] In one aspect of the invention, multi-layer electronic
device package includes first and second outer layers and at least
one signal layer disposed between the outer layers. The signal
layer includes signal traces and ground traces interleaved with the
signal traces.
[0009] In another aspect of the invention, a method of routing
signal traces in an electronic device package includes the acts of
disposing a plurality of signal traces in at least one substrate
layer, and interleaving a plurality of ground traces with the
signal traces.
[0010] In a further aspect of the invention, a semiconductor device
includes a first semiconductor die, a second semiconductor die, and
a multi-layer package, with the first die and the second die
mounted on the multi-layer package. The multi-layer package defines
at least one signal layer. Each signal layer includes signal traces
and ground traces interleaved therewith, with the signal traces
interconnecting the first die and the second die.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Other objects and advantages of the invention will become
apparent upon reading the following detailed description and upon
reference to the drawings in which:
[0012] FIG. 1 is a conceptualized, cross-sectional view of a
multi-layer package in accordance with an embodiment of the present
invention;
[0013] FIG. 2 is a conceptualized, cross-sectional view of a
multi-layer package having three signal layers in accordance with
an embodiment of the present invention;
[0014] FIG. 3 is a side view of an MCM employing a multi-layer
package in accordance with an embodiment of the present
invention;
[0015] FIG. 4 is a side view of a PCB assembly employing a
multi-layer package in accordance with an embodiment of the present
invention;
[0016] FIG. 5 illustrates a portion of a single layer of a
multi-layer package in accordance with aspects of the present
invention;
[0017] FIG. 6 is a block diagram illustrating a processor having an
external cache made up of a single memory die, employing a
multi-layer package in accordance with an embodiment of the present
invention;
[0018] FIG. 7 is a block diagram illustrating a processor device
having an external cache made up of two memory dice in a first
configuration, employing a multi-layer package in accordance with
an embodiment of the present invention; and
[0019] FIG. 8 is a block diagram illustrating a processor device
having an external cache made up of two memory dice in a second
configuration, employing a multi-layer package in accordance with
an embodiment of the present invention.
[0020] While the invention is susceptible to various modifications
and alternative forms, specific embodiments thereof have been shown
by way of example in the drawings and are herein described in
detail. It should be understood, however, that the description
herein of specific embodiments is not intended to limit the
invention to the particular forms disclosed, but on the contrary,
the intention is to cover all modifications, equivalents, and
alternatives falling within the spirit and scope of the invention
as defined by the appended claims.
DETAILED DESCRIPTION OF THE INVENTION
[0021] Illustrative embodiments of the invention are described
below. In the interest of clarity, not all features of an actual
implementation are described in this specification. It will of
course be appreciated that in the development of any such actual
embodiment, numerous implementation-specific decisions must be made
to achieve the developers' specific goals, such as compliance with
system-related and business-related constraints, which will vary
from one implementation to another. Moreover, it will be
appreciated that such a development effort, even if complex and
time-consuming, would be a routine undertaking for those of
ordinary skill in the art having the benefit of this
disclosure.
[0022] FIG. 1 illustrates a conceptualized cross-section of a
multi-layer electronic device package 10 in accordance with an
embodiment of the present invention. The exemplary package 10
includes two outer layers 12, 14. In one embodiment, the outer
layers comprise a ground (V.sub.SS) layer 12 and a power (V.sub.CC)
layer 14. Other outer layer arrangements are possible, such as two
outer ground layers in conjunction with an inner power layer. The
package 10 further includes at least one internal signal layer 16
disposed between the outer layers 12, 14. Each layer 12, 14, 16 of
the package comprises two portions, including an insulating portion
and a conductive portion disposed on, or incorporated with, the
insulating portion as discussed more fully below. In the present
specification, a "substrate layer" refers to any of the layers of
the multi-layer package, including both the insulating portion and
the conductive portion incorporated therewith.
[0023] The substrate layers 12, 14, 16 of the package 10 may be
fabricated out of any suitable substrate material, including
standard PCB materials such as Fire Retardant-4 ("FR-4"),
Bismaleimide Triazine ("BT"), ceramic, or an organic advanced
printed circuit board ("APCB") substrate material as is known in
the art. In typical PCB manufacture, conductive traces are formed
on each layer, then the layers are stacked and bonded together.
With an APCB material, the conductive traces may be built up upon
the nonconducting substrate using thin film approaches. Thus, with
an APCB substrate, the multiple layers are usually built-up by a
sequential process.
[0024] The signal layers of known multi-layer packages typically
define a plurality of conductive signal traces for routing signals
between components coupled to the package. In the embodiment of the
invention illustrated in FIG. 1, however, the signal layer 16
includes both ground (V.sub.SS) traces 22 and signal traces 24. The
traces 22, 24 are arranged such that the ground traces 22 shield
adjacent signal traces 24 from each other. The ground traces 22 are
"interleaved," or alternated with the signal traces 24 within the
is signal layer 16 to provide this shielding.
[0025] FIG. 2 illustrates a multi-layer package 11 in accordance
with an embodiment of the invention that includes three signal
layers 16, 18, 20. As in the embodiment illustrated in FIG. 1, the
ground traces 22 are interleaved with the signal traces 24 within
each of the signal layers 16, 18, 20. Alternative embodiments may
have some signal layers that have ground traces interleaved with
the signal traces to shield the signal traces, while other signal
layers do not have ground traces shielding the signal traces.
[0026] The ground traces 22 may further be arranged such that, in
addition to shielding adjacent signal traces 24 within a signal
layer, ground traces 22 are interleaved with signal traces 24
between layers, thus reducing cross-talk from signal traces 24 in
other signal layers. For example, as shown in FIG. 2, ground traces
22 in signal layer 18 are situated between aligned signal traces 24
in signal layers 16 and 20. Interleaving ground traces 22 with
signal traces 24 between layers may eliminate the need for
additional ground layers, increasing the potential signal density
without requiring additional device layers and associated costs of
adding a layer.
[0027] Multi-layer packages in accordance with the present
invention are particularly suitable in applications requiring
routing of several high-speed signals. For example, the signal
traces 24 may be used to route a plurality of signals between two
or more semiconductor devices mounted on the multi-layer package.
FIG. 3 illustrates an exemplary multi-chip module ("MCM") 40 in
accordance with an embodiment of the invention, in which two
semiconductor dice 42, 44 are mounted directly on a multi-layer
package 38 using any of several known methods, including wire
bonding, tape automated bonding ("TAB"), controlled collapse chip
connection ("C4"), etc. The package 38 includes a plurality of
layers 12, 14, 16, including at least one signal layer 16 having
signal traces and ground traces (not shown in FIG. 3) interleaved
in the manner described in conjunction with FIG. 1 and FIG. 2. In
embodiments employing multiple signal layers, the ground traces may
be further interleaved with signal traces between layers.
[0028] A plurality of vias 32 interconnect the substrate layers 12,
14, 16, and also couple the substrate layers 12, 14, 16 to the
semiconductor dice 42, 44. The vias 32 further couple the layers
12, 14, 16 and the semiconductor dice 42, 44 to the bottom surface
of the package 38, which in turn, may be coupled to another package
such as a system motherboard or other PCB with surface-mount or
through-hole techniques as are well known in the art.
[0029] FIG. 4 illustrates an exemplary PCB assembly 41, such as a
computer system motherboard, in accordance with aspects of the
present invention, wherein a multi-layer package 39 is embodied in
a PCB. Two or more semiconductor dice 42, 44 are disposed in
individual component packages 46, 48, which, for example, may
comprise pin grid array ("PGA") packages, ball grid array ("BGA")
packages, dual in-line packages ("DIP"), or other package types as
are known in the art. In the particular embodiment illustrated in
FIG. 5, the component packages 46, 48 comprise BGA packages that
are mounted on the multi-layer package 39 via a plurality of solder
balls 50.
[0030] The package 39 includes a plurality of layers 12, 14, 16,
including at least one signal layer 16 having signal traces and
ground traces (not shown in FIG. 4) interleaved in the manner
described in conjunction with FIG. 1 and FIG. 2. In embodiments
employing multiple signal layers, the ground traces may be further
interleaved with signal traces between layers. A plurality of vias
32 interconnects the layers 12, 14, 16 of the package 10, and also
connects the conductive portions of the layers 12, 14, 16 to the
solder ball array 50 of the component packages 46, 48.
[0031] The number of traces routed per layer may be limited in
various embodiments of the invention by, among other things, the
size of the package, the pitch and width of the traces, and the
diameter and horizontal pitch of the vias in various embodiments of
the invention. FIG. 5 illustrates an example of a portion of a
substrate layer 30 of a multi-layer package in accordance with
aspects of the present invention. The layer 30 defines a plurality
of vias 32 therethrough that interconnect the various layers of the
multi-layer package. Vias 32 also provide interconnections between
the components mounted on the package and the various layers of the
package. For example, in applications in which the components are
mounted on the package using C4, the vias terminate in a via land,
sometimes referred to as a "bump," to which the component connects.
A plurality of traces 34, comprising both signal and ground traces,
are disposed on the layer 30 in an interleaved manner as disclosed
above.
[0032] The relative size of the vias 32 and the traces 34, along
with the required spacing between the vias 32 and the traces 34,
influences the number of traces 34 that will fit between adjacent
vias 32 and is implementation specific. In one embodiment, the
trace pitch is about 74 .mu.m, the signal and ground traces 34 are
about 37 .mu.m wide, the via pitch is about 318 .mu.m and the
opening diameter of the vias 32 is about 150 .mu.m. Thus, two
traces 34 may be routed between vias 32 in this embodiment. FIG. 3
also illustrates a trace 36 that, while meeting the minimum pitch
requirements, is unroutable, or "trapped," due to the positioning
of the vias 32. In a particular embodiment having trace and via
pitch and sizes as described above, 250 signals were able to be
routed in a 18,500 .mu.m wide array.
[0033] The exemplary MCM 40 and PCB assembly 41 illustrated in FIG.
3 and FIG. 4 may comprise, for example, a processor device, such as
the type around which a computer is mounted. Processors typically
include various cache memories, including memory caches and disk
caches. A memory cache typically is a portion of memory made of
high-speed static random access memory ("SRAM") instead of the
slower and cheaper dynamic random access memory ("DRAM") used for
main memory. Memory caching is effective because most programs
access the same data or instructions over and over. By keeping as
much of this information as possible in SRAM, the computer avoids
accessing the slower DRAM.
[0034] Some memory caches are built into the architecture of
processors and are known as "internal" caches. Such internal caches
are often called primary, or Level 1 ("L1") caches. The processor
may access main memory and L1 caches via a system bus. Many
computers also come with external cache memory, often called Level
2 ("L2") caches. The processor may access the L2 cache via a
dedicated bus, sometimes referred to as a "backside bus." Like L1
caches, L2 caches are composed of SRAM, but they are typically much
larger. The L2 cache improves system-level performance by improving
the processor's memory read and write performance, as well as
decreasing the system bus utilization. The large L2 cache results
in less processor read requirements to main memory, thereby
reducing the number of times the processor needs to access the
system bus.
[0035] In a particular embodiment in accordance with aspects of the
present invention, a multi-layer package is used to implement a
backside bus that interconnects a processor and an external cache.
FIG. 6 illustrates such a processor device 70, including a
processor semiconductor die 62 and at least one cache semiconductor
die 64 coupled to a multi-layer package 66 having interleaved
signal and ground traces as disclosed herein above. FIG. 7 shows
another processor device 71 employing a processor semiconductor die
62 and two cache dice 64 situated on opposite sides of the
processor die 62. FIG. 8 illustrates yet another processor device
72 having two cache dice 64 situated to one side of a processor die
62 in a generally L-shaped configuration. In each of the
embodiments illustrated in FIG. 6, FIG. 7 and FIG. 8, the processor
62 may be any type of processor known to the art, and likewise, the
cache 64 may be any suitable memory device known to the art.
[0036] The processor die 62 and the one or more memory dice 64 are
interconnected by a backside bus 68 for routing signals
therebetween. The backside bus 68 comprises a plurality of signal
traces disposed within the signal layers of the multi-layer package
66 in the manner described in conjunction with FIG. 1 and FIG. 2.
The processor die 62 and memory dice 64 may be directly coupled to
the package 66, as illustrated in FIG. 3. Alternatively, the
processor and memory dice 62, 64 may be disposed in individual
component packages that are mounted on the package 66 in the manner
described in conjunction with FIG. 4.
[0037] To increase system performance, it is desirable to increase
the width (number of signal traces) of the backside bus, while
increasing processor speed. In other words, providing more
interconnections (conductive traces) between the processor 62 and
cache 64 would allow more signals to be transferred in a given time
period. However, problems such as cross-talk between signal traces
has limited the width of existing backside buses. Prior to the
present invention, routing signal traces in multiple signal layers
has been largely unsatisfactory, as traces in adjacent layers
typically may not be used simultaneously due to intense cross-talk
between the traces. Interleaving ground traces 22 with signal
traces 24 (referring to FIG. 1) reduces cross-talk, allowing
simultaneous use of traces in adjacent layers, thus providing a
greater density of usable signal traces 24 within a given package
space. Moreover, providing both signal and ground traces within a
layer may eliminate a ground layer in the package, providing
additional signal layers without the added expense and complication
of adding additional layers to the package.
[0038] The particular embodiments disclosed above are illustrative
only, as the invention may be modified and practiced in different
but equivalent manners apparent to those skilled in the art having
the benefit of the teachings herein. Furthermore, no limitations
are intended to the details of construction or design herein shown,
other than as described in the claims below. It is therefore
evident that the particular embodiments disclosed above may be
altered or modified and all such variations are considered within
the scope and spirit of the invention. Accordingly, the protection
sought herein is as set forth in the claims below.
* * * * *