U.S. patent application number 09/758221 was filed with the patent office on 2001-07-12 for non-volatile semiconductor memory device and semiconductor disk device.
Invention is credited to Kobayashi, Naoki, Kurata, Hideaki, Saeki, Shunichi.
Application Number | 20010007533 09/758221 |
Document ID | / |
Family ID | 18534819 |
Filed Date | 2001-07-12 |
United States Patent
Application |
20010007533 |
Kind Code |
A1 |
Kobayashi, Naoki ; et
al. |
July 12, 2001 |
Non-volatile semiconductor memory device and semiconductor disk
device
Abstract
A non-volatile semiconductor memory device is capable of having
its individual banks controlled separately from the outside, and a
semiconductor disk device is capable of proceeding immediately to
the next writing to a bank of non-volatile semiconductor memory
device which has become ready. Each bank has the independent write
operation of data from its data register to memory cells, enabling
the transfer of data from the outside to the data register of the
bank even during the write operation of other bank from the data
register to memory cells thereof.
Inventors: |
Kobayashi, Naoki; (Setagaya,
JP) ; Saeki, Shunichi; (Oume, JP) ; Kurata,
Hideaki; (Kokubunji, JP) |
Correspondence
Address: |
Antonelli, Terry, Stout & Kraus, LLP
Suite 1800
1300 North Seventeenth Street
Arlington
VA
22209
US
|
Family ID: |
18534819 |
Appl. No.: |
09/758221 |
Filed: |
January 12, 2001 |
Current U.S.
Class: |
365/185.11 |
Current CPC
Class: |
G11C 7/1078 20130101;
G11C 16/08 20130101; G11C 8/12 20130101; G11C 16/10 20130101; G11C
7/1087 20130101; G11C 2216/14 20130101 |
Class at
Publication: |
365/185.11 |
International
Class: |
G11C 011/34 |
Foreign Application Data
Date |
Code |
Application Number |
Jan 12, 2000 |
JP |
2000-006262 |
Claims
What is claimed is:
1. A non-volatile semiconductor memory device comprising a
plurality of banks each including a plurality of word lines, a
plurality of bit lines which are arranged to intersect the word
lines, a memory cell array made up of non-volatile memory cells
located at the intersections of the word lines and bit lines, and a
data register which temporarily holds data to be written which is
put in from the outside, each of said banks operating to select a
word line in accordance with an input command and the combination
of input address signals and write data which is held in the data
register to all or part of memory cells connected to the selected
word line, wherein each of said banks has an independent write
operation of data from the data register to memory cells, enabling
the transfer of data from the outside to the data register of said
bank even during the write operation of other bank from the data
register to memory cells thereof.
2. A non-volatile semiconductor memory device according to claim 1
further comprising a bank selection register which can take states
more than the number of said banks, thereby producing a signal for
pointing one of said banks depending on the state, said bank
selection register having its state established by an input signal
from the outside.
3. A non-volatile semiconductor memory device according to claim 2,
wherein the state of said bank selection register can be read out
from the outside.
4. A non-volatile semiconductor memory device according to claim 1
further comprising a plurality of input terminals of bank enable
signals, thereby producing a signal for pointing one of said banks
in accordance with the combination of the bank enable signals.
5. A non-volatile semiconductor memory device according to any of
claims 1 through 4, wherein said data transfer from the outside to
a bank takes place for the data register which belongs to the
selected bank.
6. A non-volatile semiconductor memory device according to any of
claims 1 through 4, wherein said device releases the state of the
selected bank in response to a status checking command from the
outside.
7. A non-volatile semiconductor memory device according to any of
claims 1 through 4, wherein a read, write, erase or status check
commands from the outside act only on a selected bank.
8. A semiconductor disk device which incorporates one or more
non-volatile semiconductor memory devices and makes access to said
non-volatile semiconductor memory devices in response to disk
access requests from a host, wherein said non-volatile
semiconductor memory devices have a total number (Nb) of banks of
two or more, and a controller device which is connected to said
non-volatile semiconductor memory devices and adapted to control
said non-volatile semiconductor memory devices has a data buffer
with a storage capacity which is greater than the total storage
capacity (A) of data registers included in said non-volatile
semiconductor memory devices and a buffer control table which
temporarily stores the correspondence between the data held by said
data buffer and the non-volatile semiconductor memory devices to
which the data is to be written.
9. A semiconductor disk device according to claim 8, wherein said
data buffer has a storage capacity of 2A or more.
10. A semiconductor disk device according to claim 8 or 9, wherein
said data buffer has storage areas of at least Nb in number which
can be addressed separately.
11. A semiconductor disk device according to claim 10, wherein said
buffer control table stores identifiers indicative of banks to
which data held by said buffer regions is to be transferred, said
device initiating the writing to said non-volatile semiconductor
memory devices while transferring data from a buffer area, which is
relevant to a bank which has become ready, to said bank.
12. A semiconductor disk device according to claim 11, wherein
information stored in the areas of said buffer control table
includes information which indicates the priority level of the
transfer of data held in the areas of said data buffer to said
non-volatile semiconductor memory devices.
13. A semiconductor disk device according to claim 11, wherein
information stored in the areas of said buffer control table
indicates as to whether data held in the regions of said data
buffer has been transferred to said non-volatile semiconductor
memory devices.
14. A semiconductor disk device according to claim 8, wherein said
buffer control table contains an information for addressing the
data buffer area for each bank of each non-volatile semiconductor
memory device, said data buffer area storing data to be transferred
to the bank, said device initiating the writing to said
non-volatile semiconductor memory devices while transferring data
from a buffer area, which is relevant to a bank which has become
ready, to said bank.
15. A semiconductor disk device according to claim 14, wherein
information for each bank stored in said buffer control table
includes a plurality of information for addressing the data buffer
area, said address information indicating the order of data
transfer to said banks.
16. A semiconductor disk device according to claim 14 or 15,
wherein said information for addressing the data buffer area is
designed to address areas of at least Nb in number of said data
buffer.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to a non-volatile
semiconductor memory device and a semiconductor disk device.
Specifically, the invention relates to the technique useful for
non-volatile memory devices capable of having their pieces of
stored information erased electrically at once (it will be called
"flash memory" hereinafter) and for semiconductor disk devices
which use the flash memory.
BACKGROUND OF THE INVENTION
[0002] FIG. 1 shows an example of the conventional semiconductor
disk device. This semiconductor disk device 99 is made up of a disk
controller 1 and one or more chips of flash memory 3. The
controller 1 includes a host interface logic circuit 14, a flash
control interface logic circuit 17, I/O buffers 15 and 16, an MPU
12, an MPU interface logic circuit 13, and a data transfer logic
circuit 11, and it implements data writing to the flash memory 3 in
response to a write request and for data transferred from the host
2 which is a workstation, personal computer, or the like.
[0003] FIG. 2 shows an example of the arrangement of the flash
memory 3. This example shows the arrangement including eight flash
memory chips indicated by 31 through 38. The flash memory chips
have individual lines 521 through 528 of chip select signals wired
from the controller 1 (the chip select signal lines 521-528 are
shown generically as a wiring 52 at the controller 1 and the
interconnection is not shown). Another wiring 51 represents a data
bus, address bus and various control signal lines, and it is a
common wiring to all flash memory chips. In other words, the
data-pin, the address pin and the control signal lines other than
the wiring 52 are had in common in the eight flash memory chips,
and for example, a signal line A0 in the address bus is connected
with each terminal A0 of the eight flash memory chips.
[0004] In this arrangement, the controller 1 controls each flash
memory chip by selecting a chip in accordance with the chip select
signal and issuing a command and address for data to be
written.
[0005] FIG. 3 shows the write operation of the conventional
semiconductor disk device which is arranged as shown in FIG. 2.
Shown by the flowchart is the case of sequential and cyclic data
writing to the flash memory chips 31-38.
[0006] Each block STSn (n=31,32, . . . ,38) is the operation of the
controller 1 to check the operational state of a flash memory chip
n, and it branches to the direction of Ready if the chip has Ready
status or to the direction of Busy if the chip has Busy status.
Each block DTn (n=31,32, . . . ,38) is the operation of the host 2
to issue a write command to a flash memory chip n and issue a
command of initiating the automatic write operation within the chip
for data to be written which is held by the data buffer. Following
the operation of DTn, the flash memory chip n writes the data to
memory cells based on the in-chip automatic write operation, and it
stays in Busy status until the end of writing.
[0007] The foregoing arrangement and operation enable the transfer
of data and the issuance of write command to the next flash memory
chip during the automatic write operation within the former chip,
and accomplish the speed-up of data writing based on the parallel
writing to multiple flash memory chips.
[0008] Recently, there has been devised an efficient flash memory
access method based on the early execution of write operation for a
flash memory chip which is early detected to be Ready, as
illustrated by FIG. 10 of Japanese Patent Unexamined Publication
No. H10-63442.
[0009] This patent publication No. H10-63442 shown by FIG. 10 is a
semiconductor disk having 16 flash memory chips, and for one
pattern of the write operation, it can proceeds to the write
operation for any flash memory chip which becomes Ready among three
flash memory chips having a high, medium and low write-in priority
levels.
[0010] However, there is given the description of the problem
occurring when the write operation is performed with the
aforementioned configuration.
[0011] There is considered the case in which as shown in FIG. 4, a
flash memory chip indicated by chip No. 1 (hereinafter, called chip
1) is a high write-in priority chip, chip 2 is a medium write-in
priority chip and chip 3 is a low write-in priority chip, and when
chips No. 8 and No. 13 are in Ready status and other chips than the
chips No. 8 and No. 13 are in Busy status, the write operation is
performed according to the flow chart as in FIG. 10 of the patent
publication No. H10-63442. Although the chip in which the write
operation is performed is checked its execution ability at the
steps S19, S21 and S23 as in the FIG. 10, the decision of the
execution ability is performed only for a high priority chip (chip
1) in the step S19, for a medium priority chip (chip 2) in the step
S21 and for a low priority chip (chip 3) in the step S23, and
despite the existence of chips (chips No. 8 and No. 13) being in
Ready status where the write operation is available, the decision
that the write operation is unavailable is made and while the write
operation is not performed, the next step S25 is proceeded.
[0012] In other words, in the conventional configuration, even if
there exists one or more flash memory chips being in Ready status
after the write operation is done earlier, there raises the problem
in which the next write operation can not be performed
immediately.
[0013] Recently, there has been introduced in Symp. on VLSI
Circuits Tech. Digest, 1996, pp. 174-175, a flash memory having
multiple banks (will be called "multi-bank flash memory") as a
scheme of increasing the number of bits of simultaneous writing on
a flash memory chip. However, the multi-bank flash memory chip has
Busy status during the writing of data to memory cells of one bank,
while other banks are left inaccessible. Therefore, this flash
memory is problematic in that individual banks cannot be controlled
separately from the outside.
SUMMARY OF THE INVENTION
[0014] The present invention is intended to deal with the foregoing
situation, and its prime object is to provide a semiconductor disk
device which has a plurality of flash memory chips or one or more
multi-bank flash memory chips and is capable of writing immediately
to a bank of flash memory chip or multi-bank flash memory chip
which has become Ready, and provide a non-volatile semiconductor
memory device having a multi-bank flash memory capable of having
its banks controlled separately from the outside.
[0015] These and other objects and novel features of the present
invention will become apparent from the following description of
specification taken in conjunction with the accompanying
drawings.
[0016] In the present invention disclosed in this specification, or
other objects and novel features are summarized as follows.
[0017] The inventive device has a plurality of banks, allows each
bank to operate independently to write data from its data register
to memory cells, and is capable of transferring write data from the
outside to the data register of each bank even during the write
operation of other bank from the data register to memory cells.
[0018] The inventive device has a bank selection register which
release a signal for designating one of the banks in accordance
with the bank status which is established by an external input
signal.
[0019] The device has a plurality of input terminals of bank enable
signals and produces an internal control signal which designates
one of the banks based on the combination of the bank enable
signals. Data to be written from the outside is transferred to the
data register of the designated bank. The device can indicate the
status of the designated bank in response to the external status
check command. The external read command, erase command, write
command and status polling command act on a designated bank.
[0020] The inventive device incorporates one or more non-volatile
semiconductor memory devices and makes access to said non-volatile
semiconductor memory devices in response to disk access requests
from a host, wherein the non-volatile semiconductor memory devices
have a total number (Nb) of banks of two or more, and a controller
device which is connected to the non-volatile semiconductor memory
devices and adapted to control the non-volatile semiconductor
memory devices has a data buffer with a storage capacity which is
greater than the total storage capacity (A) of data registers
included in the non-volatile semiconductor memory devices and a
buffer control table which temporarily stores the correspondence
between the data held by the data buffer and the non-volatile
semiconductor memory devices to which the data is to be
written.
[0021] The data buffer has a storage capacity of 2A or more. The
data buffer can be addressed for its divided areas of at least Nb
in number. The buffer control table stores for each area of data
buffer an identifier indicative of the destination bank of the data
to be written which is held in the buffer area, and the device
initiates the data writing to the non-volatile semiconductor memory
devices, while transferring data from a buffer area, which is
relevant to a destination which has become Ready, to the
destination.
[0022] Information stored for each area of the buffer control table
contains priority levels of the transfer of data from the area to
the non-volatile semiconductor memory device. Information stored
for each area of data buffer includes information which indicates
as to whether data held in the area has already been transferred to
the non-volatile semiconductor memory device. The buffer control
table stores, for each bank of the non-volatile semiconductor
memory device, information for addressing an data buffer area, and
the addressed area holds data to be transferred to the bank, so
that data from a bank which has become Ready is transferred and
written to the non-volatile semiconductor memory device.
Information of each bank stored in the buffer control table
includes address information of multiple data buffer areas
indicative of the order of transfer to the bank
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] FIG. 1 is a block diagram of the conventional semiconductor
disk device;
[0024] FIG. 2 is a block diagram showing the arrangement of the
non-volatile semiconductor memory device used for the semiconductor
disk;
[0025] FIG. 3 is a flowchart showing the write operation of the
conventional semiconductor disk;
[0026] FIG. 4 is a diagram used to explain the problem involved in
the conventional fast write operation;
[0027] FIG. 5 is a block diagram showing an example of the
semiconductor disk device based on this invention;
[0028] FIGS. 6A and 6B are block diagrams showing examples of the
arrangement of the data buffer of the inventive semiconductor disk
device;
[0029] FIG. 7 is a table showing an example of the arrangement of
the buffer control table of the inventive semiconductor disk
device;
[0030] FIG. 8 is a flowchart showing an example of the write
operation of the inventive semiconductor disk;
[0031] FIG. 9 is a table showing another example of the arrangement
of the buffer control table of the inventive semiconductor
disk;
[0032] FIG. 10 is a flowchart showing another example of the write
operation of the inventive semiconductor disk;
[0033] FIG. 11 is a block diagram showing an example of the
arrangement of the non-volatile semiconductor memory device having
multiple banks based on this invention;
[0034] FIG. 12 is a table showing another example of the
arrangement of the buffer control table of the inventive
semiconductor disk device;
[0035] FIG. 13 is a table showing another example of the
arrangement of the buffer control table of the inventive
semiconductor disk device;
[0036] FIG. 14 is a flowchart showing another example of the write
operation of the inventive semiconductor disk;
[0037] FIG. 15 is a flowchart showing another example of the write
operation of the inventive semiconductor disk;
[0038] FIG. 16 is a block diagram showing another example of the
arrangement of the non-volatile semiconductor memory device having
multiple banks based on this invention;
[0039] FIG. 17 is a block diagram showing another example of the
arrangement of the non-volatile semiconductor memory device based
on this invention; and
[0040] FIG. 18 is a block diagram showing another example of the
arrangement of the non-volatile semiconductor memory device based
on this invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
[0041] Preferred embodiments of the present invention will be
explained with reference to the drawings.
[0042] FIG. 5 shows by block diagram the arrangement of the
semiconductor disk device based on an embodiment of this invention.
This semiconductor disk device 99 is made up of a flash memory 3
and a controller 1. The flash memory 3 is formed of multiple flash
memory chips or one or more multi-bank flash memory chips. The
controller 1 includes a host interface logic circuit 14, a flash
control interface logic circuit 17, I/O buffers 15 and 16, an MPU
12, an MPU interface logic circuit 13, a data transfer logic
circuit 11, and a buffer control table 18, and it implements the
data writing to the flash memory 3 in response to a write request
and data transfer from a host 2 which is a workstation, personal
computer, or the like.
[0043] The MPU interface logic circuit 13 is an interface circuit
which connects the MPU 12 to the host interface logic circuit 14,
flash control interface logic circuit 17 and data transfer logic
circuit 11, and it functions to drive various control signals and
transfer data.
[0044] The MPU 12 functions to control the operation of the whole
semiconductor disk device, and specifically it implements the
address conversion from the host address which is used by the host
2 to make a disk access into the memory address which is used to
make access to the flash memory 3 and controls the access operation
for a selected flash memory chip.
[0045] A wiring 4 (will be called "external bus" 4) is to connect
the controller 1 to the host 2, and it includes a data bus, address
bus and various control signal lines.
[0046] The host interface logic circuit 14 is an interface which
conforms to the specifications of IDE or CMCIA for example, and it
is connected to the host 2 via the external bus 4.
[0047] A wiring 5 (will be called "memory bus" 5) is to connect the
controller 1 to the flash memory 3, and it includes an 8-bit I/O
data/address bus and various control signal lines.
[0048] The flash control interface logic circuit 17 is a hardware
logic which implements the access control of the flash memory under
control of the MPU 12, and it functions to drive various control
signals for the flash memory 3 thereby to transact data with the
flash memory 3 via the memory bus 5.
[0049] The I/O buffers 15 and 16 are input/output buffers connected
to the external bus 4 and memory bus 5, respectively.
[0050] The data transfer logic circuit 11 has a data buffer for
holding data to be written which is transferred from the host 2,
and it functions to transfer the data held by the data buffer to
the flash memory 3 via the flash control interface logic circuit 17
by being controlled by the MPU 12.
[0051] The buffer control table 18 is a temporary memory for
holding information which is used to control the data buffer in the
data transfer logic circuit 11.
[0052] It should be noted that the present invention is not
confined to the arrangement of FIG. 5, but it is possible to
provide a variant arrangement of a semiconductor disk device such
that the data transfer logic circuit 11 is included in the MPU
interface logic circuit 13.
[0053] Moreover, instead of the arrangement of the semiconductor
disk device made up of the controller 1 and flash memory 3, a
variant arrangement, which is assumed to be within the scope of the
present invention, is to arrange part or all of the controller 1 as
part of the host 2 for example so that the semiconductor disk is
formed of only the flash memory 3 or the flash memory 3 and part of
the controller 1.
[0054] Moreover, it is not obligatory for the componential members
of the controller 1 to be formed on a same semiconductor substrate,
but it is possible to form the MPU 12 and data buffer of the data
transfer logic circuit 11 on separate semiconductor substrates or
incase these members in separate packages.
[0055] The flash memory chips or multi-bank flash memory chips
which constitute the flash memory 3 are flash memories of the
command control type in which all their operations can be specified
by external commands, with the read and write operations taking
place in a certain unit data size (it will be called "page"), and
the flash memory chip has a data register for one page or the
multi-bank flash memory chip has a data register for pages equal in
number to the number of banks.
[0056] The data write operation from the data register to the
memory cell array can take place automatically without external
control, and the flash memory chip has Busy status during the
automatic data writing (the behavior of the multi-bank flash memory
will be explained later). The external system can confirm the end
of automatic data writing by checking the ready/busy signal
released by the chip or based on the status polling.
Embodiment 1
[0057] The first embodiment of this invention will be explained. In
this embodiment, the flash memory 3 shown in FIG. 5 is formed of
eight flash memory chips 31 through 38 configured as shown in FIG.
2. A memory bus 5 connects the controller and the memory chips as
shown in FIG. 2. Lines 521-528 of chip select signals are wired
from the controller 1 to the individual flash memory chips
separately. The chip select signal lines 521-528 are shown
generically as a wiring 52 at the controller 1 and the
interconnection is not shown. Another wiring 51 represents an 8-bit
I/O data/address bus and various control signal lines connected to
the control signal terminals of the flash memory chips, and it is
common to all flash memory chips.
[0058] In this arrangement of flash memory chips, the address, data
and various control signals sent from the controller 1 to the flash
memory 3 over the wiring 51 act only on a chip selected by a chip
select signal, so that each flash memory chip is controlled
separately.
[0059] In this embodiment, the data transfer logic circuit 11 is
equipped with eight data buffers 1101 through 1108 each having a
storage capacity of one page of the flash memory as shown in FIG.
6A. These eight data buffers may not be separated physically, but
can be a buffer memory which has a capacity of 8 pages, i.e., the
total capacity of the data registers of the eight flash memory
chips which form the flash memory 3, or more, and can be addressed
logically.
[0060] In this embodiment, the buffer control table 18 assigns
eight priority levels to the eight buffers, and each buffer with a
certain priority level has a buffer number, chip number, memory
address to be specified at data writing, and write-in flag
information as shown in FIG. 7. The buffer number is address
information for pointing the location for storing data of one page
in the buffer area, i.e., one of the data buffers 1101-1108. The
chip number is an identifier for the access to one of the eight
flash memory chips. The write-in flag information is to indicate as
to whether the contents of data buffer has been transferred to the
flash memory 3, e.g. , it has a value of "0" if data has been
transferred or "1" if data is not transferred yet.
[0061] Data transfer from the host 2 to the controller 1 takes
place for a data buffer with the highest priority level among data
buffers having write-in flag information of "0", and as a result,
that data buffer will have its write-in flag information set to
"1".
[0062] There can be a variant arrangement in which the buffer
control table 18 does not fill the information fields for data
buffers having write-in flag information of "0", i.e., data buffers
having their contents already transferred to the flash memory 3.
Namely, the write-in flag information can be substituted by the
presence or absence of information in the buffer information
fields.
[0063] FIG. 8 shows by flowchart an example of the write operation
of the inventive semiconductor disk device of the case of using the
contents of the buffer control table 18 shown in FIG. 7. Shown in
this example is the operation with successive data transfer from
the host to the semiconductor disk after the initiation of data
writing.
[0064] Each block BSTSn (n=1, 2, . . . , 8) is the operation to
check the information field with priority level n in the buffer
control table 18, and it branches to the direction of Flag=0 if the
write-in flag information is "0", to the direction of Ready if the
flash memory chip pointed by the chip information has Ready status
or to the direction of Busy if the chip has Busy status.
[0065] Each block DTBn (n=1,2, . . . ,8) is the operation of the
controller 1 to issue a write command to the designated flash
memory chip in accordance with the priority level n in the buffer
control table 18 and issue commands of initiating the transfer of
write data held by the data buffer and the automatic writing within
the chip. Following the operation of DTBn, the flash memory chip
writes the data in the data register to the memory cell array based
on the in-chip automatic write operation, and it stays in Busy
status until the end of writing.
[0066] The block of Table Update is the operation for revising the
buffer control table 18 after the transfer of data from the
controller 1 to the flash memory 3.
[0067] Based on the operational procedure shown in FIG. 8, each
flash memory chip with a priority level indicated by the buffer
control table 18 is checked for its write-in flag information and
Ready/Busy status. Specifically, if the write-in flag information
is "0", the operation returns to check the information of priority
level 1, or if the write-in flag information is "1" and the flash
memory chip is Ready, it transfers the write data held by the data
buffer, revises the buffer control table 18 and returns to the
checking of information of priority level 1. Otherwise, if the
write-in flag information is "1" and the flash memory chip is Busy,
the operation proceeds to the checking of information of the data
buffer having the 1-level lower priority. These operations are
repeated to write data to the semiconductor disk device.
[0068] According to the arrangement and operation of this
embodiment described above, it becomes possible for a flash memory
chip among all chips that has finished the writing early and become
Ready to proceed immediately to the next data writing, whereby the
efficient write operation without time wasting can be
accomplished.
[0069] Although in this embodiment, the eight flash memory chips
are provided with eight data buffers 1101-1108 each having a 1-page
capacity, a variant arrangement based on this invention is to
provide the eight flash memory chips with 16 data buffers 1101-1116
as shown in FIG. 6B. This arrangement further eliminates the time
wasting of a flash memory chip which has finished the writing twice
before other flash memory chip finishes the writing once.
[0070] Similarly, providing the data buffers with an increased
storage capacity accomplishes a semiconductor disk device which is
virtually rid of time wasting even in the presence of a large
disparity of the time of write operation among the flash memory
chips.
[0071] Although this embodiment is the case of eight flash memory
chips, the present invention is not confined to this
arrangement.
[0072] Although in this embodiment, there is no fixed combination
between the buffer number and the chip number in the buffer control
table 18, an alternative design is to provide a fixed chip number
for each buffer number so that each chip has a certain data
buffer.
Embodiment 2
[0073] Next, the second embodiment of this invention will be
explained. The flash memory 3 of this embodiment has the same
arrangement as that of the first embodiment shown in FIG. 5.
[0074] In this embodiment, the data transfer logic circuit 11 is
equipped with 16 data buffers 1101 through 1116 each having a
capacity of one page of the flash memory as shown in FIG. 6B. These
16 data buffers may not be separated physically, but can be a
buffer memory which can be addressed logically.
[0075] In this embodiment, the buffer control table 18 has fields
of buffer information 1 and buffer information 2 for the eight
flash memory chips as shown in FIG. 9. The buffer information 1 is
to point a data buffer which holds data to be written immediately
to the respective flash memory chip, and the buffer information 2
is to point a data buffer which holds data to be written next to
the data indicated by the buffer information 1. In case there is no
relevant data to be written, the buffer information field may be
filled with data or flag information indicative of "empty".
[0076] The flash memory address to which write data is written may
be stored together with the buffer information in the buffer
control table 18, or may be stored together with data in the data
buffer which is pointed by the buffer information. The chip number
is an identifier for the access to one of the eight flash memory
chips.
[0077] FIG. 10 shows by flowchart an example of the write operation
of the inventive semiconductor disk device of the case of using the
above-mentioned buffer control table 18. Shown in this example is
the operation with successive data transfer from the host to the
semiconductor disk after the initiation of data writing.
[0078] Each block CSTSn (n=1,2, . . . ,8) is the operation to check
the information field indicated by chip number n in the buffer
control table 18, and it branches to the direction of Ready if the
buffer information 1 is not "empty" and the designated flash memory
chip has Ready status, or to the direction of Busy if it has Busy
status.
[0079] Each block DTCn (n=1,2, . . . ,8) is the operation of the
controller 1 to issue a write command to the designated flash
memory chip in accordance with the chip number n in the buffer
control table 18 and issue commands of initiating the transfer of
data held by the data buffer pointed by the buffer information 1
and the automatic writing within the chip. Following the operation
of DTCn, the chip n writes the data in the data register to the
memory cell array based on the in-chip automatic write operation,
and it stays in busy status until the end of writing.
[0080] The block of Table Update is the operation for revising the
buffer control table 18 after the transfer of write data from the
controller 1 to the flash memory 3.
[0081] Based on the operational procedure shown in FIG. 10, each
flash memory chip pointed by the chip number in the buffer control
table 18 is checked for its Ready/Busy status. Specifically, if the
chip is Ready, the operation transfers the data which is held by
the data buffer, revises the buffer control table 18, and proceeds
to the checking of the information of chip No. 1. Otherwise, if the
chip is Busy, the operation proceeds to the checking of information
of the next chip number. These operations are repeated to write
data to the semiconductor disk device.
[0082] Although FIG. 10 shows the operational procedure in which
the revision of the buffer control table 18 is always followed by
the status checking for chip No. 1, a variant procedure is to check
the status of chip No. (n+1) after the revision of the buffer
control table 18 following the transfer of data to chip No. n. The
operation proceeds to the checking of chip No. 1 if n is the last
number.
[0083] According to the arrangement and operation of this
embodiment described above, it becomes possible for a flash memory
chip among all chips that has finished the writing early and become
Ready to proceed immediately to the next data writing, whereby the
efficient write operation without time wasting can be
accomplished.
[0084] Although in this embodiment, the eight flash memory chips
are provided with 16 data buffers 1101-1116 each having a 1-page
capacity, a variant arrangement based on this invention is to have
FIFO (first-in-first-out) data buffers of an arbitrary number,
which is greater than the number of flash memory chips, allotted to
the flash memory chips, and the present invention is not confined
in terms of the number of flash memory chips and the number of data
buffers.
[0085] Although in this embodiment, there is no fixed combination
between the buffer number and the chip number in the buffer control
table 18, an alternative design is to provide a fixed chip number
for each buffer number so that each chip has a certain data
buffer.
Embodiment 3
[0086] FIG. 11 shows an example of the arrangement of the
multi-bank flash memory based on this invention. The flash memory
has an address input terminal ADR, a control command input terminal
COM, a status output terminal STS for indicating the status of the
semiconductor memory device to the outside, a set of control signal
terminals C (including a chip enable signal terminal), a data
input/output terminal DIO, and power supply terminals (not shown).
With the provision of a multiplexer circuit within the chip, the
ADR, COM, DIO and STS signals can share terminals.
[0087] The flash memory incorporates an internal control signal
generation circuit CTR, a data input/output buffer circuit DB, an
address buffer circuit AB, memory arrays AR1 and AR2 having memory
cells MC at intersections of word lines W and bit lines D (only one
memory cell MC, word line W and bit line D are shown in each memory
cell array for the sake of simplicity), sense circuits and data
registers SDL, X-address decoder circuits XD which decode the
address signal to select word lines W of the arrays AR1 and AR2,
Y-address decoder circuits YD which decode the address signal to
select bit lines D of the arrays AR1 and AR2, and a bank selection
register SBR. The sense circuit and data register SDL can be simply
a sense circuit having a data holding function.
[0088] When the bank selection register SBR is used, there is an
advantage that the least control signal for controlling the flash
memory chip is required.
[0089] The memory cell arrays AR1 and AR2 are designed to operate
independently from each other as independent banks.
[0090] The non-volatile semiconductor memory device of this
arrangement has its operation controlled based on the distribution
to the componential circuits of the internal control signals
produced by the internal control signal generation circuit CTR
depending on the control signal CC, input command and the states of
the circuits.
[0091] The bank selection register SBR is designed to have at least
two states and produce a signal in the first state to indicate that
AR1 is the selected bank and produce a signal in the second state
to indicate that AR2 is the selected bank. The internal control
signal generation circuit CTR receives from the outside the read,
write, erase and status polling commands and the address signal for
the bank pointed by the bank selection register SBR, and produces
and sends the internal control signals to the bank.
[0092] Specifically, when the bank AR1 is pointed by the bank
selection register SBR, it is possible to distinguish the input
command to be a command for the bank AR1, so that it acts on the
bank AR1 irrespective of the Ready/Busy state of the bank AR2. For
example, during the write operation of data from the data register
SDL to the memory cell array of the bank AR2, it is possible to
transfer data from the outside to the data register of the bank
AR1.
[0093] For the above-mentioned performance, the multi-bank flash
memory of this embodiment is capable of reversing the bank pointing
information provided by the bank selection register SBR.
[0094] It is possible to alter the information held by the bank
selection register SBR in response to an external command for
example, and once information is set to the register SBR, it is
possible to keep the information unchanged until another
information is set. It is possible to read out the contents of the
bank selection register SBR in response to an external command.
[0095] It is possible to append the bank selecting information as
an argument to the read, write and status polling commands so as to
set the information to the bank selection register SBR.
[0096] Based on the above-mentioned arrangement, it becomes
possible to control multiple banks of one multi-bank flash memory
chip separately from the outside.
[0097] Although this embodiment is the case of two banks provided
for one multi-bank flash memory chip, the present invention is not
confined to this arrangement, but the invention is applicable to
the cases of three or more banks in one multi-bank flash memory
chip by designing the bank selection register to have states more
than the number of banks.
[0098] The third embodiment of this invention using the multi-bank
flash memory shown in FIG. 11 will be explained. In this
embodiment, the flash memory 3 of FIG. 5 is formed of four flash
memory chips arranged as shown in FIG. 17, although the present
invention is not confined to this arrangement.
[0099] The memory bus 5 shown in FIG. 5 connects the controller to
the memory chips as shown in FIG. 17. Lines 521 through 524 of chip
select signals are wired from the controller 1 to the individual
flash memory chips separately. The chip select signal lines 521-528
are shown generically as a wiring 52 at the controller 1 and the
interconnection is not shown. Another wiring 51 represents an 8-bit
I/O data/address bus and various control signal lines connected to
the control signal terminals of the flash memory chips, and it is
common to all flash memory chips.
[0100] In this arrangement, the address, data and various control
signals sent from the controller 1 to the flash memory 3 over the
I/O data/address bus of the wiring 51 act only on a chip selected
by a chip select signal, so that each flash memory chip is
controlled separately.
[0101] In this embodiment, the data transfer logic circuit 11 is
equipped with eight data buffers 1101 through 1108 each having a
capacity of one page of the flash memory as shown in FIG. 6A. These
eight data buffers may not be separated physically, but can be a
buffer memory which has a capacity of 8 pages, i.e., the total
capacity of the data registers of the eight flash memory chips
which form the flash memory 3, or more, and can be addressed
logically.
[0102] In this embodiment, the buffer control table 18 assigns
priority levels 1 through 8 to the eight data buffers, with each
column of table having fields of the buffer number, chip number,
bank number, memory address to be specified at data writing, and
write flag information as shown in FIG. 12. The buffer number is
address information for pointing the location for storing data of
one page in the data buffer area, i.e., one of the data buffers
1101-1108. The chip number is an identifier for the access to one
of the four multi-bank flash memories, the bank number is an
identifier for the access to one of the two multi-bank flash
memories, and the write-in flag information is to indicate as to
whether the contents of data buffer has been transferred to the
flash memory 3, e.g., it has a value of "0" if data has been
transferred or "1" if data is not transferred yet.
[0103] Data transfer from the host 2 to the controller 1 takes
place for a data buffer with the highest priority among data
buffers having write-in flag information of "0", and that data
buffer will have its write-in flag information set to "1".
[0104] There can be a variant arrangement in which the buffer
control table 18 does not fill the information fields for data
buffers having write-in flag information of "0", i.e., data buffers
having their contents already transferred to the flash memory 3.
Namely, the write-in flag information can be substituted by the
presence or absence of information in the buffer information
fields.
[0105] The write operation of the inventive semiconductor disk
device of the case of using the buffer control table 18 can be
based on the same procedure as the first embodiment shown in FIG.
8.
[0106] Each block BSTSn (n=1,2, . . . ,8) is the operation to check
the information field with priority level n in the buffer control
table 18, and it branches to the direction of Flag=0 if the
write-in flag information is "0", to the direction of Ready if the
bank of the specified channel number and bank number has Ready
status, or to the direction of Busy if the bank has Busy
status.
[0107] Each block DTBn (n=1,2, . . . ,8) is the operation of the
controller 1 to issue a write command to the specified bank of the
specified flash memory chip in accordance with the priority level n
in the buffer control table 18 and issue commands of initiating the
transfer of data held by the data buffer and the automatic writing
within the chip. Following the operation of DTBn, the bank of the
flash memory chip writes the data in the data register to the
memory cell array based on the in-chip automatic write operation,
and it stays in Busy status until the end of writing.
[0108] The block of Table Update is the operation for revising the
buffer control table 18 after the transfer of write data from the
controller 1 to the flash memory 3.
[0109] Based on the operational procedure shown in FIG. 8, the
specified bank of the specified multi-bank flash memory chip with a
priority level indicated by the buffer control table 18 is checked
for its write-in flag information and Ready/Busy status.
Specifically, if the write-in flag information is "0", the
operation returns to the checking of information with priority
level 1, or if the write-in flag information is "1" and the bank is
Ready, the operation transfers the data which is held by the data
buffer, revises the buffer control table 18, and proceeds to the
checking of the information of with priority level 1. Otherwise, if
the write-in flag information is "1" and the bank is Busy, the
operation proceeds to the checking of the information of the next
lower priority. These operations are repeated to write data to the
semiconductor disk device.
[0110] According to the arrangement and operation of this
embodiment described above, it becomes possible for a flash memory
chip among all chips that has finished the writing early and become
Ready to proceed immediately to the next data writing, whereby the
efficient write operation without time wasting can be
accomplished.
[0111] Although in this embodiment, the four multi-bank flash
memory chips each having two banks are provided with eight data
buffers 1101-1108 each having a 1-page capacity, a variant
arrangement based on this invention is to provide 16 data buffers
1101-1116 as shown in FIG. 6B, and in this case, it becomes
possible to eliminate the time wasting of a bank which has finished
the writing twice before other bank finishes the writing once.
[0112] Similarly, providing the data buffers with an increased
storing capacity accomplishes a semiconductor disk device which is
virtually rid of time wasting even in the presence of a large
disparity of the time of write operation among the banks.
[0113] Although this embodiment is the case of four flash memory
chips, the present invention is not confined to this
arrangement.
[0114] Although in this embodiment, there is no fixed combination
between the buffer number and the chip number and bank number in
the buffer control table 18, an alternative design is to provide a
fixed combination of the chip number and bank number for each
buffer number so that each bank has a certain data buffer.
Embodiment 4
[0115] Next, the fourth embodiment of this invention which uses the
multi-bank flash memory shown in FIG. 11 will be explained. In this
embodiment, the flash memory 3 of FIG. 5 has the same arrangement
as the case of the third embodiment.
[0116] The data transfer logic circuit 11 is equipped with 16 data
buffers 1101 through 1116 each having a capacity of one page of the
multi-bank flash memory as shown in FIG. 6B. These 16 data buffers
may not be separated physically, but can be a buffer memory which
can be addressed logically.
[0117] In this embodiment, the buffer control table 18 has fields
of buffer information 1 and buffer information 2 for two banks of
each multi-bank flash memory chip as shown in FIG. 13. The buffer
information 1 is to point a data buffer which holds data to be
written immediately to the respective bank, and the buffer
information 2 is to point a data buffer which holds data to be
written next to the data indicated by the buffer information 1. In
case there is no relevant data to be written, the buffer
information field may be filled with data or flag information
indicative of "empty".
[0118] The multi-bank flash memory address to which write data is
written may be stored together with the buffer information in the
buffer control table 18, or may be stored together with write data
in the data buffer which is pointed by the buffer information. The
chip number is an identifier for the access to one of the four
flash memory chips, and the bank number is an identifier for the
access to one of the two banks of multi-bank flash memory.
[0119] FIG. 14 shows by flowchart an example of the write operation
of the inventive semiconductor disk device of the case of using the
contents of the foregoing buffer control table 18. Shown in this
example is the operation of successive data transfer from the host
to the semiconductor disk after the initiation of data writing.
[0120] Each block CSTSnm (n=1,2,3,4;m=1,2) is the operation to
check information field indicated by chip number n and bank number
m in the buffer control table 18, and it branches to the direction
of Ready if the buffer information 1 is not "empty" and the pointed
flash memory chip has Ready status, or to the direction of Busy if
it has Busy status.
[0121] Each block DTCnm (n=1,2,3,4;m=1,2) is the operation of the
controller 1 to issue a write command to the specified bank of chip
n in accordance with the information field indicated by the chip
number n and bank number m in the buffer control table 18 and issue
commands of initiating the transfer of data held by the data buffer
indicated by the buffer information 1 and the automatic writing
within the chip.
[0122] The block of Table Update is the operation for revising the
buffer control table 18 after the transfer of write data from the
controller 1 to the flash memory 3.
[0123] Based on the operational procedure shown in FIG. 14, the
flash memory chips specified by the combination of the chip number
and bank number indicated by the buffer control table 18 are
checked for their Ready/Busy status. Specifically, if a flash
memory chip is Ready, the operation takes place to transfer the
data held by the data buffer and revise the buffer control table
18, and it proceeds to the checking of the information relevant to
chip No. 1 and bank No. 1. Otherwise, if the flash memory chip is
Busy, the operation proceeds to the checking of the information
relevant to the combination of the next chip number and bank
number. These operations are repeated to write data to the
semiconductor disk device.
[0124] Although shown in this example is the operation of status
checking, which takes place always for bank No. 1 of chip No. 1
after the buffer control table 18 has been revised, a variant
operational procedure after the transfer of data to one bank
following the revision of the buffer control table 18 is to check
the status for a bank other than bank No. 1 of chip No. 1.
[0125] According to the arrangement and operation of this
embodiment described above, it becomes possible for a bank among
all banks of all multi-bank flash memory chips that has finished
the writing early and become Ready to proceed immediately to the
next data writing, whereby the efficient write operation without
time wasting can be accomplished.
[0126] Although in this embodiment, the four multi-bank flash
memory chips each having two banks are provided with 16 data
buffers 1101-1116 each having a 1-page capacity, a variant
arrangement based on this invention is to have FIFO data buffers of
an arbitrary number, which is greater than the number of multi-bank
flash memory chips, allotted to the flash memory chips, and the
present invention is not confined in terms of the number of chips,
number of banks and number of data buffers.
[0127] Although in this embodiment, there is no fixed combination
between the buffer number and the chip number and bank number in
the buffer control table 18, an alternative design is to provide a
fixed combination of the chip number and bank number for each
buffer number so that each bank has a certain data buffer.
[0128] The present invention is not confined in terms of the order
of checking among the banks of each multi-bank flash memory chip,
but it is also possible to write data in the order as shown in FIG.
15 for example.
Other Embodiments
[0129] FIG. 16 shows another example of the arrangement of the
multi-bank flash memory based on this invention. The flash memory
has an address input terminal ADR, a control command input terminal
COM, a status output terminal STS for indicating the status of the
semiconductor memory device to the outside, a set of control signal
terminals CC excluding BE1 and BE2, a data input/output terminal
DIO, a bank No. 1 enable signal terminal BE1, a bank No. 2 enable
signal terminal BE2, and power supply terminals (not shown). With
the provision of a multiplexer circuit within the chip, the ADR,
COM, DIO and STS signals can share terminals.
[0130] The flash memory incorporates an internal control signal
generation circuit CTR, a data input/output buffer circuit DB, an
address buffer circuit AB, memory arrays AR1 and AR2 having memory
cells MC at intersections of word lines W and bit lines D (only one
memory cell MC, word line W and bit line D are shown in each memory
cell array for the sake of simplicity), sense circuits and data
registers SDL, X-address decoder circuits XD which decode the
address signal to select word lines W of the arrays AR1 and AR2,
and Y-address decoder circuits YD which decode the address signal
to select bit lines D of the arrays AR1 and AR2. The sense circuit
and data register SDL can be simply a sense circuit having a data
holding function. The memory cell arrays AR1 and AR2 are designed
to operate independently from each other as independent banks.
[0131] When the bank enable signals are used, since each bank is
selected and controlled by the individual selection signals BE1 and
BE2, the multi-bank flash memory of the present invention has an
equivalent function to the case where two of the conventional one
bank flash memory chip are used.
[0132] Therefore, for example, in the device having the two of the
conventional one bank flash memory chip, when the two of the one
bank flash memory chip are replaced with the multi-bank flash
memory chip of the present invention, there is an advantage that
the least modification of the firmware is required.
[0133] The non-volatile semiconductor memory device of this
arrangement has its operation controlled based on the distribution
to the componential circuits of the internal control signals
produced by the internal control signal generation circuit CTR
depending on the control signals CC, input command, bank enable
signals BE1 and BE2, and the states of the circuits. The bank
enable signal BE1 or BE2 in the active state points the memory
array AR1 or AR2 to be the selected bank.
[0134] The internal control signal generation circuit CTR receives
from the outside the read, write, erase and status polling commands
and the address designation for a bank selected by a bank enable
signal, and produces and sends the internal control signals to the
bank.
[0135] Specifically, when the bank AR1 is selected by the bank
enable signal, it is possible to distinguish the input command to
be a command for the bank AR1, so that it acts on the bank AR1
irrespective of the Ready/Busy state of the bank AR2. For example,
during the write operation of data from the data register SDL to
the memory cell array of the bank AR2, it is possible to transfer
data from the outside to the data register of the bank AR1.
[0136] Based on the above-mentioned arrangement, it becomes
possible to control multiple banks of one multi-bank flash memory
chip separately from the outside.
[0137] Although this embodiment is the case of two banks provided
for one multi-bank flash memory chip, the present invention is not
confined to this arrangement, but the invention is applicable to
the cases of three or more banks in one multi-bank flash memory
chip by designing the bank enable signals to take states more than
the number of banks.
[0138] At this time, the number of lines for the bank enable
signals may be prepared so that the status taken by the bank enable
signals is greater than the number of banks by one or more. In
other words, if the multi-bank flash memory chip has seven banks,
there may be provided at least three bank enable signals. This is
because total eight kinds of status can be represented by setting
the three bank enable signals to a high or a low status.
[0139] Specifically, for example, for a multi-bank flash memory
having four banks, the number of states which the bank enable
signals need to have is four for selecting the four banks plus one
state for no bank selection, and it is enough for three bank enable
signals, which can have eight states, to produce these five
states.
[0140] FIG. 18 shows an example for the arrangement of the flash
memory 3 in the case of using the foregoing multi-bank flash memory
for the semiconductor disk of FIG. 5, which is formed of four flash
memory chips in this example.
[0141] The memory bus 5 shown in FIG. 5 connects the controller to
the memory chips as shown in FIG. 18. Lines 5211 through 5214 and
lines 5221 through 5225 of chip select signals BE1 and BE2 are
wired from the controller 1 to the individual multi-bank flash
memory chips separately. The bank select signal lines 5211-5224 are
shown generically as a wiring 52 at the controller 1 and the
interconnection is not shown. Another wiring 51 represents an 8-bit
I/O data/address bus and various control signal lines connected to
the control signal terminals of the multi-bank flash memory chips,
and it is common to all flash memory chips.
[0142] In this arrangement, the address, data and various control
signals sent from the controller 1 to the flash memory 3 over the
I/O data/address bus of the wiring 51 act only on a bank selected
by a bank enable signals, so that each bank of each multi-bank
flash memory chip is controlled separately.
[0143] As a variant arrangement of the foregoing multi-bank flash
memory used for the semiconductor disk of FIG. 5, only chip select
signals of multi-bank flash memory chips are wired separately, with
the bank enable signals BE1 and BE2 being wired commonly to all
flash memory chips, and in this case, it becomes possible to
control each bank of each multi-bank flash memory chip based on the
combination of a chip select signal and a bank enable signal.
[0144] In consequence, there is accomplished a semiconductor disk
device which uses the foregoing multi-bank flash memory and is
capable of controlling the banks individually, and this
semiconductor disk device can write data efficiently based on the
operational procedures shown in FIG. 8, FIG. 14 and FIG. 15 as in
the case of the semiconductor disk device using the multi-bank
flash memory shown in FIG. 11.
[0145] Although the foregoing embodiments of the semiconductor disk
device using the multi-bank flash memory have the same number of
banks in all multi-bank flash memory chips, the present invention
is also applicable to the arrangement of multi-bank flash memory
chips having different numbers of banks or the arrangement
including flash memory chips having only one bank.
[0146] It is possible for all of the foregoing embodiments to have
a flash memory or multi-bank flash memory of the type of
multi-value memory in which each memory cell can store more than
one bit.
[0147] As described above, the present invention accomplishes a
fast-writing semiconductor disk device and a method of writing on
the disk based on the ability of immediate initiation of the next
write operation of a non-volatile semiconductor memory device which
has finished the writing early.
[0148] Furthermore, the present invention enables the control of
individual banks of a non-volatile semiconductor memory device from
the outside.
* * * * *