U.S. patent application number 09/750226 was filed with the patent office on 2001-07-05 for method for forming a gate insulating film for semiconductor devices.
Invention is credited to Park, Dong Su.
Application Number | 20010006843 09/750226 |
Document ID | / |
Family ID | 19631881 |
Filed Date | 2001-07-05 |
United States Patent
Application |
20010006843 |
Kind Code |
A1 |
Park, Dong Su |
July 5, 2001 |
Method for forming a gate insulating film for semiconductor
devices
Abstract
A method for forming a gate insulating film for a semiconductor
device comprising forming an insulating film of silicon nitride or
silicon oxynitride in the active regions of the semiconductor
substrate; forming an amorphous TaON insulating film on the
insulating film; and crystallizing the amorphous TaON insulating
film. Using TaON as the primary gate insulating film provides a
high dielectric constant (.epsilon.=20.about.25), and thus produces
a gate insulating film having properties superior to those possible
with silicon dioxide gate films and thus more suitable for use in
highly integrated semiconductor devices.
Inventors: |
Park, Dong Su; (Kyoungki-do,
KR) |
Correspondence
Address: |
Pillsbury Madison & Sutro LLP
Intellectual Property Group
East Tower, Ninth Floor
1100 New York Avenue, NW.
Washington
DC
20005-3918
US
|
Family ID: |
19631881 |
Appl. No.: |
09/750226 |
Filed: |
December 29, 2000 |
Current U.S.
Class: |
438/591 ;
257/E21.194; 438/287; 438/786 |
Current CPC
Class: |
H01L 21/28176 20130101;
H01L 29/513 20130101; H01L 29/518 20130101; H01L 21/28202 20130101;
H01L 21/28185 20130101 |
Class at
Publication: |
438/591 ;
438/287; 438/786 |
International
Class: |
H01L 021/336; H01L
021/4763; H01L 021/469 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 29, 1999 |
KR |
99-64610 |
Claims
What is claimed is:
1. A method for forming a gate insulating film for a semiconductor
device, comprising the steps of: providing a semiconductor
substrate comprising active regions and isolation regions; forming
an insulating film containing nitrogen on the exposed surface of
the semiconductor substrate; forming an amorphous TaON insulating
film on the insulating film; and crystallizing the amorphous TaON
insulating film.
2. The method according to claim 1, wherein the insulating film
containing nitrogen comprises a silicon nitride or a silicon
oxynitride film.
3. The method according to claim 2, wherein the step of forming the
insulating film containing further comprises forming a silicon
nitride film in a LPCVD chamber, the LPCVD chamber being operated
at a temperature between 200 and 600.degree. C., by the reaction of
the semiconductor substrate and NH.sub.3 or a mixture of N.sub.2
and H.sub.2 or forming a silicon oxynitride film in a LPCVD
chamber, the LPCVD chamber being operated at a temperature between
200 and 600.degree. C., by the reaction of the semiconductor
substrate and NH.sub.3 and O.sub.2 or N.sub.2O.
4. The method according to claim 3, wherein the step of forming the
silicon oxynitride film further comprises the steps of introducing
NH.sub.3 into the LPCVD chamber for a first period of time and
subsequently introducing a mixture of NH.sub.3 and O.sub.2 or
N.sub.2O into the LPCVD chamber for a second period of time.
5. The method according to claim 1, wherein the step of forming an
amorphous TaON insulating film further comprises supplying a
predetermined amount of a Ta compound to an evaporator through a
flow controller, evaporating the Ta compound at a temperature
ranging from 150 to 200.degree. C. to form a Ta chemical vapor, and
injecting the Ta chemical vapor into a LPCVD chamber.
6. The method according to claim 1, wherein the step of forming an
amorphous TaON insulating film further comprises supplying
predetermined amounts of a Ta chemical vapor, O.sub.3 and/or
O.sub.2 and NH.sub.3 to a LPCVD chamber, operating the LPCVD
chamber at a temperature between 300 and 600.degree. C., at a
pressure of less than 100 Torr, and with a power of from 0.15 to 2
torr (in a low pressure process) or 50 to 300 torr (in a high
pressure process) applied to induce a surface chemical reaction
between the Ta chemical vapor, O.sub.3 and NH.sub.3.
7. The method according to claim 1, wherein the step of
crystallizing the amorphous TaON insulating film further comprises
annealing the amorphous TaON insulating film.
8. The method according to claim 7, wherein the step of annealing
the amorphous TaON insulating film further comprises heating the
TaON insulating film to a temperature within a temperature range
between 650 and 950.degree. C. and maintaining the TaON insulating
film within this temperature range for a period of time between 0.5
and 30 minutes.
9. The method according to claim 7, wherein the step of annealing
the amorphous TaON insulating film further comprises heating the
TaON insulating film under an atmosphere of N.sub.2O, O.sub.2 or
N.sub.2 to a temperature within a temperature range between 650 to
950.degree. C. maintaining the TaON insulating film within this
temperature range for a period of time between 1 to 30 minutes.
10. The method according to claim 1, further comprising nitriding
or oxynitriding the surface of the amorphous TaON insulating film
with a plasma treatment under an atmosphere of NH.sub.3 or N.sub.2
and H.sub.2 at a temperature ranging from 200 to 600.degree. C.
11. The method according to claim 10, wherein the step of nitriding
or oxynitriding the surface of the amorphous TaON insulating film
replaces the step of crystallizing the amorphous TaON insulating
film.
12. A method for forming a gate insulating film for a semiconductor
device, comprising the steps of: providing a semiconductor
substrate comprising active regions and device isolation regions,
the surface of the semiconductor being exposed in the active
regions; forming an insulating film on the active regions of the
semiconductor substrate; forming an amorphous TaON insulating film
on the SiN or SiON film; and crystallizing the amorphous TaON
insulating film.
13. The method according to claim 12, wherein the step of forming
an insulating film further comprises forming a silicon nitride film
in a LPCVD chamber, the LPCVD chamber being operated at a
temperature of between 200 and 600.degree. C., under an atmosphere
of NH.sub.3 or N.sub.2 and H.sub.2.
14. The method according to claim 12, wherein the step of forming
an insulating film further comprises forming a silicon oxynitride
film in a LPCVD chamber, the LPCVD chamber being operated at a
temperature between 200 and 600.degree. C., under an atmosphere of
NH.sub.3 and O.sub.2 or N.sub.2O.
15. The method according to claim 12, wherein the step of forming
an amorphous TaON insulating film further comprises obtaining a Ta
chemical vapor by supplying a fixed amount of a Ta compound an
evaporator through a mass flow controller, and evaporating the Ta
compound at a temperature ranging from 150 to 200.degree. C.
16. The method according to claim 12, wherein the step of forming
an amorphous TaON insulating film further comprises supplying
predetermined amounts of a Ta chemical vapor, O.sub.3 and/or
O.sub.2 and NH.sub.3 to a LPCVD chamber, operating the LPCVD
chamber at a temperature between 300 and 600.degree. C., at a
pressure of less than 100 Torr, and with a power of from 0.15 to 2
torr (in a low pressure process) or 50 to 300 torr (in a high
pressure process) applied to induce a surface chemical reaction
between the Ta chemical vapor, O.sub.3 and NH.sub.3.
17. The method according to claim 12, wherein the step of
crystallizing the amorphous TaON insulating film further comprises
annealing the amorphous TaON insulating film.
18. The method according to claim 17, wherein the step of annealing
the amorphous TaON insulating film further comprises heating the
TaON insulating film to a temperature within a temperature range
between 650 and 950.degree. C. and maintaining the TaON insulating
film within this temperature range for a period of time between 0.5
and 30 minutes.
19. The method according to claim 17, wherein the step of annealing
the amorphous TaON insulating film further comprises heating the
TaON insulating film under an atmosphere of N.sub.2O, O.sub.2 or
N.sub.2 to a temperature within a temperature range between 650 to
950.degree. C. maintaining the TaON insulating film within this
temperature range for a period of time between 1 to 30 minutes.
20. The method according to claim 12, further comprising nitriding
the surface of the amorphous TaON insulating film with a plasma
treatment under an atmosphere of NH.sub.3 or N.sub.2 and H.sub.2 at
a temperature ranging from 200 to 600.degree. C.
21. A method for forming a gate insulating film for a semiconductor
device, comprising the steps of: providing a semiconductor
substrate, the semiconductor comprising active regions separated by
device isolating regions, the device isolating regions comprising
field oxide; forming an insulating film containing nitrogen on the
active regions of the semiconductor substrate; forming an amorphous
TaON insulating film on the insulating film; and crystallizing the
amorphous TaON insulating film.
22. The method according to claim 21, wherein the step of
crystallizing the amorphous TaON insulating film further comprises
annealing the TaON insulating film with a rapid thermal treatment
at a temperature ranging from 650 to 950.degree. C., the duration
of the rapid thermal treatment being between 0.5 minute and 30
minutes.
23. The method according to claim 21, wherein the step of
crystallizing the amorphous TaON insulating film further comprises
annealing the TaON insulating film in an electric furnace for
between 1 and 30 minutes under an atmosphere of N.sub.2O, O.sub.2
or N.sub.2 at a temperature ranging from 650 to 950.degree. C.
24. The method according to claim 21, further comprising a step for
nitriding the surface of the amorphous TaON insulating film in an
atmosphere of NH.sub.3 or N.sub.2/H.sub.2 at a temperature ranging
from 200 to 600.degree. C.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a method for forming a gate
insulating film for a semiconductor device, and in particular to an
improved method for forming a gate insulating film for a high
integration semiconductor device which has a superior electric
property.
[0003] 2. Description of the Background Art
[0004] In general, in a metal oxide semiconductor field effect
transistor (MOSFET), the gate electrodes are isolated from the
substrate by a thin, high quality, silicon dioxide film that is
referred to as the gate oxide or gate insulating film. By
insulating the gate electrodes from the substrate, MOSFET devices
provide reduced impedance when compared with equivalent junction
effect transistors (JFET). In addition, the silicon dioxide gate
insulating film is easily formed by a single and relatively brief
thermal oxidation process, making the process generally suitable
for even highly integrated semiconductor devices.
[0005] However, as the level of integration of semiconductor memory
devices has increased, the size of the various components that
define a functional unit cell have become even more miniaturized.
For a DRAM cell transistor, this has required reductions in both
the thickness of the gate insulating film and the gate width. For
example, advanced memory devices such as a 256M DRAM generally use
a conventional gate insulating film of approximately 50 .ANG.of
silicon dioxide that is formed in a wet oxidation process at
between 800 and 900.degree. C. to obtain the necessary device
properties. The minimum thickness of the silicon dioxide gate
insulating film is, however, limited by the need to maintain
adequate breakdown resistance and other parametric properties.
[0006] Recently, a Ta.sub.2O.sub.5 film having a higher dielectric
constant (.epsilon. of approximately 25) has been used as the gate
insulating film for highly integrated memory devices as an
alternative to the conventional SiO.sub.2 film. However, because
the deposited Ta.sub.2O.sub.5 film has an relatively unstable
stoichiometry, vacancy Ta atoms resulting from variations in the
composition ratio between the component Ta and O atoms will be
present in the thin film. Further, during the deposition of the
Ta.sub.2O.sub.5 gate insulating film various contaminants such as
carbon (C), carbon compounds (CH.sub.4, C.sub.2H.sub.4, etc.) and
water vapor (H.sub.2O) may be generated and incorporated into the
film. This contaminants are the result of byproduct reactions
between the organic metal precursor, such as
Ta(OC.sub.2H.sub.5).sub.5 or Ta(N(CH.sub.3).sub.2).sub.5, and the
reaction gas, typically O.sub.2 or N.sub.2O, in the deposition
chamber.
[0007] These contaminants, as well as other ions or radicals
present in the film, will result in increased leakage currents and
degraded dielectric properties if left untreated. In order to
overcome such a disadvantage, the deposited Ta.sub.2O.sub.5 film is
typically subjected to at least one low temperature thermal
treatment (for example, a plasma N.sub.2O or UV-O.sub.3 treatment)
and at least one high temperature thermal treatment. These thermal
treatments are, however, rather complicated and can produce in
other undesirable results. For example, because the Ta.sub.2O.sub.5
can act as a strong oxidizer, it can react with the silicon
substrate during the high temperature thermal treatment and form a
heterogeneous parasitic oxide film at the interface. This parasitic
oxide film degrades the electrical properties of the
Ta.sub.2O.sub.5 gate insulating film and increases the thickness of
the gate insulating film.
SUMMARY OF THE INVENTION
[0008] Accordingly, a primary object of the present invention is to
provide a method for forming a gate insulating film for a
semiconductor device that exhibits superior electric
properties.
[0009] Another object of the present invention is to provide a
method for forming a gate insulating film for a semiconductor
device that prevents degradation or deterioration of the electric
properties of the resulting semiconductor device.
[0010] Still another object of the present invention is to provide
a method for forming a gate insulating film for a semiconductor
device that simplifies the fabrication process.
[0011] Still another object of the present invention is to provide
a method for forming a gate insulating film for a semiconductor
device that can increase the life span of the resulting
products.
[0012] In order to achieve these objects, the present invention
provides a method for forming a gate insulating film for a
semiconductor device including the steps of: providing a
semiconductor substrate where a field oxide film for defining an
active region and a device isolating region has been formed;
forming an insulating film containing nitride on the exposed
surface of the semiconductor substrate; forming an amorphous TaON
insulating film on the insulating film; and crystallizing the
amorphous TaON insulating film.
[0013] In addition, the present invention provides a method for
forming a gate insulating film for a semiconductor device,
including the steps of: providing a semiconductor substrate where a
field oxide film for defining an active region and a device
isolating region has been formed; forming an SiN or SiON film on
the exposed surface of the semiconductor substrate; forming an
amorphous TaON insulating film on the SiN or SiON film; and
crystallizing the amorphous TaON insulating film.
[0014] The present invention also provides a method for forming a
gate insulating film for a semiconductor device, including the
steps of: providing a semiconductor substrate where a field oxide
film for defining an active region and a device isolating region
has been formed; forming an insulating film containing nitride on
the exposed surface of the semiconductor substrate; forming an
amorphous TaON insulating film on the insulating film; and
crystallizing the amorphous TaON insulating film according to an
annealing process.
[0015] The above objects, and other features and advantages of the
present invention will become more apparent in light of the
following detailed description and the accompanying figures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIGS. 1 to 5 are cross-sectional views illustrating
sequential steps of a method for forming a gate insulating film for
a semiconductor device in accordance with the present
invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0017] Referring to FIG. 1, a field oxide film 12 is formed on a
semiconductor substrate 10 to define an active region and a device
isolating region according to a conventional device isolation
process such as LOCOS or trench processes. As illustrated in FIG.
2, the surface of the substrate 10 in the action region is then
cleaned, typically using chemicals such as HF, SC-1 (NH.sub.4OH
mixture in which NH.sub.4OH+H.sub.2O.sub.2+H.sub.2O is mixtured to
a rate of 1:4:20) and/or H.sub.2SO.sub.4 to remove any natural
oxide film, particles, or other contaminants.
[0018] After the surface of the substrate has been cleaned, a
silicon nitride (Si.sub.xN.sub.y; Si-N bond) or silicon oxynitride
(SiON) film 14 is formed on the surface of the substrate. This film
14 prevents the formation of a heterogeneous oxide film having a
low dielectric constant at the interface between the substrate 10
and the gate insulating film during subsequent processing such as
the deposition of an amorphous TaON film. A suitable Si.sub.xNy(
Si-N bond) film may be formed in a low pressure chemical vapor
deposition (LPCVD) chamber operating at 200 to 600.degree. C. by
forming a plasma and supplying ammonia (NH.sub.3) or forming gas
(N.sub.2/H.sub.2). Alternatively, a SiON film may be formed in the
low pressure chemical vapor deposition chamber at 200 to
600.degree. C., by forming a plasma and supplying a mixture of
ammonia (NH.sub.3) and oxygen (O.sub.2) (for example, a ratio of
NH.sub.3:O.sub.2 is 0.5:1 to 10:1, or preferably 3:1 to 5:1) and/or
N.sub.2O gas through a mass flow controller at 10 to 1000 sccm.
[0019] A process of forming SiON film is carried out under a power
of 50 to 600 W and a pressure of 0.2 to 10 torr.
[0020] Preferably, in the formation of a SiON film, NH.sub.3 is
injected into the deposition chamber for an initial period before
beginning the injection of the O.sub.2 and/or N.sub.2O to further
suppress formation of a parasitic oxide film on the surface of the
substrate 10.
[0021] Thus, in contrast to the conventional method, the surface of
substrate 10 is nitrided (or oxynitrided) at a low temperature of
200 to 600.degree. C. before depositing the amorphous TaON film.
This nitriding (or oxynitriding) process helps maintain the
electric properties the subsequent thin films and resulting
device.
[0022] As depicted in FIG. 3, an amorphous TaON film 16 is then
deposited on the SiN or SiON film 14 using a LPCVD process. A gate
insulating film is actually the stacked structure of the SiN or
SiON film 14 and amorphous TaON film 16.
[0023] The TaON film 16 is the product of the reaction between a
tantalum-containing organic metal compound, such as
Ta(OC.sub.2H.sub.5).sub.5 or Ta(N(CH.sub.3).sub.2).sub.5, with
reaction gases NH.sub.3 and O.sub.2 at a temperature of 300 to
600.degree. C. The absolute and relative flow rates of the, Ta
chemical vapor, NH.sub.3 and O.sub.2 gases into the LPCVD chamber
are controlled to produce the desired TaON film. The process of
forming TaON 16 is carried out under Ta source of 3 to 100 mg/min,
NH.sub.3) of 10 to 1000 sccm and O.sub.2 of 0.1 to 10000 sccm.
[0024] The Ta chemical vapor is typically prepared by injecting a
predetermined amount of the Ta compound, either directly or in
solution, into an evaporator through a mass flow controller (MFC),
and evaporating it at a temperature ranging from 150 to 200.degree.
C., a power ranging from 10 to 50 W and a pressure of from 0.15 to
2 torr (in a low pressure process) or from 50 to 300 torr (in a
high pressure process).
[0025] In order to increase the density of the gate insulating film
16 and reduce the level of impurities, the deposited TaON film is
annealed. This annealing process removes the carbon, carbon
compounds, water, and oxygen vacancies present in the thin film and
induces crystallization of the amorphous TaON film.
[0026] This annealing process preferably utilizes either a rapid
thermal process or an electric furnace to treat the wafer under an
atmosphere of N.sub.2O, O.sub.2 or N.sub.2 for a period of between
0.5 to 30 minutes and at a temperature ranging from 650 to
950.degree. C. This annealing process converts and/or removes the
carbon-based contaminants as volatile carbon compounds (such as CO,
CO.sub.2, CH.sub.4, C.sub.2H.sub.4) and induces crystallization of
the amorphous TaON film. In addition to crystallizing the TaON
film, this annealing process corrects other structural defects such
as micro cracks and pinholes in the film, thereby improving the
overall film homogeneity to provide an improved gate insulating
film 16.
[0027] In the alternative, the surface of the TaON gate insulating
film 16 may be nitrided with a plasma treatment in an atmosphere of
NH.sub.3 (or N.sub.2/H.sub.2), or oxynitrided in an atmosphere of
N.sub.2O (or a mixture of N.sub.2 and O.sub.2), at a temperature
ranging from 200 to 600.degree. C. This nitriding or oxynitriding
process may be performed either in-situ after the deposition of the
TaON film or in a subsequent ex-situ process. If the TaON film is
subjected to either the nitriding or oxynitriding process, the
separate high temperature annealing process (650-900.degree. C.)
described above may be skipped. The TaON gate insulating film 16
will, however, generally be crystallized during subsequent thermal
processing associated with the formation of the gate electrode.
[0028] As illustrated in FIG. 4, a doped polysilicon film 18 that
will serve as the gate electrode is then formed on the upper
portion of the gate insulating film 16. The gate electrode may also
include a silicide, such as a W-silicide or a Ti-silicide, that is
stacked on the doped polysilicon film 18 to lower the effective
gate electrode resistance.
[0029] Referring to FIG. 5, the doped polysilicon film 18, with or
without an additional silicide layer, the TaON gate insulating film
16 and the SiN or SiON film 14 are then patterned and etched using
conventional photolithography and etch processes to form the gate
structure. The remaining portions of the doped polysilicon film
18a, the TaON gate insulating film 16a and the SiN or SiON film 14a
comprise the completed gate structure.
[0030] The method for forming the gate insulating film for the
semiconductor device in accordance with the present invention
provide the following advantages:
[0031] Firstly, the dielectric constant (.epsilon.=20.about.25) of
the TaON film used for the gate insulating film is significantly
higher than the conventional SiO.sub.2 gate insulating film. This
improvement in dielectric constant allows the physical thickness of
the gate insulating film to be increased while simultaneously
reducing the electrical thickness when compared with a conventional
gate oxide film. Thus a gate insulating film according to the
present invention increases the resistance of a highly integrated
semiconductor device to degraded gate performance or gate failure,
thereby improving the life span of resulting products.
[0032] In addition, as compared with the conventional
Ta.sub.2O.sub.5 gate insulating film, the TaON gate insulating film
has a more stable structure, and thus exhibits reduced oxidation
reactivity with the silicon substrate and gate electrode. The TaON
gate insulating film according to the present invention is,
therefore, is resistant to externally-applied electric discharges
(ESD), provides a high insulation breakdown voltage, and exhibits
very low leakage currents.
[0033] Moreover, the oxidation resistance of the interface between
the silicon substrate 10 and the gate insulating film can be
increased by nitriding or oxynitriding the surface of the silicon
substrate 10 before depositing the TaON gate insulating film. As a
result, generation of a heterogeneous oxide film is further
suppressed, thereby providing improved interface properties.
[0034] In contrast to conventional nitriding or oxynitriding
processes utilizing rapid thermal treatment, the nitriding or
oxynitriding processes of the present invention are performed at
lower temperatures of between 200 and 600.degree. C., thereby
avoiding degradation of other electric properties. Furthermore, the
nitriding or oxynitriding processes of the present invention can be
performed in-situ in combination with the TaON deposition, thus
eliminating the need for special or separate apparatus and
providing additional simplification of the fabrication process.
[0035] As the present invention may be embodied in several forms
without departing from the spirit or essential characteristics
thereof, it should also be understood that the embodiments is not
limited to the specific details provided in the foregoing
description, unless otherwise specified, but rather should be
construed broadly within its spirit and scope as defined in the
appended claims. All changes and modifications to the specifically
described methods that fall within the meets and bounds of the
claims, or equivalences of such meets and bounds are, therefore,
intended to be embraced by the appended claims.
* * * * *