U.S. patent application number 09/741888 was filed with the patent office on 2001-06-28 for semiconductor memory circuit.
Invention is credited to Endo, Nobuyuki, Sekino, Yoshimasa, Yamada, Hitoshi.
Application Number | 20010005027 09/741888 |
Document ID | / |
Family ID | 18496900 |
Filed Date | 2001-06-28 |
United States Patent
Application |
20010005027 |
Kind Code |
A1 |
Endo, Nobuyuki ; et
al. |
June 28, 2001 |
Semiconductor memory circuit
Abstract
A memory circuit includes a plurality of word lines connected to
a plurality of memory cells, a plurality of row address decode
circuits having address input terminals, first wafer burn-in signal
terminal, and second wafer burn-in signal terminal. The row address
decode circuits activate all of the word lines when the first wafer
burn-in signal and the second wafer burn-in signal are in an enable
state. On the other hand, the row address decode circuits activate
a subset of the word lines when the second wafer burn-in signal is
in the enable state.
Inventors: |
Endo, Nobuyuki; (Tokyo,
JP) ; Sekino, Yoshimasa; (Tokyo, JP) ; Yamada,
Hitoshi; (Tokyo, JP) |
Correspondence
Address: |
JONES VOLENTINE, L.L.C.
SUITE 150
12200 SUNRISE VALLEY DRIVE
RESTON
VA
20191
US
|
Family ID: |
18496900 |
Appl. No.: |
09/741888 |
Filed: |
December 22, 2000 |
Current U.S.
Class: |
257/296 |
Current CPC
Class: |
G11C 29/12 20130101;
G11C 8/10 20130101; G11C 8/08 20130101 |
Class at
Publication: |
257/296 |
International
Class: |
H01L 027/108; H01L
029/76; H01L 029/94; H01L 031/119 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 27, 1999 |
JP |
370431/1999 |
Claims
What is claimed is:
1. A memory circuit comprising: a plurality of word lines connected
to a plurality of memory cells; and a plurality of row address
decode circuits which selectively activate said plurality of word
lines, respectively, and each having at least one address input
terminal, a first terminal which receives a first wafer burn-in
signal, and a second terminal which receives a second wafer burn-in
signal; wherein said row address decode circuits activate all of
said word lines when said first wafer burn-in signal and said
second wafer burn-in signal are in an enable state, and wherein
said row address decode circuits activate a subset of said word
lines when said second wafer burn-in signal is in the enable state
and said first wafer burn-in signal is in a disable state.
2. A memory circuit according to claim 1, wherein each of said row
address decode circuit includes: a pre-decode circuit which outputs
a pre-decode signal according to the first wafer burn-in signal,
the second wafer burn-in signal and an address signal received from
said at least one address input terminal; a decode circuit which
outputs a decode signal according to said pre-decode signal; and a
word driver circuit which activates at least one of said plurality
of word lines according to said decode signal.
3. A memory circuit comprising: a plurality of word lines connected
to a plurality of memory cells; a plurality of pre-decode circuits
which output a respective plurality of pre-decode signals according
to an address signal, a first wafer burn-in signal, and a second
wafer burn-in signal; a plurality of decode circuits which output a
respective plurality of decode signal according to said plurality
of pre-decode signals; and a plurality of word driver circuits
which selectively activate said respective plurality of word lines
according to said respective plurality of decode signals; wherein
said pre-decode circuits output all of the respective pre-decode
signals as a first logic level when said first wafer burn-in signal
and second wafer burn-in signal are in an enable state, and wherein
said pre-decode circuits output a subset of the respective
pre-decode signals as the first logic level when said second wafer
burn-in signal is in the enable state and said first wafer burn-in
signal is in a disable state.
4. A memory circuit comprising: a plurality of word lines connected
to a plurality of memory cells; a plurality of pre-decode circuits
which output a respective plurality of pre-decode signals according
to an address signal and a wafer burn-in signal; a plurality of
decode circuits which output a respective plurality of decode
signals according to said respective plurality of pre-decode
signals; a first group of word driver circuits which activates a
first subset of the plurality of word lines in response to a first
group of said respective plurality of decode signals and a
predetermined bit in said address signal; and a second group of
word driver circuits which activate a second subset of the
plurality of word lines in response to a second group of said
respective plurality of decode signals and an inverted signal of
said predetermined bit in said address signal.
5. A memory circuit according to claim 4, wherein said first group
of word driver circuits and said second group of word driver
circuits are alternatively arranged.
6. A memory circuit comprising: a plurality of word lines connected
to a plurality of memory cells; a plurality of pre-decode circuits
which output a respective plurality of pre-decode signals according
to an address signal; a first group of decode circuits which
outputs a first group of respective decode signals according to a
first group of said respective plurality of pre-decode signals and
a first wafer burn-in signal; a second group of decode circuits
which output a second group of respective decode signals according
to a second group of said respective plurality of pre-decode
signals and a second wafer burn-in signal; and a plurality of word
driver circuits which activate said plurality of word lines
according to said first and second groups of respective decode
signals; wherein said first group of decode circuits output the
first group of respective decode signals as a first logic level
when said first wafer burn-in signal is in an enable state, and
said second group of decode circuits output the second group of
respective decode signals as the first logic level when said second
wafer burn-in signal is in the enable state, and wherein each of
the plurality of word driver circuit are responsive to the first
logic level to activate a respective one of the plurality of word
lines.
7. A memory circuit according to claim 6 wherein said first group
of decode circuits and second group of decode circuits are
alternatively arranged.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor memory
circuit, and particularly to a row address decode circuit for a
semiconductor memory circuit.
[0003] 2. Description of the Related Art
[0004] FIG. 9 is a circuit diagram of a memory cell. The memory
cell has an NMOS transistor 1, a capacitor 2, a word line WLi, and
a bit line BLj. As the semiconductor memory circuit has many memory
cells, a plurality of word lines WLi(i=1,2,3 . . .) and bit lines
BLj are disposed in a matrix pattern. One of the word lines is
selected and raised to a predetermined potential during each "data
read" or "data write" operation.
[0005] To check the reliability of the semiconductor memory
circuit, a wafer burn-in test is performed. During the wafer
burn-in test, all of the word lines are raised to the predetermined
potential at the same time to shorten the time needed to carry out
the test.
[0006] FIG. 10 is a circuit diagram of a row address decode circuit
1000 which performs the wafer burn-in test, and FIG. 11 is an
operational waveform diagram of the same. This row address decode
circuit has a pre-decode circuit 10, a decode circuit 20, and a
word driver circuit 30.
[0007] The pre-decode circuit 10 has parallel inverters
11.sub.0.about.11.sub.n, NAND gates 12.sub.0.about.12.sub.n, and
NAND gates 13.sub.0.about.13.sub.n. Address signals
AX.sub.0.about.AX.sub.k, Inverted address signals
AX.sub.0b.about.AX.sub.kb, are inputted to the NAND gates
12.sub.0-12.sub.n. Wafer burn-in signal WBI is inputted to the
inverters 11.sub.0.about.11.sub.n. The output signals of the NAND
gates 12.sub.0-12.sub.n and the inverters 11.sub.0-11.sub.n are
respectively inputted to the NAND gates 13.sub.0-13. This
pre-decode circuit 10 outputs pre-decodes signal
PAX.sub.0.about.PAX.sub.n of (n+1) bits. Half of k+1 is n+1 in this
circuit.
[0008] The least significant address signal AX.sub.0 or AX.sub.0b,
which is the inverted signal of AX.sub.0, is inputted to one input
terminal of the NAND gate 12.sub.0, and second to least significant
address signal AX.sub.1 or AX.sub.1b, which is the inverted signal
of AX.sub.1, is inputted to another input terminal of NAND gate
12.sub.0. The third to least significant address signal AX.sub.2 or
AX.sub.2b, which is the inverted signal of AX.sub.2, is inputted to
one input terminal of the NAND gate 12.sub.1, and fourth to least
significant address signal AX.sub.3 or AX.sub.3b, which is the
inverted signal of AX.sub.3, is inputted to another input terminal
of NAND gate 12.sub.1. Input signals are applied to all other NAND
gates 12.sub.2-12.sub.n in the same manner as described above. The
NAND gates 120.about.12.sub.n output a logic "L" level only when
both input signals are a logic "H" level.
[0009] When the wafer burn in signal WBI is L level (ground
potential), which designates a disable state, the memory circuit
operates in a normal mode. Nodes NI.sub.0.about.NI.sub.n are an H
level (power supply potential). Therefore, the output signals of
NAND gates 13.sub.0.about.13.sub.n depend on the output signals of
NAND gates 12.sub.0.about.12.sub.n. NAND gates
13.sub.0.about.13.sub.n output a logic L level when the output
signal of NAND gates 12.sub.0.about.12.sub.n is a logic H level.
The NAND gates 13.sub.0.about.13.sub.n output a logic L level when
output signal of NAND gates 12.sub.0.about.12.sub.n is a logic H
level.
[0010] When the wafer burn in signal WBI is an H level, which
designates an enable state, the memory circuit operates in a
burn-in test mode. Nodes NI.sub.0.about.NI.sub.n are L level.
Therefore, all of the NAND gates 13.sub.0.about.13.sub.n output a
logic H level.
[0011] Decode circuit 20 has a P channel MOS transistor 21, an N
channel MOS transistors 22.sub.0.about.22.sub.n, and an inverter
23. Pre-decode signals PAX.sub.0.about.PAX.sub.n and a reset signal
PREb are inputted to the decode circuit 20. The reset signal PREb
become an L level when the decode circuit 20 is reset, and the
reset signal PREb become an H level when the decode circuit 20 is
in an enable state. NMOS transistors 22.sub.0.about.22.sub.n are
connected in series. The source of 22n is connected to the ground
level. The drain of the NMOS transistor 22.sub.0 is connected to
the node ND.sub.0. Pre-decode signals PAX.sub.0.about.PAX.sub.n are
inputted to the gates of transistor 22.sub.0.about.22.sub.n,
respectively. The source of PMOS transistor 21 is connected to the
power supply potential, and the drain is connected to the node
ND.sub.0. The reset signal PREb is inputted to the gate of PMOS
transistor 21. The node ND.sub.0 is connected to the input terminal
of the inverter 23. The inverter 23 outputs a decode signal
D.sub.0.
[0012] When the decode circuit is reset, reset signal PREb and all
of the address signals AX.sub.0.about.AX.sub.n become an L level.
Therefore, pre-decode signals PAX.sub. .about.PAX.sub.n become an L
level. PMOS transistor 21 is in an on state, and the NMOS
transistors 22.sub.0.about.22.sub.n are in off state 20 in this
case. The node ND.sub.0 becomes an H level, and the decode signal
D.sub.0 becomes an L level.
[0013] When the decode line is activated, reset signal PREb becomes
an H level. The PMOS transistor 21 is in an off state in this case.
Address signals AX.sub.0.about.AX.sub.k are inputted to the
pre-decode circuit 10. Pre-decode circuit 10 outputs pre-decode
signals PAX.sub.0.about.PAX.sub.n. If all of the pre-decode signals
PAX.sub.0.about.PAX.sub.n are an H level, all of the NMOS
transistor 22.sub.0.about.22.sub.n are in an on state. Therefore,
the node ND.sub.0 becomes an L level, and the decode signal D.sub.0
becomes an H level. If one of the pre-decode signals
PAX.sub.0.about.PAX.sub.n is an L level, one of the NMOS transistor
22.sub.0.about.22.sub.n is in an off state. Therefore, the node
ND.sub.0 keeps an H level.
[0014] When the wafer burn in test is performed, all of the
pre-decode signals PAX.sub.0.about.PAX.sub.n become an H level.
Therefore, the decode signal D.sub.0 is an H level during the wafer
burn in test.
[0015] The word driver circuit 30 has an inverter 31, level shift
circuit 32, PMOS transistor 33, and NMOS transistor 34. The level
shift circuit changes the amplitude of the input signal. The input
signal has an amplitude between the power supply potential and the
ground potential. However, to activate a word line, a slightly high
level than power supply potential is needed. This level is called
the word line activate potential. Therefore, the level shift
circuit is needed. The output terminal of the level shift circuit
is connected to the gates of PMOS transistor 33 and NMOS transistor
34. The source of PMOS transistor 33 is connected to the word line
activate potential. The source of the NMOS transistor is connected
to the ground potential. The drains of transistors 33 and 34 are
connected to a word line WLi.
[0016] When the decode signal D.sub.0 is an L level, the word
driver circuit makes the word line WLi the ground potential. When
the decode signal D.sub.0 is an H level, the word driver circuit
makes the word line WLi word line an activate potential.
[0017] FIG. 10 shows one row address decode circuit. A memory
circuit has a plurality of row address decode circuits. For
example, address signals inputted to NAND gate 12.sub.0 have four
patterns. The first pattern is that the inputted signals are
AX.sub.0 and AX.sub.1. The second pattern is that the inputted
signals are AX.sub.0b and AX.sub.1. The third pattern is that the
inputted signals are AX.sub.0 and AX.sub.1b. The fourth pattern is
that the inputted signals are AX.sub.0b and AX.sub.1b. The same
relationship applies to other NAND gates 12.sub.1-12.sub.n.
Therefore, there are 4.sup.(n+1) units of row address decode
circuits and word lines in a memory circuit.
[0018] In the prior art, only the selected word line is activated
during the normal mode, and all of the word lines are activated
during the wafer burn-in test mode.
[0019] While the wafer burn in test is performed, there is not any
electrical potential difference between the word lines. However, in
the normal operation, there are electrical potential differences
between the word lines. Therefore, the wafer burn-in test in the
prior art can not test for the stress between word lines.
SUMMARY OF THE INVENTION
[0020] An object of the present invention is to provide a
semiconductor memory device which allows stress acceleration
testing between word lines.
[0021] A memory circuit includes a plurality of word lines
connected to a plurality of memory cells and a plurality of row
address decode circuits which selectively activates the plurality
of word lines, respectively, and each having at least one address
input terminal, a first terminal which receive a first wafer
burn-in signal, and a terminal which receive a second wafer burn-in
signal.
[0022] wherein the row address decode circuits activate all of the
word lines when the first wafer burn-in signal and the second wafer
burn-in signal are in an enable state, wherein the row address
decode circuits activate a subset of the word lines when the second
wafer burn-in signal is enable state and the first wafer burn-in
signal is in a disable state.
BRIEF DESCRIPTUON OF THE DRAWINGS
[0023] While the specification concludes with claims particularly
pointing out and distinctly claiming the subject matter which is
regarded as the invention, it is believed that the invention, the
objects and features of the invention and further objects, features
and advantages thereof will be better understood from the following
description taken in connection with the accompanying drawings in
which:
[0024] FIG. 1 is a circuit diagram of a row address decode circuit
of a first embodiment of the present invention.
[0025] FIG. 2 is a schematic diagram of a memory circuit of the
invention.
[0026] FIG. 3 shows activated word lines of the first
embodiment.
[0027] FIGS. 4 and 5 are a circuit diagrams of a row address decode
circuit of the second embodiment of the present invention.
[0028] FIG. 6 shows a disposition of a first row address decode
circuit and a second row address decode circuit of the second
embodiment.
[0029] FIG. 7 is a circuit diagram of a row address decode circuit
of a third embodiment of the present invention.
[0030] FIG. 8 is a signal diagram of the row address decode circuit
of the third embodiment.
[0031] FIG. 9 is a circuit diagram of a memory cell.
[0032] FIG. 10 is a circuit diagram of a row address decode
circuit.
[0033] FIG. 11 is a signal diagram of a row address decode
circuit.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0034] The memory circuit of this embodiment has a plurality of
word lines and a plurality of bit lines. Word lines Wli (i=1, 2, 3
. . . ) and bit lines BLj are disposed like a matrix. A plurality
of row address decode circuits 100 are connected to each word line
as shown in FIG. 2.
[0035] FIG. 1 is a circuit diagram that shows a row address decode
circuit 100 of a first embodiment of the present invention. This
row address decode circuit has a pre-decode circuit 40, a decode
circuit 20, and a word driver circuit 30. FIG. 1 shows only one row
address decode circuit. A memory circuit has a plurality of row
address decode circuits. This row address decode circuit 100 has
two modes of the wafer burn-in test.
[0036] The pre-decode circuit 40 has parallel inverters
41.sub.0.about.41.sub.n, NAND gates 42.sub.0.about.42.sub.n, and
NAND gates 43.sub.0.about.43.sub.n. Address signals
AX.sub.0.about.AX.sub.k and inverted address signals
AX.sub.0b.about.AX.sub.kb, are inputted to the NAND gates
42.sub.0.about.42.sub.n. In this embodiment, a first wafer burn-in
signal WBI0 is inputted to the inverter 41.sub.0, and a second
wafer burn-in signal WBI1 is inputted to the inverters
41.sub.0.about.41.sub.n. The output signals of the NAND gates
42.sub.0.about.42.sub.n and the inverters 41.sub.0.about.41.sub.n
are inputted to the NAND gates 43.sub.0.about.43.sub.n
respectively. This pre-decode circuit 40 outputs pre-decode signal
PAX.sub.0.about.PAX.sub.n of (n+1) bits. Half of k+1 is n+1 in this
circuit.
[0037] The least significant address signal AX.sub.0 or AX.sub.0b,
which is the inverted signal of AX.sub.0, is inputted to one input
terminal of the NAND gate 42.sub.0, and second to least significant
address signal AX.sub.1 or AX.sub.1b, which is the inverted signal
of AX.sub.1, is inputted to another input terminal of NAND gate
42.sub.0. The third to least significant address signal AX.sub.2 or
AX.sub.2b, which is the inverted signal of AX.sub.2, is inputted to
one input terminal of the NAND gate 42.sub.1, and third to least
significant address signal AX.sub.3 or AX.sub.3b, which is the
inverted signal of AX.sub.3, is inputted to another input terminal
of NAND gate 42.sub.1. The relationship of input signals to all
other NAND gates 42.sub.2.about.42.sub.n are the same as described
above. NAND gates 42.sub.0.about.42.sub.n output a logic L level
only when both of the input signals are a logic H level.
[0038] Both wafer burn-in signals are set to the L level during
normal mode. While both wafer burn-in signals WBI0 and WBI1 are the
L level (ground potential), nodes NI.sub.0.about.NI.sub.n are H
level (power supply potential). Therefore, the output signals of
NAND gates 43.sub.0.about.43.sub.n depend on the output signals of
NAND gates 42.sub.0.about.42.sub.n. NAND gates
43.sub.0.about.43.sub.n output the logic L level when output
signals of NAND gates 42.sub.0.about.42.sub.n are the logic H
level. NAND gates 43.sub.0.about.43.sub.n output the logic L level
when output signals of NAND gates 42.sub.0.about.42.sub.n are the
logic H level. A pre-decode circuit 40 operates according to
address signals AX.sub.0.about.AX.sub.k. Therefore, only the
selected word line is raised to a predetermined potential (word
line activate potential) in the normal mode.
[0039] Both wafer burn-in signals WBI0 and WBI1 are set to the H
level during first burn-in test mode. While the Wafer burn-in
signals WBI0 and WBI1 are the H level, nodes NI0.about.NIn are the
L level. Therefore, all of the NAND gates 43.sub.0.about.43.sub.n
output a logic H level. All word lines are activated and raised to
a predetermined potential in the first burn-in test mode.
[0040] The first burn-in signal WBI0 is set to the L level, and the
second burn-in signal is set to the H level during the second
burn-in test mode. While the wafer burn-in signal WBI1 is the H
level, nodes NI1.about.NIn are the L level. Therefore, the NAND
gates 43.sub.1.about.43.sub.n output a logic H level. The output
signals of the NAND gates 43.sub.0 depend on the output signals of
NAND gates 42.sub.0.
[0041] There are four patterns of signal combination inputted to
the NAND gate 42.sub.0. The first pattern is AX.sub.0 and AX.sub.1,
the second pattern is AX.sub.0b and AX.sub.1, the third pattern is
AX.sub.0 and AX.sub.1b, and the fourth pattern is AX.sub.0b and
AX.sub.1b. There is at least one combination that makes the NAND
gate 42.sub.0 output a signal of an L level. Therefore, one fourth
of pre-decode circuits 40 output pre-decode signal PAX.sub.0 of the
H level. One fourth of the word lines are raised to a predetermined
level.
[0042] Decode circuit 20 has a P channel MOS transistor 21, N
channel MOS transistors 22.sub.0.about.22.sub.n, and an inverter
23. Pre-decode signals PAX.sub.0.about.PAX.sub.n and a reset signal
PREb are inputted to the decode circuit 20. The reset signal PREb
becomes the L level when the decode circuit 20 is reset, and the
reset signal PREb becomes the H level when the decode circuit 20 is
in the enable state. NMOS transistors 22.sub.0.about.22.sub.n are
connected in series. The source of is connected to the ground
potential. The drain of the NMOS transistor 22.sub.0 is connected
to the node NDO. Pre-decode signals PAX.sub.0.about.PAX.sub.n are
inputted to the gates of transistor 22.sub.0.about.22.sub.n,
respectively. The source of PMOS transistor 21 is connected to the
power supply potential, and the drain is connected to the node ND0.
The reset signal PREb is inputted to the gate of PMOS transistor
21. The node ND0 is connected to the input terminal of the inverter
23. The inverter 23 outputs a decode signal D0.
[0043] When the decode circuit is reset, reset signal PREb and all
of the address signals AX0-Axn become the L level. Therefore,
pre-decode signals PAX.sub.0.about.PAX.sub.n become the L level.
PMOS transistor 21 is in an on state, and the NMOS transistors
220-22n are in an off state in this case. The node ND0 becomes the
H level, and the decode signal D0 is L level, which means disable
state.
[0044] When the decode circuit is activated in the normal mode,
reset signal PREb becomes the H level. The PMOS transistor 21 is in
an off state in this case. Address signals AX.sub.0.about.AX.sub.k
are inputted to the pre-decode circuit 40. Pre-decode circuit 40
outputs pre-decode signals PAX.sub.0.about.PAX.sub.n. If all of the
pre-decode signals PAX.sub.0.about.PAX.sub.n are the H level, all
of the NMOS transistor 22.sub.0.about.22.sub.n are in the on state.
Therefore, the node ND0 becomes the L level, and the decode signal
D0 becomes the H level, which means enable state. If one of the
pre-decode signals PAX.sub.0.about.PAX.sub.n is the L level, one of
the NMOS transistor 22.sub.0.about.22.sub.n is in the off state.
Therefore, the node ND0 keeps the H level.
[0045] When the first mode of wafer burn-in test is performed, all
of the pre-decode signals PAX.sub.0.about.PAX.sub.n become the H
level. Therefore, the decode signal D.sub.0 is the H level during
the first wafer burn in test.
[0046] When the second mode of wafer burn-in test is performed, all
of the pre-decode signals PAX.sub.1.about.PAX.sub.n become the H
level. Also, one-fourth of the pre-decode signals PAX.sub.0 become
the H level. As described above, there is at least one combination
that makes the NAND gate 42.sub.0 output a signal of the L level.
Therefore, one fourth of pre-decode circuits 40 output pre-decode
signal PAX.sub.0 of the H level. One-fourth of the word lines are
raised to a predetermined level.
[0047] Therefore, one-forth of the decode signals D0 are the H
level during the second wafer burn-in test.
[0048] The word driver circuit 30 has an inverter 31, a level shift
circuit 32, a PMOS transistor 33, and a NMOS transistor 34. The
level shift circuit changes the amplitude of the input signal. The
input signal has an amplitude between the power supply potential
and the ground potential. However, to activate a word line, a
slightly higher level than the power supply potential is needed.
This is called the word line activate potential. Therefore, the
level shift circuit is needed. The output terminal of the level
shift circuit is connected to the gates of PMOS transistor 33 and
NMOS transistor 34. The source of PMOS transistor 33 is connected
to the word line activate potential. The source of the NMOS
transistor is connected to the ground potential. The drains of
transistors 33 and 34 are connected to a word line WL1.
[0049] When the decode signal D.sub.0 is the L level, the word
driver circuit 30 makes the word line WLi the ground potential.
When the decode signal D.sub.0 is the H level, word driver circuit
makes the word line WLi word line the activate potential.
[0050] As described above, address signals inputted to NAND gate
42.sub.0 have four patterns. The same relationship applies to other
NAND gates 42.sub.1-42.sub.n. Therefore, there are 4.sup.(n+1)
units of row address decode circuits and word lines in a memory
circuit.
[0051] In this embodiment, there are two wafer burn-in test modes.
One-fourth of the word lines are raised to a predetermined level
during the second burn in test mode. FIG. 3 schematically shows
activated word lines in the second wafer burn-in test mode.
[0052] Therefore, the test can be performed in a state, which there
are electrical potential differences between word lines, in
addition to the prior wafer burn-in test. Also, there is no need to
add another device to achieve this embodiment.
[0053] FIGS. 4 and 5 are circuit diagrams of row address decode
circuits 400 and 500 for performing wafer burn-in test in the
second embodiment. These row address decode circuits have a
pre-decode circuit 50, a decode circuit 60, and a word driver 70.
The predetermined bit AX.sub.m of the address signals is inputted
to the first row address decode circuit 400, as shown in FIG. 4.
The inverted signal AX.sub.mb of the predetermined bit is its
inputted to second row address circuit 500. These row address
decode circuits are the same except for the address signal that is
inputted to the word driver circuit 70.
[0054] The row address decode circuit is described below with
reference to FIG. 4.
[0055] The pre-decode circuit 50 has parallel inverters
51.sub.0.about.51.sub.n-1, NAND gates 52.sub.0.about.52.sub.n-1,
and NAND gates 53.sub.0.about.53.sub.n-1. Address signals
AX.sub.0.about.AX.sub.k and inverted address signals
AX.sub.0b.about.AX.sub.kb, are inputted to the NAND gates
52.sub.0.about.52.sub.n-1. However, in this embodiment, a
predetermined bit of the address signal AX.sub.m and AX.sub.mb are
not inputted to the NAND gates 52.sub.0.about.52.sub.n-1.
[0056] Wafer burn-in signal WBI is inputted to the inverters
51.sub.0.about.51.sub.n-1. The output signals of the NAND gates
52.sub.0.about.52.sub.n-1 and the inverters
51.sub.0.about.51.sub.n-1 are inputted to the NAND gates
53.sub.0.about.53.sub.n-1, respectively. This pre-decode circuit 50
outputs the pre-decode signal PAX.sub.0.about.PAX.sub.n-1 of n
bits. Half of k is n in this circuit.
[0057] The least significant address signal AX.sub.0 or AX.sub.0b,
which is the inverted signal of AX.sub.0, is inputted to one input
terminal of the NAND gate 52.sub.0, and the second to least
significant address signal AX.sub.1 or AX.sub.1b, which is the
inverted signal of AX.sub.1, is inputted to another input terminal
of NAND gate 52.sub.0. The third to least significant address
signal AX.sub.2 or AX.sub.2b, which is the inverted signal of
AX.sub.2, is inputted to one input terminal of the NAND gate
52.sub.1, and the fourth to least significant address signal
AX.sub.3 or AX.sub.3b, which is the inverted signal of AX.sub.3, is
inputted to another input terminal of NAND gate 52.sub.1. The
relationship of input signals to all other NAND gates
52.sub.2-52.sub.n-1 are the same as described above except for
skipping the address signal AX.sub.m. NAND gates
52.sub.0-52.sub.n-1 output a logic L level only when both of input
signals are a logic H level.
[0058] When the wafer burn-in signal WBI is the L level (ground
potential) which means disable state, nodes
NI.sub.0.about.NI.sub.n-1 are the H level (power supply potential).
Therefore, the output signals of NAND gates 53.sub.0-53.sub.n-1
depend on the output signals of NAND gates 52.sub.0-52.sub.n-1.
NAND gates 53.sub.0-53.sub.n-1 output a logic L level when output
signals of NAND gates 52.sub.0-52.sub.n-1 are a logic H level. NAND
gates 53.sub.0-53.sub.n-1 output a logic H level when output
signals of NAND gates 52.sub.0-52.sub.n-1 are a logic L level.
[0059] When the wafer burn in signal WBI is the H level, which
means enable state, nodes NI.sub.0.about.NI.sub.n-1 are the L
level. Therefore, NAND gates 53.sub.0-53.sub.n-1 output a logic H
level.
[0060] Decode circuit 60 has a P channel MOS transistor 61, N
channel MOS transistors 62.sub.0-62.sub.n-1, and an inverter 63.
The operation of the decode circuit 60 is the same as the operation
of the first embodiment.
[0061] The word driver circuit 70 has an inverter 71, a first level
shift circuit 72, a PMOS transistor 73, an NMOS transistor 74, and
a second level shift circuit 75. The level shift circuits 72 and 75
change the amplitude of inputted signal. The input signal has
amplitude between the power supply potential and the ground
potential. However, to activate a word line, a slightly high
potential than the power supply potential is needed. Therefore, the
level shift circuits are needed. The output terminal of the first
level shift circuit is connected to the gates of PMOS transistor 73
and NMOS transistor 74. The output terminal of the second level
shift circuit 75 is connected to the source of PMOS transistor 73.
The source of the NMOS transistor 74 is connected to the ground
potential. The drains of transistors 73 and 74 are connected to a
word line WLi. The address signal AX.sub.m (AX.sub.mb in FIG. 5) is
inputted to the level shift circuit 75 in this embodiment.
[0062] When both the decode signal D.sub.0 and the address signal
AX.sub.m are the H level, the word driver circuit 70 raises a
potential of the word line WLi. When the address signal AX.sub.m is
the L level, the word line WLi is not so raised, even if the decode
signal the D.sub.0 is H level.
[0063] On the other hand, the row address decode circuit as shown
in FIG. 5 raises the potential of the word line WLi to the word
line activate potential, when both the decode signal D.sub.0 and
the address signal AX.sub.mb are the H level. When the address
signal AX.sub.mb is the L level, the word line WLi is not raised,
even if the decode signal D.sub.0 is H the level.
[0064] The first row address decode circuit and the second row
address decode circuit are alternatively arranged as shown in FIG.
6.
[0065] The selected word line is activated during the normal mode.
While the wafer burn-in test is performed, half of the word lines
are activated because the row address decode circuit 400 and 500
are alternatively arranged. The time needed to test for stress
between word lines becomes shorter than that of the first
embodiment.
[0066] FIG. 7 is a schematic diagram that shows a row address
decode circuit 700 of a third embodiment of the present invention.
This row address decode circuit has a pre-decode circuit 80, a
decode circuit 90, and a word driver 30. FIG. 7 shows only one row
address decode circuit. A memory circuit has a plurality of first
and second row address decode circuits. This row address decode
circuit has two modes of wafer burn-in test. A first wafer burn-in
signal DWB0 is inputted to the first row address decode circuits. A
second wafer burn-in signal is inputted to second the row address
circuits. These row it address decode circuits are the same except
for the wafer burn-in signals that are inputted to the decode
circuit 90.
[0067] The pre-decode circuit 80 has NAND gates 81.sub.0-81.sub.n,
and inverters 82.sub.0-82.sub.n. Address signals
AX.sub.0.about.AX.sub.k, and inverted address signals
AX.sub.0b.about.AX.sub.kb, are inputted to the NAND gates
81.sub.0-81.sub.n. In this embodiment, this pre-decode circuit 80
outputs pre-decode signal PAX.sub.0.about.PAX.sub.n of (n+1) bits.
Half of k+1 is n+1 in this circuit.
[0068] The least significant address signal AX.sub.0 or AX.sub.0b,
which is the inverted signal of AX.sub.0, is inputted to one input
terminal of the NAND gate 81.sub.0, and the second to least
significant address signal AX.sub.1 or AX.sub.1b, which is the
inverted signal of AX.sub.1, is inputted to another input terminal
of NAND gate 81.sub.0. The third to least significant address
signal AX.sub.2 or AX.sub.2b, which is the inverted signal of
AX.sub.2, is inputted to one input terminal of the NAND gate
81.sub.1, and the third to least significant address signal
AX.sub.3 or AX.sub.3b, which is the inverted signal of AX.sub.3, is
inputted to another input terminal of NAND gate 81.sub.1. The
relationship of input signals to all other NAND gates
81.sub.2.about.81.sub.n are the same as described above. NAND gates
81.sub.0.about.81.sub.n output a logic L level only when both of
input signals are a logic H level.
[0069] Decode circuit 90 has a P channel MOS transistor 91, N
channel MOS transistors 92.sub.0.about.92.sub.n, and an inverter
93. Pre-decode signals PAX.sub.0.about.PAX.sub.n and a reset signal
PREb are inputted to the decode circuit 90. The reset signal PREb
becomes the L level when the decode circuit 90 is reset, and the
reset signal PREb becomes the H level when the decode circuit 90 is
in an enable state. NMOS transistors 92.sub.0.about.92.sub.n are
connected in series. The source of 92.sub.n is connected to the
ground level. The drain of the NMOS transistor 92.sub.0 is
connected to the node ND.sub.0. Pre-decode signals
PAX.sub.0.about.PAX.sub.n are inputted to the gates of transistor
92.sub.0.about.92.sub.n, respectively. The source of the PMOS
transistor 91 is connected to the power supply potential, and the
drain is connected to the node ND.sub.0. The reset signal PREb is
inputted to the gate of the PMOS transistor 91. The node ND.sub.0
is connected to the input terminal of the inverter 93. The inverter
93 outputs a decode signal D.sub.0.
[0070] The decode circuit 90 also has an inverter 94 and P channel
MOS transistor 95. The input terminal of the inverter 94 is
connected to the output terminal of the inverter 93. The output
terminal of the inverter 94 is connected to the node ND.sub.0. The
drain of P channel MOS transistor 95 is connected to the node
ND.sub.0. The gate of P channel MOS transistor 95 is connected to
the output terminal of the inverter 93. Either first wafer burn-in
signal DWBI0 or second wafer burn-in signal DWBI1 is inputted to
the source of P channel MOS transistor 95. These wafer burn-in
signals are set to the H level during the normal mode, and set to
the L level during the wafer burn-in test. First wafer burn-in
signal DWBI0 and second wafer burn-in signal WBI1 are independent
signals. DWBI0 is inputted to the decode circuit 90 of the first
row address decode circuits. Second wafer burn-in signal DWBI1 is
inputted to the second decode circuits 90. The ability to make an
electric current of the transistor 95 and the inverter 94 is less
than that of transistors 92.sub.0.about.92.sub.n.
[0071] The word driver circuit 30 is the same as that of first
embodiment.
[0072] The operation of the row address decode circuit 700 is
described below.
[0073] The pre-decode circuit 80 outputs pre-decode signals
PAX0.about.PAXn according to the address signal
AX.sub.0.about.AX.sub.n during the normal mode and the wafer
burn-in mode. Wafer burn-in signals DWBI0 and DWBI1 are to the set
H level during the normal operation. Therefore, only the selected
word line is raised to the word line activate potential during the
normal mode.
[0074] When the wafer burn-in signal DWBI0 (or DEBI1) is set to the
L level in the test mode, the potential of node ND.sub.0 starts to
drop with no relationship to the pre-decode signals
PAX.sub.0.about.PAX.sub.n. Therefore, the decode signal D.sub.0
starts to rise. When the potential of the decode signal exceeds the
threshold voltage of the P channel MOS transistor 95, the P channel
MOS transistor 95 becomes the off state. However, the potential of
node ND.sub.0 is keeps the L level due to inverter 93 and inverter
94. The decode signal keeps the H level, and the word line WL1 is
raised to the word line activate potential. For example, when the
first wafer burn-in signal DWBI0 is set to the L level, all of the
first row address decode circuits raise the word lines to the word
line activate potential. When the second wafer burn-in signal DWBI0
is set to the L level, all of the second row address decode circuit
raise the word lines to the word line activate potential. FIG. 8
schematically shows the operation signals described above.
[0075] The row address decode circuits, having a first wafer burn
in signal input, and the row address decode circuits, having a
second wafer burn-in signal input, are alternatively arranged.
Therefore, the test can be performed in the state where there are
electrical potential differences between word lines. Also, the
wafer burn-in test of the prior art can be performed by controlling
the timings of the wafer burn-in signals.
* * * * *