Arrangement for reducing power dissipation in a line driver

Barkaro, Stefan

Patent Application Summary

U.S. patent application number 09/727694 was filed with the patent office on 2001-06-21 for arrangement for reducing power dissipation in a line driver. Invention is credited to Barkaro, Stefan.

Application Number20010004387 09/727694
Document ID /
Family ID20418180
Filed Date2001-06-21

United States Patent Application 20010004387
Kind Code A1
Barkaro, Stefan June 21, 2001

Arrangement for reducing power dissipation in a line driver

Abstract

To reduce power dissipation in a line driver (2) connected to a transmission line (3) for transmitting multitone signals in the form of successive symbols separated by cyclic prefixes, generated by a digital signal processor (1), a controllable voltage supply (5) is connected with its output terminal to a supply voltage terminal (6) of the line driver (2) to supply a controllable supply voltage thereto, and with its control input terminal to a control output terminal of the digital signal processor (1). In response to an expected peak-to-peak value of the next symbol to be transmitted, the digital signal processor (1) controls the controllable voltage supply (5) during each cyclic prefix to set the supply voltage to the line driver (2).


Inventors: Barkaro, Stefan; (Solna, SE)
Correspondence Address:
    NIXON & VANDERHYE P.C.
    1100 North Glebe Rd.
    8th Floor
    Arlington
    VA
    22201-4714
    US
Family ID: 20418180
Appl. No.: 09/727694
Filed: December 4, 2000

Current U.S. Class: 375/257
Current CPC Class: H03F 2200/504 20130101; H04L 27/2607 20130101; H04L 27/2626 20130101; H04L 27/2614 20130101; H03F 1/0244 20130101
Class at Publication: 375/257
International Class: H04B 003/00; H04L 025/00

Foreign Application Data

Date Code Application Number
Dec 17, 1999 SE 9904642-7

Claims



1. An arrangement for reducing power dissipation in a line driver (2) connected to a transmission line (3) for transmitting multitone signals in the form of successive symbols (S1, S2) separated by cyclic prefixes (CP1, CP2), generated by a digital signal processor (1), characterized in that it comprises a controllable voltage supply (5) having an output terminal and a control input terminal, the output terminal of the controllable voltage supply (5) being connected to a supply voltage terminal (6) of the line driver (2) to supply a controllable supply voltage thereto, and the control input terminal of the controllable voltage supply (5) being connected to a control output terminal of the digital signal processor (1), the digital signal processor (1) being adapted to control the controllable voltage supply (5) during each cyclic prefix (CP1, CP2) to control the supply voltage to the line driver (2) in response to an expected peak-to-peak value of the next symbol to be transmitted.

2. The arrangement according to claim 1, characterized in that the controllable voltage supply (5) is connected to the digital signal processor (1) via a control bus (4).

3. The arrangement according to claim 1 or 2, characterized in that the controllable voltage supply comprises a switch (5) which is adapted to apply different supply voltages (SV1, SV2 . . . SVn) to the line driver (2) in response to different expected peak-to-peak values of the symbols to be transmitted.

4. The arrangement according to claim 1 or 2, characterized in that the controllable voltage supply comprises a DC/DC converter controlled by the digital signal processor (1).
Description



TECHNICAL FIELD

[0001] The invention relates generally to line drivers, and more specifically to an arrangement for reducing power dissipation in line drivers connected to transmission lines in multitone systems, such as e.g. ADSL (Asymmetric Digital Subscriber Line) systems.

BACKGROUND OF THE INVENTION

[0002] In a multitone system, such as an ADSL-system, data information is randomly coded into the phase and amplitude of a plurality of sine tones that are transmitted by line drivers on transmission lines in bursts with a so-called symbol rate or length, which in the ADSL case is 246.3 .mu.s.

[0003] To enable Fourier transformations to be made on each symbol, a so-called cyclic prefix is inserted between the symbols. The cyclic prefix does not contain any valid data but ensures that the multitone signal appears continuous for the Fourier transformation.

[0004] In the ADSL case, each cyclic prefix has a length of 32 samples or about 15 .mu.s.

[0005] Since the phase and amplitude of each individual tone can be seen as random and the total signal consists of a sum of many tones, there will be a great difference between successive symbols in the peak-to-peak voltage of the total signal that is to be transmitted.

[0006] In view hereof, in normal ADSL systems, the supply voltage of the line drivers that are connected to the transmission line for transmitting such multitone signals must be selected such that the theoretical maximum peak can be transmitted without being clipped.

[0007] This causes the supply voltage of the line driver to be far too high for the majority of the symbols that are transmitted.

[0008] Consequently, the power dissipation in the line driver will be higher than necessary for most of the symbols.

SUMMARY OF THE INVENTION

[0009] The object of the invention is to bring about an arrangement for reducing the power dissipation in such line drivers.

[0010] This is attained essentially in that the supply voltage to the line driver is controlled from symbol to symbol during the cyclic prefixes in response to a known expected peak-to-peak value of the next symbol to be transmitted.

[0011] By adapting the supply voltage to expected peak-to-peak values, the power dissipation will be reduced in the line driver.

BRIEF DESCRIPTION OF THE DRAWING

[0012] The invention will be described more in detail below with reference to the appended drawing, on which FIG. 1 schematically illustrates two successive symbols to be transmitted in an ADSL system, and FIG. 2 is a schematic block diagram of one end of an ADSL connection with an embodiment of an arrangement according to the invention.

DESCRIPTION OF THE INVENTION

[0013] FIG. 1 schematically illustrates two successive symbols S1 and S2 to be transmitted in an ADSL system.

[0014] In a manner known per se, each symbol S1 and S2, is preceded by a so-called cyclic prefix CP1 and CP2, respectively.

[0015] In ADSL systems, the symbol length is 246.3 .mu.s, while the length of the cyclic prefix is 32 samples or about 15 .mu.s as already mentioned.

[0016] In FIG. 1, the peak-to-peak value of the symbol S1 is U1, while the peak-to-peak value of the symbol S2 equals U2, which in FIG. 1 is supposed to be a lower value than U1.

[0017] Today, the symbols S1 and S2 illustrated in FIG. 1 are transmitted by a line driver having a constant supply voltage even if they actually do not require the same supply voltage in order to be transmitted without being clipped.

[0018] Thus, unnecessary power is consumed today in such line drivers.

[0019] In FIG. 2, an arrangement according to the invention for reducing the power dissipation in a line driver is schematically illustrated.

[0020] In FIG. 2, a digital signal processor 1 is connected with its digital input/output terminals to corresponding output/input terminals of an analog front end or line driver 2 connected to a transmission line 3 for transmitting and receiving data information in the form of symbols as illustrated in FIG. 1.

[0021] In a manner known per se, the line driver 2 comprises a digital-to-analog converter (not shown) for converting digital signals from the digital signal processor 1 into analog signals to be transmitted as symbols in accordance with FIG. 1, and an analog-to-digital converter (not shown) for converting analog symbols received into digital signals to the digital signal processor 1.

[0022] Also in a manner known per se, the digital signal processor 1 knows the peak value of the tones to be transmitted in each symbol.

[0023] Thus, the digital signal processor 1 has knowledge of the peak value U1 in the symbol S1 in FIG. 1 before it is transmitted to the line driver 2 as well as of the peak value U2 in the symbol S2 in FIG. 1.

[0024] With this knowledge, the digital signal processor 1 can select the most appropriate supply voltage to the driver 2 for each symbol.

[0025] An embodiment of an arrangement for enabling such a supply voltage selection is illustrated in FIG. 2.

[0026] In the embodiment in FIG. 2, the digital signal processor 1 is connected via a control bus 4 to a switch 5 which is adapted to apply different supply voltages SV1, SV2 . . . SVn to a supply voltage input terminal 6 of the driver 2 in response to different control signals from the digital signal processor 1 on the control bus 4.

[0027] It should be pointed out in this connection that the different supply voltages do not have to be fixed and be applied by means of a switch but can be supplied e.g. by a controllable DC/DC converter (not shown).

[0028] Anyhow, in accordance with the invention, the selection of the appropriate supply voltage to the driver 2 takes place during each cyclic prefix CP1, CP2, i.e. at times when no relevant information is transmitted.

[0029] Thus, during each cyclic prefix, an optimum supply voltage for the driver 2 for the next symbol to be transmitted can be selected without causing any disturbances.

[0030] By optimizing the supply voltage for each symbol, the total power dissipation of the driver 2 can be considerably reduced.

* * * * *


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