U.S. patent application number 09/740269 was filed with the patent office on 2001-06-21 for secured master-slave d type flip-flop circuit.
This patent application is currently assigned to STMicroelectronics S.A.. Invention is credited to Pomet, Alain.
Application Number | 20010004220 09/740269 |
Document ID | / |
Family ID | 9553574 |
Filed Date | 2001-06-21 |
United States Patent
Application |
20010004220 |
Kind Code |
A1 |
Pomet, Alain |
June 21, 2001 |
Secured master-slave D type flip-flop circuit
Abstract
A master-slave D type flip-flop circuit includes a power
consumption circuit including a reference stage in parallel with a
master and a slave stage of the flip-flop circuit. This structure
advantageously provides a switching of the flip-flop circuit on
each of the leading and trailing edges of the clock signal for the
sequencing of the flip-flop circuit.
Inventors: |
Pomet, Alain; (Rousset,
FR) |
Correspondence
Address: |
CHRISTOPHER F. REGAN, ESQUIRE
ALLEN, DYER, DOPPELT, MILBRATH & GILCHRIST, P.A.
P.O. Box 3791
Orlando
FL
32802-3791
US
|
Assignee: |
STMicroelectronics S.A.
7, Avenue Gallieni
Gentilly
FR
94250
|
Family ID: |
9553574 |
Appl. No.: |
09/740269 |
Filed: |
December 19, 2000 |
Current U.S.
Class: |
327/203 |
Current CPC
Class: |
H03K 3/35625 20130101;
H03K 3/0372 20130101; G06K 19/073 20130101 |
Class at
Publication: |
327/203 |
International
Class: |
H03K 003/3562 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 21, 1999 |
FR |
99 16180 |
Claims
That which is claimed is:
1. A master-slave D type flip-flop circuit comprising a master
stage followed by a slave stage, the two stages having an identical
structure comprising a first pass gate for the transmission, on an
internal node, of an input data element, a storage loop with
inverters, connected to said internal node to supply a data element
at output of the stage and comprising a second pass gate for the
transmission, on said internal node, of the data element
complementary to the output data element, wherein the flip-flop
circuit furthermore comprises a power consumption masking circuit
comprising in parallel, at each of the stages, namely the master
and slave stage, a reference stage with a similar structure whose
storage loop is disconnected from the output of the associated
master or slave stage, the second pass gate of the storage loop of
the reference stage being connected between the output of the
associated master stage or slave stage and the internal node of the
reference stage.
2. A master-slave D type flip-flop circuit according to claim 1,
wherein the storage loop in each of the reference stages is formed
by a load that is equivalent, when seen from the internal node of
the stage, to the chain of inverters of the storage loop of the
master stage or slave stage.
3. An integrated circuit comprising several master-slave D type
flip-flops according to claim 1 or 2.
4. An integrated circuit according to claim 3, wherein said
flip-flop circuits form registers to process confidential data.
5. A smart card or microcircuit comprising an integrated circuit
according to claim 3 or 4.
6. An electronic system using a smart card or a microcircuit
according to claim 5.
Description
FIELD OF THE INVENTION
[0001] The present invention relates to the field of electronic
circuits, and, more particularly, to a master-slave D type
flip-flop circuit with a secured structure. The present invention
may be used in applications in which access to services or data is
strictly monitored, and in which electronic circuits implementing
security hardware and/or software are used. Electronic circuits of
this kind are used especially in chip cards or microelectronic
circuits for certain applications such as accessing certain data
banks, banking applications, and the like. For these applications,
such electronic circuits have an architecture formed around a
microprocessor and memories. These circuits may be used, for
example, to process secret or confidential data, to encipher
messages with cryptography algorithms, to decipher received
messages, or to compute signatures.
BACKGROUND OF THE INVENTION
[0002] It has been observed that external attacks on a circuit may
be carried out based upon the differential analysis of current
consumption of the circuit during the performance of certain
instructions. In particular, it is possible to determine all or
part of a secret key used in a cryptography algorithm performed by
a microprocessor. These external attacks, known as differential
power analysis or DPA attacks, are based on the fact that the
current consumption of the microprocessor carrying out instructions
varies according to the data being handled. For example, when an
instruction performed by the microprocessor requires bit-by-bit
handling, there are two different power consumption profiles at the
instant of execution, depending on whether the bit being handled is
equal to 1 or 0.
[0003] Thus, the DPA attack makes use of the difference in the
current consumption profile in the electronic circuit during the
performance of an instruction depending on the value of the bit or
bits handled. Stated alternatively, this attack uses a statistical
approach to verify assumptions concerning the value of the bits of
a confidential data element. This is done by making the same
scenario run several times in the electronic circuit, with
different input values of this scenario, and by analyzing all the
consumption profiles obtained.
[0004] The present invention is designed to make it more difficult
to carry out DPA attacks of this kind on certain instructions. More
specifically, the present invention makes it impossible in the
first order approach to differentiate between the handling of a 1
and the handling of a 0 by these instructions through the
differential analysis of the consumption profiles.
[0005] All the data elements handled in an electronic circuit
travel in transit, between memories and the microprocessor, through
registers. Other registers are used by the microprocessor to store
data during the execution of certain programs. More particularly,
some of these registers are required to transmit sensitive data,
such as a secret key of a cryptography algorithm.
[0006] These registers are usually based on master-slave D type
flip-flop circuits. In this type of flip-flop circuit, if a new
data element corresponding to a data element already stored in this
flip-flop circuit is presented at the input, there is no switching
in the flip-flop circuit. The switching in the flip-flop circuit
gives rise to a specified current consumption. Thus, depending on
whether the data changes or does not change in the flip-flop
circuit, there are two distinct consumption profiles (or
signatures), and this fact may render a DPA attack possible while
these registers are being used.
SUMMARY OF THE INVENTION
[0007] It is an object of the invention to provide a secured
master-slave D type flip-flop circuit so that a current consumption
profile of the flip-flop circuit is independent of the data handled
therein.
[0008] The basic idea of the invention is that the flip-flop
circuit will always provide a switching operation, whatever the
state at the time, of the flip-flop circuit and the state of the
new data element presented at the input.
[0009] The invention therefore relates to a master-slave D type
flip-flop circuit including a master stage followed by a slave
stage. The two stages may have an identical structure including a
first pass gate for the transmission on an internal node of an
input data element and a storage loop with inverters connected to
the internal node to supply a data element at an output of the
stage. The storage loop may also include a second pass gate for the
transmission on the internal node of the data element complementary
to the output data element.
[0010] The flip-flop circuit may also include a power consumption
masking circuit including, at each of the stages (i.e., the master
and slave stage), a parallel reference stage with a similar
structure whose storage loop is disconnected from the output of the
associated master or slave stage. The second pass gate of the
storage loop of the reference stage may be connected between the
output of the associated master stage or slave stage and the
internal node of the reference stage.
[0011] The invention also relates to an integrated circuit
including at least one secured flip-flop circuit as described
above. Such integrated circuit is especially suited for registers
that are required to process confidential or secret data
elements.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Other features and advantages of the invention will be
described in detail in the following description of different
embodiments, given by way of a non-limitative example, with
reference to the appended figures, in which:
[0013] FIG. 1 is a schematic diagram of a master-slave D type
flip-flop circuit according to the prior art;
[0014] FIG. 2 is a schematic diagram of a master-slave D type
flip-flop circuit according to the present invention;
[0015] FIG. 3 is a timing diagram showing the changes undergone at
the different internal nodes in the flip-flop circuit of FIG. 2 as
a function of the input data elements; and
[0016] FIGS. 4a and 4b are schematic diagrams illustrating the
equivalent diagram of a master-slave flip-flop circuit according to
the invention at a high level and a low level, respectively, of the
clock signal H for the sequencing of the flip-flop circuit.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0017] A typical structure of a master-slave D type flip-flop
circuit is shown in FIG. 1. It has a master stage M followed by a
slave stage S. These two stages have identical structures
corresponding to a D type flip-flop circuit, and they are
controlled in phase opposition.
[0018] Referring to the master stage M, this structure has a first
pass gate FM1 and a second pass gate FM2, each connected at their
outputs to the same input internal node NM of a storage loop BM by
inverters. These two pass gates FM1, FM2 are controlled in phase
opposition by a clock signal H for the sequencing of the flip-flop
circuit. The first pass gate FM1 is used for the transmission on
the node NM of the data element DATA applied to the input of the
stage in one phase. The second pass gate FM2 enables the imposition
on the node NM of the complementary data element NQM of the output
QM of the stage in the other phase.
[0019] Each pass gate typically has two transistors of opposite
types. As seen in FIG. 1, these may be a P type MOS transistor and
an N type MOS transistor. The transistors of a pass gate are
controlled from the clock signal H for the sequencing of the
flip-flop circuit so that they are on at the same time and off at
the same time.
[0020] The first pass gate FM1 is equivalent to an open circuit on
the high level of the clock signal H and equivalent to a short
circuit on the low level of the clock signal. The second pass gate
FM2 is equivalent to a short circuit on the high level of the clock
signal H and equivalent to an open circuit on the low level of the
clock signal. The storage loop BM has a first inverter connected
between the internal node NM and the output QM of the stage and a
second inverter connected between the output QM and the second pass
gate FM2. Thus, at the output of the second inverter, there is a
complementary output NQM applied to the input of the second pass
gate FM2.
[0021] The slave stage has an identical structure. As such, the
references corresponding to the references FM1, FM2, NM, BM, QM and
NQM in the master stage are the references FS1, FS2, NS, BS, QS and
NQS in the slave stage. The pass gates of the slave stage are
controlled in phase opposition with respect to the pass gates of
the master stage. Thus, the first pass gate FM1 of the master stage
and the second pass gate FS2 of the slave stage are on (i.e.,
equivalent to short circuits) at the low level of the clock signal
H and off (i.e., equivalent to open circuits) at the high level of
the clock signal H. The second pass gate FM2 of the master stage
and the first pass gate FS1 of the slave stage are on (i.e.,
equivalent to short circuits) on the high level and off (i.e.,
equivalent to open circuits) on the low level of the clock signal
H.
[0022] With such a master-slave D flip-flop circuit according to
the prior art, if a new data element identical to the previous data
element comes to the input of the master stage, no switching
operation will take place either in the master stage or in the
slave stage. Indeed, if the node NM is already at the level of the
new data element at the input, there will be no change in either of
the two storage loops, master and slave, and therefore no switching
in the master-slave D type flip-flop circuit. However, if a data
element of a different level is applied to the input of the
master-slave flip-flop circuit, at the first trailing edge that
follows there will be a switching operation in the storage loop of
the master stage. Then, at the next leading edge, there will be a
switching operation in the storage loop of the slave stage.
[0023] Thus, with a master-slave D type flip-flop circuit according
to the prior art, it is possible at a given time, depending on the
data element handled at the input, to have either no switching
operation in the flip-flop circuit or a switching operation in the
storage loop of either of the master or the slave stage. This
characteristic of operation of the master-slave D flip-flop circuit
enables a differential analysis on the current signature of a
circuit when it uses registers based on such flip-flop circuits.
This is because, depending on the data handled, the current
consumption profile of the circuit is different.
[0024] Turning now to FIG. 2, a master-slave D type flip-flop
circuit according to the present invention is illustrated. This
flip-flop circuit may be used to obtain the same consumption
profile in all cases in forcing the selection switching in the
flip-flop circuit at each high level and low level of the clock.
This may be done independently of the flow of input data.
[0025] This flip-flop circuit has two stages, namely a master stage
M and a slave stage S as above, with identical structures. To
simplify the description, the same reference labels will be used in
FIG. 2 for the elements common to FIG. 1. According to the
invention, a consumption masking circuit is included in the
flip-flop circuit. This masking circuit includes, in parallel on
each of the master and slave stages, a reference or "dummy" stage
with a similar structure whose storage loop is disconnected from
the output of the associated master or slave stage. The second pass
gate of this storage loop of the reference stage is connected
between the output of the associated master or slave stage and the
internal node of the reference stage.
[0026] For the storage loop of the reference stage, the same chain
of inverters may be used as that of the storage loops of the master
and slave stages. Also, the equivalent load of this chain of
inverters may be obtained, as seen from the internal node of the
main stage, to obtain behavior (in terms of consumption) that is
identical to that of the storage loop of the main stage with which
the reference stage is associated. The two inverters of the loop
may then be replaced by an equivalent capacitor connected between
the internal node and ground. This is sufficient for a first-order
approach. Another capacitor (not shown) may be included between the
supply voltage and the internal node for a more efficient
approximation of the behavior of the two inverters in selection
switching.
[0027] As seen in FIG. 2, the reference stage Md of the master
stage also includes a first pass gate FM1d to transmit the input
data element DATA on the internal node Nmd. A storage loop BMd
includes two series-connected inverters with the same
characteristics as those of the storage loop of the master stage.
Also included is a second pass gate FM2d for the transmission of
the output QM of the master stage to the internal node NMd of the
reference stage.
[0028] The reference stage Sd of the slave stage S similarly
includes a first pass gate FS1d for the transmission of the state
of the output QM of the master stage to an internal node NSd, a
storage loop BSd including two series-connected inverters with the
same characteristics as those of the storage loop of the master
stage, and a second pass gate FS2d to transmit the output QS of the
slave stage to the internal node NSd of the reference stage. The
pass gates of each reference stage are controlled in the same way
as the corresponding pass gates in the associated main stage.
[0029] By including a reference stage of this kind on each of the
master and slave stages of the flip-flop circuit, a systematic
switching operation is enforced in the flip-flop circuit on each
clock edge, whatever the data present at input. This forced
switching operation in the flip-flop circuit includes in practice
switching two of the four storage loops of the stage on each edge.
This causes the switching of each of the inverters of these two
loops. Thus, on each of the leading and trailing edges of the clock
signal for sequencing the flip-flop circuit, the same current
consumption profile is obtained (as a first-order result)
independently of the input data element.
[0030] The foregoing will be further illustrated with reference to
FIG. 3. The timing diagram of FIG. 3 represents the different
states of the internal input nodes of the four storage loops of a
flip-flop circuit according to the invention for a flow of data
elements DATA presented at the input of the secured master-slave D
type flip-flop circuit. Also, for ease of understanding, FIGS. 4a
and 4b show the structure of the flip-flop circuit according to the
present invention with the equivalent diagram of the pass gates at
the high level and the low level, respectively, of the clock signal
H.
[0031] A leading edge of the clock signal H makes the flip-flop
circuit go into a next stage, shown in FIG. 4a. That is, the gates
FM1, FM1d, FS2, FS2d are on, and the gates FM2, FM2d, FS1, FS1d are
off. A leading edge of the clock signal H makes the flip-flop
circuit go into a next state, shown in FIG. 4b. That is, the gates
FM1, FM1d, FS2, FS2d are off, and the gates FM2, FM2d, FS1, FS1d
are on.
[0032] In the exemplary operating sequence shown in FIG. 3, the
starting conditions as are follows: the clock signal H is at a low
level or 0; the internal node NM of the master stage is at 0; the
internal node NMd of the associated reference stage is at 0; the
internal node NS of the slave stage is at 1; and the internal node
NSd of the associated reference stage is at 0. On the first leading
edge of the clock signal H, (FIG. 4a) the node NM cut off from the
input DATA remains unchanged, i.e., at 0. There is therefore no
switching operation in the storage loop of the master stage. The
output QM of the master stage is at 1. Since the internal node NS
of the slave stage is already at 1, there is no change at the input
of the storage loop of the slave stage, and therefore no switching
in this loop.
[0033] However, the gate FM2d of the reference stage associated
with the master stage makes the internal node NMd go from 0 to 1,
leading to a switching in the associated storage loop. The gate
FS1d of the reference stage of the slave stage makes the associated
internal node NSd go from 0 to 1. This gives rise to a switching in
the associated storage loop. Thus, on this first leading edge,
there is a switching operation in each of the reference stages of
the flip-flop circuit.
[0034] On the next trailing edge (FIG. 4b), DATA is still at 0. The
internal node NM of the master stage remains at 0. There is
therefore no switching in the storage loop of the master stage.
However, the gate FM1d makes the internal node NMd go from 1 to 0,
leading to a switching operation in the associated storage loop.
The internal node NS of the slave stage remains unchanged, i.e., at
1. The gate FS2d of the slave stage makes the internal node NSd of
the slave reference stage go from 1 to 0, leading to a switching
operation in the storage loop of this reference stage. Thus, on
this trailing edge, there is a selection switching operation in
each of the references stages of the flip-flop circuit.
[0035] On the next leading edge, the data element DATA has gone to
1. The node NM cut off from the input DATA remains unchanged, i.e.,
at 0. There is therefore no switching in the storage loop of the
master stage. The output QM of the master stage is at 1. The gate
FM1d therefore makes the internal node NMd go from 0 to 1, leading
to a switching operation in the storage loop of the associated
reference stage. The internal node NS of the slave stage remains
unchanged, since it is already at 1. There is therefore no
switching in the storage loop of the reference stage. The gate FS1d
of the slave reference stage makes the internal node NSd of the
slave reference stage go from 0 to 1, leading to a switching
operation in the associated storage loop. Thus, on this leading
edge, there is a switching operation in each of the reference
stages of the flip-flop circuit.
[0036] On the next trailing edge, DATA is still at 1. The internal
node NM of the master stage goes from 0 to 1, thus leading to a
switching operation in the storage loop of the master stage. The
internal node NMd remains at 1. There is therefore no switching in
the storage loop of the reference stage associated with the master
stage. The internal node NS of the slave stage remains unchanged,
i.e., at 1.
[0037] The gate FS2d of the slave stage makes the internal node NSd
of the associated reference stage go from 1 to 0, leading to a
switching operation in the storage loop of this reference stage.
Thus, on this trailing edge, there is a switching operation in the
master stage and in the reference stage associated with the slave
stage.
[0038] It can thus be shown that, whatever the conditions in the
flip-flop circuit and whatever the flow of data at the input, there
will always be a switching of two of the loops of the secured D
type master-slave flip-flop circuit according to the invention. In
FIG. 3 crosses are used to indicate the switching operations
carried out at each edge of the clock signal. The switching of a
loop must, of course, be understood to mean the switching of each
of the inverters of the loop. In the reference stages, if the
storage loop is made by an equivalent capacitor, this results in
the switching of this capacitor, or more precisely in its charging
or its discharging.
[0039] The use of a secured master-slave D type flip-flop circuit
of this kind for each cell of the registers required to process
confidential data elements in an electronic circuit thus prevents
DPA attacks from being made during the time in which these
registers are used. It will be noted that, in practice, when these
registers are used, they are not the site of any switching (the
clock signal is not transmitted).
[0040] A secured master-slave D type flip-flop circuit according to
the invention may be used in numerous applications in which it is
desired to prevent differential analysis of the current
consumption. Of course, the invention is not limited to the
structure of the flip-flop circuit described above. In particular,
the term "inverter" must be taken in its wider functional sense,
independently of its constitution.
* * * * *