U.S. patent application number 09/280892 was filed with the patent office on 2001-05-31 for method of fabricating dual damascene structure.
Invention is credited to HUANG, CHAO-YUAN, LUR, WATER, WU, JUAN-YUAN.
Application Number | 20010002333 09/280892 |
Document ID | / |
Family ID | 21639875 |
Filed Date | 2001-05-31 |
United States Patent
Application |
20010002333 |
Kind Code |
A1 |
HUANG, CHAO-YUAN ; et
al. |
May 31, 2001 |
METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE
Abstract
A method of fabricating a dual damascene is provided. A
dielectric layer is formed on a substrate. A diffusion barrier
layer is formed on the dielectric layer. A portion of the diffusion
barrier layer and the dielectric layer is removed to form a trench
and a via hole. A barrier layer is formed on the diffusion barrier
layer and in the trench and the via hole. The barrier layer on the
diffusion barrier layer is removed by chemical-mechanical
polishing. A conductive layer is formed in the trench and the via
hole by selective deposition. A planarization step is performed
with the diffusion barrier layer serving as a stop layer.
Inventors: |
HUANG, CHAO-YUAN; (HSINCHU,
TW) ; WU, JUAN-YUAN; (HSINCHU, TW) ; LUR,
WATER; (TAIPEI, TW) |
Correspondence
Address: |
DANIEL R MCCLURE
THOMAS KAYDEN HORSTEMEYER & RISLEY
100 GALLERIA PARKWAY NW
SUITE 1500
ATLANTA
GA
30339
|
Family ID: |
21639875 |
Appl. No.: |
09/280892 |
Filed: |
March 29, 1999 |
Current U.S.
Class: |
438/637 ;
257/E21.579; 257/E21.583; 257/E21.586; 438/640; 438/652; 438/680;
438/687 |
Current CPC
Class: |
H01L 21/7684 20130101;
H01L 21/76879 20130101; H01L 21/76807 20130101 |
Class at
Publication: |
438/637 ;
438/687; 438/640; 438/652; 438/680 |
International
Class: |
H01L 021/4763; H01L
021/44 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 5, 1999 |
TW |
88103376 |
Claims
What is claimed is:
1. A method of fabricating a dual damascene structure, comprising
the steps of: forming a dielectric layer on a substrate; forming a
diffusion barrier layer on the dielectric layer; removing a portion
of the diffusion barrier layer and the dielectric layer to form a
trench and a via hole; forming a barrier layer over on the
diffusion barrier layer and in the trench and the via hole;
removing the barrier layer on the diffusion barrier layer; forming
a conductive layer in the trench and the via hole; and performing a
planarization step with the diffusion barrier layer serving as a
stop layer.
2. The method of claim 1, wherein the conductive layer comprises
copper.
3. The method of claim 2, wherein the conductive layer is formed by
selective chemical vapor deposition.
4. The method of claim 2, wherein a material of the diffusion
barrier layer is silicon nitride.
5. The method of claim 2, wherein a material of the barrier layer
is Ta/TaN.
6. The method of claim 2, wherein the step of removing the barrier
layer on the diffusion barrier layer is performed by
chemical-mechanical polishing.
7. The method of claim 2, wherein the planarization process
comprises chemical-mechanical polishing.
8. The method of claim 1, wherein the conductive layer is formed by
selective chemical vapor deposition.
9. The method of claim 1, wherein a material of the diffusion
barrier layer is silicon nitride.
10. The method of claim 1, wherein a material of the barrier layer
is Ta/TaN.
11. The method of claim 1, wherein the step of removing the barrier
layer on the diffusion barrier layer is performed by
chemical-mechanical polishing.
12. The method of claim 1, wherein the planarization process
comprises chemical-mechanical polishing.
13. A method of fabricating a dual damascene structure, comprising
the steps of: forming a dielectric layer on a substrate; forming a
diffusion barrier layer on the dielectric layer; removing a portion
of the diffusion barrier layer and the dielectric layer to form a
trench and a via hole; forming a barrier layer on the diffusion
barrier layer and in the trench and the via hole; performing a
chemical-mechanical polishing step to remove the barrier layer on
the diffusion barrier layer; forming a copper layer in the trench
and the via hole by selective deposition; and performing a
planarization process by chemical-mechanical polishing with the
diffusion barrier layer serving as a stop layer.
14. The method of claim 13, wherein the step of forming the
conductive layer comprises selective chemical vapor deposition.
15. The method of claim 13, wherein the diffusion barrier layer
comprises a silicon nitride layer.
16. The method of claim 13, wherein the barrier layer comprises
Ta/TaN.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a fabricating method of
multi-layered interconnections. More particularly, the present
invention relates to a method of fabricating a dual damascene
structure.
[0003] 2. Description of the Related Art
[0004] Due to the increased number of devices incorporated in a
semiconductor circuit and the corresponding size reduction of the
devices, material property is an important factor that affects
device performance. For example, the material of the metallic
multi-layered interconnections greatly affects resistance of the
devices. Thus, in order to reduce the resistance, it is an
important subject to select a suitable metallic material.
[0005] Copper has many good qualities such as a low resistivity and
a high electromigration resistance. In addition, copper can be
formed by chemical vapor deposition (CVD) or electroplating. Thus,
copper is widely used in sub-micron process to form multi-layered
interconnects. However, some problems still occur when using copper
in sub-micron process. For example, copper is easily oxidized and
eroded. It is difficult to pattern copper by dry etching. The
adhesion between copper and dielectric materials is poor.
Furthermore, copper easily diffuses into the dielectric materials
so that the reliability of devices is decreased.
[0006] To solve the above-described problems, the conventional
method uses a dual-damascene technique with a chemical-mechanical
polishing step. FIGS. 1A through 1C are schematic, cross-sectional
views showing a conventional method of fabricating a dual damascene
structure. A dual-damascene technique is a technique that forms a
metallic interconnection 114 (FIG. 1B) in a dielectric layer 106.
In FIG. 1A, a dielectric layer 106 is first formed over a substrate
100, and then the dielectric layer 106 is planarized. According to
the required design, the dielectric layer 106 is then patterned. A
trench 108 and a via hole 110 are formed to expose a portion of the
conductive layer 102. In FIG. 1B, a barrier layer 112 is formed
over the substrate 100. A copper layer 114 is formed over the
substrate 100 to fill the trench 108 and the via hole 110. A
conductive line and a via contact are thus simultaneously
formed.
[0007] The barrier layer 112 having a high stability is used to
solve the above-described problems, such as copper atom diffusion
and poor adhesion between the copper layer 114 and the dielectric
layer 106. As shown in FIG. 1C, a chemical-mechanical polishing
(CMP) step is performed. Because it is difficult to etch the copper
layer 114, the conventional method solves this difficulty by using
the CMP step instead of performing an etching step. Thus, the
difficulty in etching the copper layer 114 does not occur.
[0008] Typically, the material of the barrier layer 112 in the dual
damascene structure is tantalum/tantalum nitride (Ta/TaN). Because
it is difficult to remove the Ta/TaN layer by chemical-mechanical
polishing, the dual damascene structure is still formed with
difficulty. In order to remove the barrier layer 112, it is
necessary for the conventional method to perform an over-polishing
step. Since the etching rate for the Ta/TaN barrier layer 112 is
lower than that of the copper layer 114, the copper layer 114 is
easily dished or suffers from an erosion problem. Thus, the process
is still not optimal.
SUMMARY OF THE INVENTION
[0009] The invention provides a method of fabricating a dual
damascene structure. A dielectric layer is formed on a substrate. A
diffusion barrier layer is formed on the dielectric layer. A
portion of the diffusion barrier layer and the dielectric layer is
removed to form a trench and a via hole. A barrier layer is formed
on the diffusion barrier layer and in the trench and the via hole.
The barrier layer on the diffusion barrier layer is removed by
chemical-mechanical polishing. A conductive layer is formed in the
trench and the via hole by selective deposition. A planarization
step is performed with the diffusion barrier layer serving as a
stop layer.
[0010] During the selective deposition of the conductive layer, the
barrier layer serves as an activation center for selective
deposition. The conductive layer easily fills the trench and the
via hole. In contrast, since the diffusion barrier layer does not
serve as an active center, it is difficult to deposit the
conductive layer on the diffusion barrier layer. Thus, there is a
high selectivity of the conductive layer between the barrier layer
and the diffusion barrier layer.
[0011] The invention removes the barrier layer, which is on the
diffusion barrier layer, before the step of forming the conductive
layer in the trench and the via hole. The conductive layer is then
formed by selective deposition. There is a high selectivity between
the barrier layer, which is in the trench and the via hole, and the
diffusion barrier layer. Thus, the conductive layer is deposited
almost only in the trench and the via hole. Therefore, the
undesired conductive layer on the diffusion barrier layer can be
easily removed by chemical-mechanical polishing, so as to prevent
the occurrence of a dishing effect and a erosion problem of the
conductive layer.
[0012] It is to be understood that both the foregoing general
description and the following detailed description are exemplary,
and are intended to provide further explanation of the invention as
claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The accompanying drawings are included to provide a further
understanding of the invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the invention and, together with the description,
serve to explain the principles of the invention. In the
drawings,
[0014] FIGS. 1A through 1C are schematic, cross-sectional views
showing a conventional method of fabricating a dual damascene
structure.
[0015] FIGS. 2A through 2F are schematic, cross-sectional views
showing a method of fabricating a dual damascene structure
according to one preferred embodiment of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0016] Reference will now be made in detail to the present
preferred embodiments of the invention, examples of which are
illustrated in the accompanying drawings. Wherever possible, the
same reference numbers are used in the drawings and the description
to refer to the same or like parts.
[0017] The preferred embodiment takes a dual damascene as an
example to explain the present invention. In practice, the
invention can also be utilized in a process of forming a metallic
line or a process of forming a contact or a via. The present
invention is not limited to the method of forming a dual damascene
structure.
[0018] FIGS. 2A through 2F are schematic, cross-sectional views
showing a method of fabricating a dual damascene structure
according to one preferred embodiment of the invention.
[0019] In FIG. 2A, a conductive layer 202 is formed in the
substrate 200. A cap layer 204 is formed on the substrate 200 to
cover the conductive layer 202. A dielectric layer 206 and a
diffusion barrier layer 207 are formed in sequence over the
substrate 200.
[0020] The material of the conductive layer 202 includes copper.
The conductive layer 202 can be formed by chemical vapor deposition
or electroplating. The thickness of the conductive layer 202 is
preferably about 3000 angstroms to 5000 angstroms, but is not
limited to this thickness. The material of the cap layer 204 is
preferably a material that can prevent the oxidation of the
conductive layer 202 and can also prevent atoms or ions of the
conductive layer 202 from diffusing into the dielectric layer 206.
The thickness of the cap layer 204 is preferably about 600
angstroms to 1000 angstroms. In a case where a material of the
conductive layer 202 is copper, the material of the cap layer 204
is preferably silicon nitride (SiN) and SiC formed by, for example,
chemical vapor deposition.
[0021] The dielectric layer 206 is preferably a silicon oxide layer
formed by plasma-enhanced chemical vapor deposition (PECVD), or
spin-on polymer (SOP) with a low dielectric constant. The SOP
includes flare, SILK, Parylene, or PAE-II.
[0022] The diffusion barrier layer 207 is used to prevent the
conductive layer 202 from diffusing into the dielectric layer 206
while depositing the conductive layer 202. There is a deposition
selectivity between the diffusion barrier layer 207 and the
dielectric layer 206 while depositing the conductive layer 214. The
material of the diffusion barrier layer 207 is preferably silicon
nitride formed by, for example, chemical vapor deposition.
[0023] In FIG. 2B, a trench 206 and a via hole 210 are formed in
the diffusion barrier layer 207, the dielectric layer 206, and the
cap layer 204 by the following exemplary steps. A patterned
photoresist layer (not shown) comprising an opening is formed over
the diffusion barrier layer 207. The location of the opening
exposes the location of the via hole 210 above the conductive layer
202. An etching step is performed with the cap layer 204 serving as
an etching stop point. The pattern of the photoresist layer is
transferred to form the via hole 210. A via hole 210 exposing the
cap layer 204 is formed in the diffusion barrier layer 207 and the
dielectric layer 206. The photoresist layer is removed. Another
photoresist layer (not shown) is formed on the dielectric layer
206, so as to form the trench 210. The diffusion barrier layer 207
and the dielectric layer 206 are patterned with the photoresist
layer serving as an etching mask. A trench 208 is formed in the
diffusion barrier layer 207 and the dielectric layer 206. The
photoresist layer is removed. The cap layer 204 exposed by the via
hole 210 is removed.
[0024] In FIG. 2C, a conformal barrier layer 212 is formed over the
substrate 200, in the trench 208 and the via hole 210, and over the
diffusion barrier layer 207. Preferably, a material of the barrier
layer 212 is titanium/titanium nitride (Ti/TiN), tantalum (Ta),
tantalum nitride (TaN), tantalum/tantalum nitride (Ta/TaN), or
tungsten nitride.
[0025] In FIG. 2D, the barrier layer 212 on the diffusion barrier
layer 207 is removed. Preferably, a chemical-mechanical polishing
step is performed with the diffusion barrier layer 207 serving as
an etching stop. The barrier layer 212 is polished until the
diffusion barrier layer 207 is exposed.
[0026] In FIG. 2E, a selective deposition step is performed. A
conductive layer 214 is formed over the substrate 200 and in the
trench 208 and the via hole 210. The material of the conductive
layer 214 is preferably copper. The step of forming the conductive
layer 214 is preferably performed by selective deposition, such as
selective chemical vapor deposition. In a case where a material of
the conductive layer 214 is copper, the material of the barrier
layer 212 is preferably Ta/TaN.
[0027] The following description takes the following materials as
examples: if a material of the conductive layer 214 is copper, a
material of the barrier layer 212 is Ta/TaN and a material of the
diffusion barrier layer 207 is silicon nitride. During the
selective chemical vapor deposition of the copper conductive layer
214, the Ta/TaN barrier layer 212 serves as an activation center
for selective chemical vapor deposition. Thus, the copper
conductive layer 214 easily fills the trench 208 and the via hole
210. In contrast, since the silicon-nitride diffusion barrier layer
207 does not serve as an active center, it is difficult to deposit
the copper conductive layer 214 on the diffusion barrier layer 207.
As explained in the above description, there is a high selectivity
of the copper conductive layer 214 between the barrier layer 212
and the diffusion barrier layer 207.
[0028] In FIG. 2F, a planarization process is performed to remove a
portion of the conductive layer 212. Preferably, a
chemical-mechanical polishing is performed with the diffusion
barrier layer 207 serving as a stop layer. The conductive layer 214
is removed until the diffusion barrier layer 207 is exposed.
[0029] In the invention, a selective ratio of the barrier layer 212
and the diffusion barrier layer 207 is not necessarily 100%. If
there is a portion of the conductive layer 212 deposited on the
diffusion barrier layer 207, the conductive layer 212 on the
diffusion barrier layer 207 can be easily removed in the following
planarization process. Thus, a dishing effect and an erosion
problem do not occur.
[0030] In the conventional method, in order to remove a Ta/TaN
barrier layer by chemical-mechanical polishing, a dishing effect
and an erosion problem occur on the conductive layer. The invention
solves the difficulty by removing the barrier layer 212 on the
diffusion barrier layer 207 before the step of depositing
conductive layer 214. Thus, when the planarization process is
performed to remove a portion of the conductive layer 214, no
barrier layer 212 needs to be removed. Thus, the dishing effect and
the erosion problem, as found in the conventional method because of
over polishing, do not occur.
[0031] Accordingly, the invention removes a barrier layer on a
diffusion barrier layer before the step of forming a conductive
layer in a trench and a via hole. The conductive layer is then
formed by selective deposition. There is a high selectivity between
the barrier layer, which is in the trench and the via hole, and the
diffusion barrier layer. Thus, the conductive layer is deposited
almost only in the trench and the via hole. Therefore, the
undesired conductive layer on the diffusion barrier layer can be
easily removed by chemical-mechanical polishing, so as to prevent
the occurrence of the dishing effect and the erosion problem found
in the conventional method.
[0032] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure and the
method of the present invention without departing from the scope or
spirit of the invention. In view of the foregoing, it is intended
that the present invention cover modifications and variations of
this invention provided they fall within the scope of the following
claims and their equivalents.
* * * * *