U.S. patent application number 09/751212 was filed with the patent office on 2001-05-24 for method of forming contact openings.
Invention is credited to Dennison, Charles H..
Application Number | 20010001506 09/751212 |
Document ID | / |
Family ID | 22430817 |
Filed Date | 2001-05-24 |
United States Patent
Application |
20010001506 |
Kind Code |
A1 |
Dennison, Charles H. |
May 24, 2001 |
Method of forming contact openings
Abstract
A method for forming a contact opening is described and which
includes providing a node location to which electrical connection
is to be made; forming a conductive line adjacent the node
location, the conductive line having a conductive top and sidewall
surfaces; forming electrically insulative oxide in covering
relation relative to the top surface of the conductive line;
forming electrically insulative nitride sidewall spacers over the
conductive sidewall surfaces, the nitride sidewall spacers
projecting outwardly of the conductive line top conductive surface,
the electrically insulative oxide positioned between the nitride
sidewall spacers; forming an electrically insulative layer
outwardly of the conductive line, and the node location; and
etching a contact opening to the node location or the top surface
through the electrically insulative layer substantially selective
relative to the nitride sidewall spacers.
Inventors: |
Dennison, Charles H.;
(Meridian, ID) |
Correspondence
Address: |
WELLS ST JOHN ROBERTS GREGORY AND MATKIN
SUITE 1300
601 W FIRST AVENUE
SPOKANE
WA
992013828
|
Family ID: |
22430817 |
Appl. No.: |
09/751212 |
Filed: |
December 29, 2000 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09751212 |
Dec 29, 2000 |
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09285322 |
Apr 2, 1999 |
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09285322 |
Apr 2, 1999 |
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09127577 |
Jul 31, 1998 |
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Current U.S.
Class: |
257/774 ;
257/412; 257/773; 257/E23.019; 438/586; 438/595 |
Current CPC
Class: |
H01L 2924/0002 20130101;
H01L 2924/0002 20130101; H01L 2924/00 20130101; H01L 23/485
20130101 |
Class at
Publication: |
257/774 ;
438/586; 438/595; 257/412; 257/773 |
International
Class: |
H01L 021/3205; H01L
021/4763; H01L 029/76 |
Claims
1. A method for forming first and second contact openings,
comprising: providing an electronic component having a top surface
on a semiconductive substrate, the semiconductive substrate having
a node location to which electrical contact is to be made; forming
a layer of insulative material in covering relation relative to the
electronic component; and in the same masking step, forming the
first contact opening through the layer of insulative material to
the top surface of the electronic component, and the second contact
opening through the layer of insulative material to the node
location.
2. A method as claimed in claim 1, wherein before providing the
layer of insulative material, forming a layer of sacrificial
material on the electronic component.
3. A method as claimed in claim 1, wherein the electronic component
has sidewalls, and the method further comprises forming an
insulative spacer on the sidewalls, and wherein before providing
the layer of insulative material, forming a layer of sacrificial
material on the electronic component.
4. A method as claimed in claim 1, wherein the electronic component
has sidewalls, and the method further comprises forming an
insulative spacer on the sidewalls, and wherein before providing
the layer of insulative material, forming a layer of sacrificial
material on the electronic component, and wherein after the step of
forming the layer of sacrificial material, the method comprises the
step of removing the layer of sacrificial material selectively
relative to the insulative spacers.
5. A method as claimed in claim 4, wherein after selectively
removing the layer of sacrificial material and before forming the
layer of insulative material, the method comprises the step of
forming a layer of material in covering relation relative to the
electronic component and the substrate, and selectively removing
the layer of material to provide second spacers partially covering
the top surface of the electronic component, the second spacers
extending outwardly relative to the top surface of the electronic
component.
6. A method as claimed in claim 5, wherein the layer of material
comprises nitride, and wherein the node location is adjacent the
electronic component and has a given target area, and wherein the
top surface of the electronic component is electrically conductive
and has a given target area, and wherein the first and second
spacers increase the size of each of the given target areas.
7. A method for forming first and second contact openings,
comprising: providing an electronic component on a semiconductive
substrate, the electronic component having a sidewall and a top
surface, and the semiconductive substrate having a node location to
which electrical contact is to be made; forming an insulative
spacer on the sidewall of the electronic component, the insulative
spacer having a portion which is disposed outwardly relative to the
top surface of the electronic component; forming a first layer of
material in covering relation relative to the top surface of the
electronic component; forming a second layer of insulative material
in covering relation relative to the electronic component and the
semiconductive substrate; and in the same masking step, forming the
first contact opening through the second layer of material to the
top surface of the electronic component and the second contact
opening through the second layer of material to the node
location.
8. A method as claimed in claim 7, wherein the electronic component
has sidewalls, and an insulative spacer is provided on the
sidewalls, and wherein the first layer of material is positioned
between the insulative spacers.
9. A method as claimed in claim 7, wherein the first layer of
material is sacrificial.
10. A method as claimed in claim 7, wherein the first layer of
material comprises polysilicon.
11. A method as claimed in claim 7, wherein the first layer of
material comprises oxide.
12. A method as claimed in claim 7, wherein the insulative spacer
comprises nitride.
13. A method as claimed in claim 7, wherein after providing the
first layer of material, and before providing the second layer of
material, the method comprises the step of etching the first layer
of material selectively relative to the insulative spacer.
14. A method as claimed in claim 13, wherein after selectively
etching the first layer of material and before forming the second
layer of material, forming a third layer of material in covering
relation relative to the electronic component and the substrate,
and selectively removing the third layer of material to provide
second spacers which are disposed in partially covering relation
relative to the top surface of the electronic component, the second
spacers extending outwardly relative to the top surface of the
electronic component.
15. A method as claimed in claim 14, wherein the third layer of
material comprises nitride, and wherein the node location is
adjacent the electronic component and has a given target area, and
wherein the top surface of the electronic component is electrically
conductive and has a given target area, and wherein the first and
second spacers increase the size of each of the given target
areas.
16. A method for forming a contact opening comprising: providing a
node location on a semiconductive substrate to which electrical
contact is to be made; forming an electronic component on the
semiconductive substrate adjacent the node location, the electronic
component having sidewalls and a top surface; forming a first
spacer on at least one of the sidewalls of the electronic
component; forming a second spacer in partial covering relation
relative to the top surface of the electronic component; forming an
insulative layer of material over the electronic component, first
and second spacers and the node location; and selectively etching
the insulative layer relative to the first and second spacers to
form a contact opening to at least one of the node location and the
top surface of the electronic component.
17. A method as claimed in claim 16, wherein the first and second
spacers comprise nitride, and wherein the first spacer extends
above the top surface of the electronic component, and wherein the
node location adjacent the electronic component and the top surface
of the electronic component each have a given target area, and
wherein the first and second spacers increase the size of each of
the given target areas.
18. A method as claimed in claim 16, wherein the electronic
component has opposite sidewalls, and individual first spacers are
formed on the opposite sidewalls, the first spacers extending above
the top surface of the electronic component.
19. A method as claimed in claim 16, wherein after forming the
electronic component, and before forming the first spacer, forming
a first layer of sacrificial material on the top surface of the
electronic component.
20. A method as claimed in claim 19, wherein after forming the
first spacer, selectively etching the first layer of sacrificial
material relative to the first spacer.
21. A method as claimed in claim 16, wherein the first and second
spacers comprise nitride.
22. A method as claimed in claim 19, wherein the first layer of
sacrificial material comprises polysilicon.
23. A method as claimed in claim 20, wherein after selectively
etching the first layer of sacrificial material, and before
providing the insulative layer of material, the method comprises
the steps of forming a third layer of material over the electronic
component and the is substrate; and selectively etching the third
layer of material to form the second spacer.
24. A method as claimed in claim 16, wherein a first contact
opening is formed to the node location and a second contact opening
is formed to the top surface of the electronic component, and
wherein each contact opening is formed in the same masking
step.
25. A method for forming a contact opening comprising: providing a
node location on a substrate to which electrical contact is to be
made; providing an electronic component on the substrate, and
adjacent the node location, the electronic component having
sidewalls and an electrically conductive top surface; forming a
first spacer on at least one of the sidewalls of the electronic
component; forming a second spacer in partial covering relation
relative to the top surface of the electronic component; forming an
insulative layer of material over the electronic component, first
and second spacers and the node location; and selectively etching
the insulative layer relative to the first and second spacers to
form a contact opening to the electrically conductive top surface
of the electronic component.
26. A method as claimed in claim 25, wherein selectively etching
the insulative layer further comprises forming a contact opening to
the node location.
27. A method as claimed in claim 25, wherein the first and second
spacers comprise nitride, and wherein the first spacer extends
above the top surface of the electronic component.
28. A method as claimed in claim 25, wherein the electronic
component has opposite sidewalls, and individual first spacers are
provided on the opposite sidewalls, the first spacers extending
above the top surface of the electronic component, and wherein the
node location and the top surface have a given target area, and
wherein the first and second spacers increase the given target
areas of the respective node location, and top surface.
29. A method as claimed in claim 25, wherein after forming the
electronic component, and before forming the first spacer, forming
a first layer of sacrificial material on the top surface of the
electronic component.
30. A method as claimed in claim 25, wherein after forming the
first spacer, selectively etching the first layer of sacrificial
material relative to the first spacer.
31. A method as claimed in claim 25, wherein the first and second
spacers comprise nitride.
32. A method as claimed in claim 29, wherein the first layer of
sacrificial material comprises polysilicon.
33. A method as claimed in claim 29, wherein after selectively
etching the first layer of sacrificial material, and before forming
the insulative layer of material, forming a third layer of material
in covering relation relative to the electronic component and the
substrate, and selectively etching the third layer of material to
form the second spacer.
34. A method for forming a contact opening to an electronic
component, comprising: forming an electronic component having a top
surface; forming an electrically insulative spacer in partial
covering relation relative to the top surface; forming an
insulating layer over the spacer and the top surface; and
selectively removing the insulative layer relative to the spacer to
form a contact opening to the electronic component top surface.
35. A method as claimed in claim 34, wherein the electronic
component is formed on a semiconductive substrate, and wherein a
node location is formed in the semiconductive substrate, and
wherein a contact opening is also formed to the node location.
36. A method as claimed in claim 34, wherein after forming the
electronic component and before forming the spacer, forming a first
layer of sacrificial material over the top surface of the
electronic component.
37. A method as claimed in claim 36, wherein the electronic
component has opposite sidewalls, and wherein after forming the
first layer of sacrificial material, and before forming the spacer,
forming an insulative sidewall spacer covering at least one of the
sidewalls of the electronic component.
38. A method as claimed in claim 37, wherein the sidewall spacer
extends above the top surface of the electronic component.
39. A method as claimed in claim 37, wherein individual sidewall
spacers are formed on the opposite sidewalls and extend above the
top surface of the electronic component, and wherein the first
layer of sacrificial material is formed between the sidewall
spacers, and wherein the top surface of the electronic component
has a given target area and the sidewall spacers effectively
increase the given target area.
40. A method as claimed in claim 37, wherein after forming the
first layer of sacrificial material and before forming the spacer,
etching the first layer of sacrificial material selectively
relative to the sidewall spacer.
41. A method as claimed in claim 40, wherein after selectively
etching the first layer of sacrificial material, forming a second
layer of material over the electronic component and selectively
etching the second layer of material to form the spacer in partial
covering relation relative to the top surface.
42. A method as claimed in claim 37, wherein the spacer comprises
nitride.
43. A method as claimed in claim 37, wherein the first layer of
sacrificial material comprises polysilicon.
44. A method for forming a contact opening, comprising: providing a
node location to which electrical connection is to be made, and a
conductive line adjacent the node location, the conductive line
having conductive top and sidewall surfaces; forming electrically
insulative oxide in covering relation relative to the top surface
of the conductive line; forming electrically insulative nitride
sidewall spacers over the conductive sidewall surfaces, the nitride
sidewall spacers projecting outwardly of the conductive line top
conductive surface, the electrically insulative oxide positioned
between the nitride sidewall spacers; forming an electrically
insulative layer outwardly of the conductive line and node
location; and etching a contact opening to the node location
through the electrically insulative layer, said etching being
substantially selective relative to the nitride sidewall
spacers.
45. A method for forming a contact opening, comprising: providing a
node location to which electrical connection is to be made; forming
a conductive line adjacent the node location, the conductive line
having conductive top and sidewall surfaces; forming a first
material over the conductive line top surface; forming electrically
insulative sidewall spacers of a second material over the
conductive sidewall surfaces, the sidewall spacers projecting
outwardly of the conductive line top surface, the first material
being received between the sidewall spacers; forming an
electrically insulative layer outwardly of the node location, first
material layer and second material sidewall spacers; and etching a
contact opening to the node location through the electrically
insulative layer substantially selectively relative to the second
material of the sidewall spacers.
46. A method as claimed in claim 45, wherein the first material
comprises substantially undoped oxide.
47. A method as claimed in claim 45, wherein the second material
comprises nitride.
48. A method for forming first and second contact openings,
comprising: providing a node location to which electrical
connection is to be made; forming a conductive line adjacent the
node location, the conductive line having conductive top and
sidewall surfaces; forming a first material layer over the
conductive line top surface; forming electrically insulative
sidewall spacers of a second material over the conductive sidewall
surfaces, the sidewall spacers projecting outwardly of the
conductive line top conductive surface, the electrically insulative
first material being formed between the sidewall spacers; forming
an electrically insulative layer outwardly of the node location,
first material insulative layer, and second material sidewall
spacers; and in the same masking step, etching a first contact
opening through the electrically insulative material to the node
location, and a second contact opening to the conductive line
conductive top surface, the etching being substantially selective
relative to the second material of the sidewall spacers.
49. A method as claimed in claim 48, wherein the first material is
polysilicon.
50. A method as claimed in claim 48, wherein the second material
comprises nitride.
51. A method as claimed in claim 48, wherein before etching the
first and second contact openings, etching the first material
selectively relative to the second material.
52. A method as claimed in claim 51, wherein after etching the
first material layer, and before etching the first and second
contact openings, forming a third layer of material over the
conductive line, and etching the third layer of material effective
to provide second spacers which are oriented in partial covering
relation relative to the top surface of the conductive line.
53. A method as claimed in claim 52, wherein the third layer of
material comprises nitride.
54. A method for forming a contact opening to an outer portion of a
conductive line comprising: forming a conductive material layer and
forming a sacrificial material layer thereover; patterning and
etching the conductive material layer and the sacrificial material
layer to form a conductive line having sacrificial material
thereover, the conductive line having top and sidewall surfaces,
the sacrificial material layer having sidewall surfaces which are
substantially aligned with the conductive line sidewall surfaces;
forming primary electrically insulative spacers over the conductive
line and sacrificial material layer sidewall surfaces; selectively
etching the sacrificial material from over the conductive line top
surface to form a void between the primary sidewall spacers and
over the outer portion of the conductive line; forming opposing
secondary electrically insulative sidewall spacers laterally
inwardly of the primary sidewall spacers, the opposing secondary
spacers disposed in partial covering relation relative to the outer
portion of the conductive lines; forming an electrically insulative
layer outwardly of the primary and secondary spacers, over the
conductive line and within the void; and etching a contact opening
to the outer portion of the electrically conductive line through
the electrically insulative layer, and substantially selective
relative to the primary and secondary sidewall spacers.
55. A method as claimed in claim 54, wherein the sacrificial
material layer comprises polysilicon.
56. A method as claimed in claim 54, wherein the primary and
secondary electrically insulative sidewall spacers comprise
nitride.
57. A method as claimed in claim 54, wherein the contact opening is
formed to the conductive line top surface.
58. A method as claimed in claim 54, wherein the conductive
material is formed atop a substrate having a node location, and
wherein the contact opening is formed to the conductive line top
surface, and a second contact opening is formed to the node
location.
59. A method for forming a contact opening to an outer portion of a
conductive line, comprising: forming a conductive line having top
and sidewall surfaces; forming primary electrically insulative
spacers over the conductive line sidewall surfaces, the primary
spacers projecting outwardly relative to the conductive line top
surface and forming a void therebetween; forming opposing secondary
electrically insulative spacers laterally inwardly of the primary
spacers, the opposing secondary electrically insulative spacers
disposed in partial covering relation relative to the outer portion
of the conductive line; forming an electrically insulative layer
outwardly of the primary and secondary spacers, over the conductive
line, and within the void; and etching a contact opening to the
outer portion of the electrically conductive line through the
electrically insulative layer, the etching conducted substantially
selectively relative to the primary and secondary spacers.
60. A method as claimed in claim 59, wherein the secondary
electrically insulative spacers are disposed in partial covering
relation relative to the top surface of the conductive line.
61. A method as claimed in claim 59, wherein the primary and
secondary spacers comprise nitride.
62. A method as claimed in claim 59, wherein the contact opening is
made to the top surface of the conductive line, and wherein the
conductive line is formed on a substrate which has a node location
which is adjacent to the conductive line, and wherein a second
contact opening is formed to the node location.
63. A method for forming first and second contact openings
comprising: providing a node location to which electrical
connection is to be made; forming a conductive line adjacent the
node location, the conductive line having top and sidewall
surfaces; forming primary electrically insulative spacers over the
conductive line sidewall surfaces, the primary spacers projecting
upwardly relative to the conductive line top surface and forming a
void therebetween; forming opposing secondary electrically
insulative spacers laterally inwardly of the primary spacers;
forming an electrically insulative layer outwardly of the primary
and secondary spacers and over the conductive line, within the
void, and over the node location; and in the same masking step,
etching a first contact opening through the electrically insulative
material to the node location, and a second contact opening to the
conductive line top surface, the etching being conducted
substantially selectively relative to the primary and secondary
spacers.
64. A method as claimed in claim 63, wherein the primary and
secondary spacers comprise nitride.
65. A method as claimed in claim 63, wherein the secondary spacers
are disposed in partial covering relation relative to the top
surface of the conductive line.
66. An electronic component comprising: a main body having
sidewalls and a top surface; a primary electrically insulative
spacer of a first material disposed in substantially covering
relation relative to one of the sidewalls of the electronic
component, the primary electrically insulative spacer extending
above the top surface of the electronic component; and a secondary
electrically insulative spacer positioned laterally inwardly
relative to the primary electrically insulative spacer, the
secondary electrically insulative spacer disposed in partial
covering relation relative to the top surface of the electronic
component.
67. An electronic component as claimed in claim 66, wherein the
primary and secondary electrically insulative spacers comprise
nitride.
68. An electronic component as claimed in claim 66, wherein the
main body has opposite sidewalls, and wherein the individual
primary electrically insulative spacers are positioned on the
opposing sidewalls, and wherein a void is defined between the
primary electrically insulative spacers.
69. An electronic component as claimed in claim 66, wherein
electrical contact is made to the top surface of the electronic
component.
70. An electronic component as claimed in claim 66, wherein the
electronic component is oriented adjacent a node location, and
wherein electrical contact is made to the top surface of the
electrical component, and the node location.
Description
TECHNICAL FIELD
[0001] This invention relates generally to a method of forming
contact openings and to electronic components formed from the same
and other methods.
BACKGROUND OF THE INVENTION
[0002] As various electronic components such as DRAMS have
increased in memory cell density, designers face a continuous
challenge to provide contact openings to predetermined node
locations, and to the top surface of conductive lines.
[0003] Heretofore, so-called self-aligned contact openings are
provided to node locations which are adjacent to wordlines, by
first encapsulating the wordline in nitride spacers, and providing
a nitride cap thereover. Once this is achieved, a silicon dioxide
layer in the form of BPSG, is provided over the encapsulated
wordline. Following the provision of the layer of BPSG, the contact
opening is etched. In view of perceived shortcomings in the prior
art techniques, the patterning and etching of the contact openings
through the layer of BPSG to the node location, can be somewhat
misaligned. To address this problem, an etching chemistry is
provided which is selective to nitride and therefore the etching
will stop on the nitride material which encapsulates the
wordline.
[0004] In addition to the foregoing, the fabrication of certain
electronic components may require that contact openings be made to
both the top surface of the respective wordlines and to substrate
areas adjacent thereto. To make electrical contact to the top
surface of wordlines, the prior art techniques have typically
included separate photo patterning, and etching steps. The present
method provides a convenient means by which contact openings to the
top surface of the wordline, and adjacent node location can be
provided in a single photo masking and etching step.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Preferred embodiments of the invention are described below
with reference to the following accompanying drawings.
[0006] FIG. 1 is a diagrammatic section of a semiconductor wafer
shown at one processing step in accordance with the present
invention.
[0007] FIG. 2 is a diagrammatic section of the FIG. 1 wafer
illustrated at a processing step subsequent to that shown by FIG.
1.
[0008] FIG. 3 is a diagrammatic section of the FIG. 1 wafer
illustrated at a processing step subsequent to that shown by FIG.
2.
[0009] FIG. 4 is a diagrammatic section of the FIG. 1 wafer
illustrated at a processing step subsequent to that shown by FIG.
3.
[0010] FIG. 5 is a diagrammatic section of the FIG. 1 wafer
illustrated at a processing step subsequent to that shown by FIG.
4.
[0011] FIG. 6 is a diagrammatic section of the FIG. 1 wafer taken
through a different plane from that depicted by FIGS. 1-5, and
corresponds in sequence to the processing depicted by FIG. 5.
[0012] FIG. 7 is a diagrammatic section of the FIG. 1 wafer
illustrated at an alternate processing step subsequent to that
shown in FIG. 1.
[0013] FIG. 8 is a diagrammatic section of the FIG. 1 wafer
illustrated at an alternative processing step subsequent to that
shown in FIG. 1.
SUMMARY OF THE INVENTION
[0014] The invention provides methods for forming a contact opening
to the top surface of an electronic component, and an adjacent node
location in the same masking step, as well as an electronic
component formed from the same methods.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0015] This disclosure of the invention is submitted in furtherance
of the constitutional purposes of the U.S. Patent Laws "to promote
the progress of science and useful arts" (Article 1, Section
8).
[0016] Preferred embodiments of the present invention are
collectively shown by the accompanying drawings as will become
apparent from the continuing discussion.
[0017] Referring first to FIG. 1, a semiconductive wafer in process
is indicated generally by reference to numeral 10. An electronic
component or conductive line 12 having a main body 13 is provided,
as shown. The electronic component or conductive line 12 is
positioned over a gate oxide layer 14. The electronic component 12
includes a layer of conductive material 16, which is provided over
the gate layer 14, and which comprises polysilicon. A tungsten
silicide layer 18 is provided over the polysilicon layer 16. The
tungsten silicide layer has an outwardly facing surface 20 which
forms the top of the conductive line or electronic component 12.
The conductive line or electronic component 12, as provided, has a
given photomasking target area identified by the line labeled
25.
[0018] An oxide layer 30 is formed over the top or outwardly facing
surface 20 of the conductive line of electronic component 12. Still
further, a node location 40 in the form of a diffusion region is
provided adjacent the conductive line or electronic component 12.
The node location may comprise LDD implants or boron halo implants
which are not shown. As will be recognized, the node locations 40
has a given target area identified by the line labeled 45.
[0019] A disposable, sacrificial, first material layer 50
preferably comprising polysilicon is formed over the oxide layer
30. Still further, an optional layer of nitride 60 having a
thickness of approximately 100 Angstroms is formed over the
disposable, sacrificial, first material layer. The nitride layer 60
serves to protect the underlying sacrificial first material layer
from oxidation during reoxidation of the adjacent node location 40.
Each of the respective layers 16, 18, 30, and 50, have
substantially coplanar sidewalls 70.
[0020] Referring now to FIG. 2, a first pair of electrically
insulative anisotropically etched nitride spacers 80 are formed in
covering relation relative to the sidewalls 70. The insulative
spacers 80 have a portion 81 which is disposed outwardly relative
to the top surface 20 of the conductive line or electronic
component 12. The sacrificial, or first material layer 50 is
disposed in covering relation relative to the top surface 20 of the
electronic component 12, and is further positioned between the
first pair of insulative spacers 80.
[0021] Referring now to FIG. 3, the conductive line or electronic
component 12 is shown following the selective removal or etching of
the sacrificial, or first layer of material 50. The selective
etching of the sacrificial layer 50 results in an elevational void
90 being formed, or otherwise defmed between the first pair of
nitride spacers 80.
[0022] Referring now to FIG. 4, the conductive line or electronic
component 12 is shown following the provision of a second nitride
layer, which has been subsequently selectively etched to provide
secondary, electrically insulative spacers 100. The secondary
spacers 100 are disposed, on the one hand, in opposing covering
relation relative to the top surface 20; and on the other hand in
partial covering relation relative to the first pair of nitride
spacers 80, and the underlying semiconductor wafer 10. The
secondary nitride spacers 100 include a first pair of nitride
spacers 101, which are disposed laterally, outwardly relative to
the first pair of nitride spacers 80; and a second pair of nitride
spacers 102, which are disposed in partial covering relation
relative to the top surface 20 of the conductive line 12, and
laterally inwardly relative to the first pair of nitride spacers
80. Following the provisions of the secondary spacers 100, optional
n.sup.+and p.sup.+implants can be provided if desired. Further, it
will be seen by a study of FIGS. 1 and 4, that the provision of the
secondary nitride spacers 102 increases the mask misalignment area
for hitting the node location 40 by the width of spacers 102. It
will be recognized, therefore, that misalignment of a subsequent
mask for making contact to the node location 40 in a dimension of
less than or equal to the dimension of the width of spacers 102,
will not result in making electrical contact to the underlying
electronic component 12. Further, it will also be recognized that
the secondary nitride spacers 101 provide an analogous added mask
misalignment dimension equal to the width of spacers 101 when
targeting for the top surface 20.
[0023] Referring now to FIGS. 5, and 6, a second layer of
insulative material 120, preferably comprising BPSG, is provided in
covering relation relative to the electronic component 12, and the
underlying semiconductor wafer 10. FIGS. 5 and 6 are different
parallel plane cross-sectional cuts. Following the provision of the
insulative layer 120, and in the same masking step, first and
second contact openings 132 and 130 are provided, as desired, to
the node location 40 (FIG. 5), and to the top surface 20 of the
conductive line 12 respectively (FIG. 6). As shown and discussed
above, the provision of the secondary nitride spacers 101 and 102
allows for some misalignment of the respective contact openings 130
and 132 to the underlying node location 40 or top surface 20.
Following the provision of the individual contact openings 130 and
132, electrically conductive material 134 is provided therein.
[0024] As seen in FIG. 6, therefore, the present method for forming
a contact opening 130 to an electronic component 12 includes
forming an electronic component 12, having a top surface 20;
forming an electrically insulative spacer 102 in partial covering
relation relative to the top surface 20; forming an insulating
layer 120 over the spacer 102 and top surface 20; and selectively
etching the insulative layer 120 relative to the spacer 102 to form
a contact opening to the electronic component top surface 20.
[0025] Referring now to FIGS. 7 and 8, a second alternate form of
the invention is shown. FIG. 7 illustrates a misalignment of a
contact mask to a node location, whereas FIG. 8 illustrates
undesired misalignment but which is not as onerous as shown in FIG.
7. In particular, the second form of the invention, as seen in FIG.
7, includes a semiconductor wafer in process 10 and a conductive
line or electronic component 12 positioned thereon. The conductive
line or electronic component 12 has a construction similar to that
earlier disclosed. More precisely, the electronic component 12
comprises a polysilicon layer 16 which is formed outwardly of a
gate oxide layer 14. Further, a tungsten silicide layer 18 is
formed over the polysilicon layer 16. The conductive line or
electronic component 12 has a top surface 20, and sidewalls 70.
[0026] A layer of nitride is formed over the conductive line 12,
and is subsequently, anisotropically etched to form the resulting
nitride sidewall 140 spacers. The electrically insulative nitride
sidewall spacers 140 are formed over the conductive sidewall
surface 70 and project outwardly of the conductive line top
conductive surface 20. The resulting nitride sidewall spacers 140
define an elevational void 142 therebetween. A layer of oxide 144
(preferably Novellas or produced from decomposition of TEOS) is
then formed over the top surface 20 of the electronic component and
between the pair of nitride sidewall spacers 140 within void 142.
An electrically insulative layer 146, preferably comprising BPSG,
is formed outwardly of the conductive line 12 and over the adjacent
node location 40. Thereafter, in the same masking step, a contact
opening 148 is formed through the electrically insulative layer.
The etching chemistry employed is selective relative to the nitride
sidewall spacers 140. The etching chemistry employed (RIE) results
in a lag time in the etch of material 144, thereby permitting
misalignment of the mask. Therefore, electrical contact to the top
surface 20 of the underlying conductive line 12 is avoided.
[0027] Accordingly, a method for forming a contact opening 148 of
the present invention comprises providing a node location 40 to
which electrical connection is to be made; forming a conductive
line 12 adjacent the node location 40, the conductive line 12
having top 20 and sidewall surfaces 70; forming an electrically
insulative oxide 144 in covering relation relative to the top
surface 20 of the conductive line 12; forming electrically
insulative nitride sidewall spacers 140 over the conductive
sidewall surfaces 70; the nitride sidewall spacers 140 projecting
outwardly of the conductive line top conductive surface 20, the
electrically insulative oxide 144 positioned between the nitride
sidewall spacers 140; forming an electrically insulative layer 146
outwardly of the conductive line 12, and node location 40; and
etching a contact opening 148 to the node location 40 through the
electrically insulative layer 146 substantially selective relative
to the nitride sidewall spacers 140. As seen in FIGS. 5 through 8,
the method of the present invention provides a convenient means for
making contact openings, in the same masking step, to both the node
location 40, and the top surface 20 of the electronic component
11.
[0028] Still fuirther, the method of the prevent invention results
in an electronic component 12 comprising a main body 13 having
sidewalls 70, and a top surface 20; a primary electrically
insulative spacer 80 of a first material disposed in substantially
covering relation relative to one of the sidewalls 70 of the
electronic component 12, the primary electrically insulative spacer
extending above the top surface 20 of the electronic component; and
a secondary electrically insulative spacer 102 formed laterally
inwardly relative to the primary electrically insulative spacer 80,
the secondary insulative spacer 102 disposed in partial covering
relation relative to the top surface 20 of the electronic component
12.
[0029] The invention as disclosed above is believed to be readily
apparent and is briefly summarized at this point.
[0030] One aspect of the present invention relates to a method for
forming first and second contact openings, comprising:
[0031] providing an electronic component 12 having a top surface 20
on a semiconductive substrate 10, the semiconductive substrate 10
having a node location 40 to which electrical contact is to be
made;
[0032] forming a layer of insulative material 120 in covering
relation relative to the electronic component 12; and
[0033] in the same masking step, forming the first contact opening
132 through the layer of insulative material 120 to the top surface
20 of the electronic component 12, and the second contact opening
130 through the layer of insulative material 120 to the node
location 40.
[0034] In accordance with another aspect of the present invention,
a method for forming first and second contact openings
comprises:
[0035] providing an electronic component 12 on a semiconductive
substrate 10, the electronic component 12 having a sidewall 70 and
a top surface 20, and the semiconductive substrate having a node
location 40 to which electrical contact is to be made;
[0036] forming an insulative spacer 80 on the sidewall 70 of the
electronic component 12, the insulative spacer 80 having a portion
81 which is disposed outwardly relative to the top surface 20 of
the electronic component 12;
[0037] forming a first layer of material 50 in covering relation
relative to the top surface 20 of the electronic component 12;
[0038] forming a second layer of insulative material 120 in
covering relation relative to the electronic component 12 and the
semiconductive substrate 10; and
[0039] in the same masking step, forming the first contact opening
132 through the second layer of material 120 to the top surface 20
of the electronic component 12 and the second contact opening 130
through the second layer of material 120 to the node location
40.
[0040] Yet still another aspect of the present invention relates to
a method for forming a contact opening comprising:
[0041] providing a node location 40 on a semiconductive substrate
10 to which electrical contact is to be made;
[0042] forming an electronic component 12 on the semiconductive
substrate 10 adjacent to the node location 40, the electronic
component 12 having sidewaUs 70 and a top surface 20;
[0043] forming a first spacer 80 on at least one of the sidewalls
70 of the electronic component 12;
[0044] forming a second spacer 100 in partial covering relation
relative to the top surface 20 of the electronic component 12;
[0045] forming an insulative layer of material 120 over the
electronic component 12, the first and second spacers 80 and 100
and the node location 40; and
[0046] selectively removing the insulative layer 120 relative to
the first and second spacers 80 and 100 to form a contact opening
130 or 132 to the node location 40, or the top surface 20 of the
electronic component 12.
[0047] Still another aspect of the present invention relates to a
method for forming a contact opening comprising:
[0048] providing a node location 40 on a substrate 10 to which
electrical contact is to be made;
[0049] providing an electronic component 12 on the substrate 10,
and adjacent the node location 40, the electronic component 12
having sidewalls 70 and an electrically conductive top surface
20;
[0050] forming a first spacer 80 on at least one of the sidewalls
70 of the electronic component 12;
[0051] forming a second spacer 100 in partial covering relation
relative to the top surface 20 of the electronic component 12;
[0052] forming an insulative layer of material 120 over the
electronic component 12, the first and second spacers 80 and 100
and the node location 40; and
[0053] selectively removing the insulative layer 120 relative to
the first and second spacers 80 and 100 to form a contact opening
132 to the electrically conductive top surface 20 of the electronic
component 12.
[0054] Another aspect of the present invention relates to a method
for forming a contact opening to an electronic component 12,
comprising:
[0055] providing an electronic component 12 having a top surface
20;
[0056] providing an electrically insulative spacer 100 in partial
covering relation relative to the top surface 20;
[0057] providing an insulating layer 120 over the spacer 100 and
the top surface 20; and
[0058] selectively removing the insulative layer 120 relative to
the spacer 100 to form a contact opening 132 to the electronic
component 12 top surface 20.
[0059] Still a further aspect of the present invention relates to a
method for forming first and second contact openings
comprising:
[0060] providing a node location 40 to which electrical connection
is to be made;
[0061] forming a conductive line 12 adjacent the node location 40,
the conductive line 12 having conductive top 20 and sidewall
surfaces 70;
[0062] forming a first material layer 50 over the conductive line
12 top surface 10;
[0063] forming electrically insulative sidewall spacers 80 of a
second material over the conductive sidewall surfaces 70, the
sidewall spacers 70 projecting outwardly of the conductive line 12
top surface 20, the electrically insulative first material 50 being
provided between the sidewall spacers;
[0064] forming an electrically insulative layer 120 outwardly of
the node location 40, the first material insulative layer 50, and
second material sidewall spacers 80; and
[0065] in the same masking step, etching a first contact opening
130 through the electrically insulative layer to the node location
40, and a second contact opening 132 to the conductive line
conductive top surface 20, the etching being substantially
selective relative to the second material of the sidewall spacers
80.
[0066] Yet still another aspect of the present invention relates to
an electronic component comprising:
[0067] a main body 12 having sidewalls 70 and a top surface 20;
[0068] a primary electrically insulative spacer 80 of a first
material disposed in substantially covering relation relative to
one of the sidewalls 70 of the electronic component 12, the primary
electrically insulative spacer 80 extending above the top surface
of the electronic component 12; and
[0069] a secondary electrically insulative spacer 100 provided
laterally inwardly relative to the primary electrically insulative
spacer 80, the secondary electrically insulative spacer 100
disposed in partial covering relation relative to the top surface
20 of the electronic component 12.
[0070] In compliance with the statute, the invention has been
described in language more or less specific as to structural and
methodical features. It is to be understood, however, that the
invention is not limited to the specific features shown and
described, since the means herein disclosed comprise preferred
forms of putting the invention into effect. The invention is,
therefore, claimed in any of its forms or modifications within the
proper scope of the appended claims appropriately interpreted in
accordance with the Doctrine of Equivalents.
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