U.S. patent application number 09/757066 was filed with the patent office on 2001-05-10 for system, ic chip, on-chip test structure, and corresponding method for modeling one or more target interconnect capacitances.
This patent application is currently assigned to BTA TECHNOLOGY, INC.. Invention is credited to Chen, James C..
Application Number | 20010000948 09/757066 |
Document ID | / |
Family ID | 22930811 |
Filed Date | 2001-05-10 |
United States Patent
Application |
20010000948 |
Kind Code |
A1 |
Chen, James C. |
May 10, 2001 |
System, IC chip, on-chip test structure, and corresponding method
for modeling one or more target interconnect capacitances
Abstract
A system, an IC chip, a test structure formed on the IC chip,
and a corresponding method for modeling one or more target
interconnect capacitances is disclosed. The test structure
comprises an interconnect configuration comprising a test
interconnect and one or more target interconnects. The interconnect
configuration has, for each target interconnect, a corresponding
target interconnect capacitance between the test interconnect and
the target interconnect. The test structure also comprises a test
interconnect charging circuit connected to the test interconnect.
The test interconnect charging circuit is configured to place a
test charge on the test interconnect. The test structure further
comprises one or more target interconnect charging circuits. Each
target interconnect charging circuit is connected to a
corresponding target interconnect. Each target interconnect
charging circuit is configured to draw a target interconnect
charging current from the corresponding target interconnect in
response to the test charge. This places an opposite charge on the
corresponding target interconnect that is induced by the
corresponding target interconnect capacitance. As a result, a
measurement of the corresponding target interconnect capacitance
may be computed by making a measurement of the target interconnect
charging current with a current meter of the system.
Inventors: |
Chen, James C.; (Foster
City, CA) |
Correspondence
Address: |
Steven M. Freeland
FLEHR HOHBACH TEST ALBRITTON & HERBERT LLP
Suite 3400
Four Embarcadero Center
San Francisco
CA
94111-4187
US
|
Assignee: |
BTA TECHNOLOGY, INC.
|
Family ID: |
22930811 |
Appl. No.: |
09/757066 |
Filed: |
January 8, 2001 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09757066 |
Jan 8, 2001 |
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09246469 |
Feb 9, 1999 |
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Current U.S.
Class: |
324/750.3 |
Current CPC
Class: |
G01R 31/2884 20130101;
G01R 31/3004 20130101 |
Class at
Publication: |
324/763 |
International
Class: |
G01R 031/02 |
Claims
What is claimed is:
1. A test structure formed on an IC chip for modeling a target
interconnect capacitance, the test structure comprising: an
interconnect configuration formed on the IC chip and comprising a
test interconnect and a target interconnect, the interconnect
configuration having the target interconnect capacitance between
the test and target interconnects; a test interconnect charging
circuit formed on the IC chip and connected to the test
interconnect, the test interconnect charging circuit being
configured to place a test charge on the test interconnect; and a
target interconnect charging circuit formed on the IC chip and
connected to the target interconnect, the target interconnect
charging circuit being configured to draw a target interconnect
charging current from the target interconnect in response to the
test charge to place an opposite charge on the target interconnect
that is induced by the target interconnect capacitance, whereby a
measurement of the target interconnect capacitance may be computed
from a measurement of the target interconnect charging current.
2. The test structure of claim 1 wherein the test interconnect
charging circuit is further configured to draw a test interconnect
charging current to the test interconnect to place the test charge
on the test interconnect.
3. The test structure of claim 2 wherein: the test structure has
reset and measure phases of operation; the test interconnect
charging circuit is further configured to draw a test interconnect
discharging current from the test interconnect during the reset
phase to remove any pre-existing charge on the test interconnect
and draw the test interconnect charging current to the test
interconnect during the measure phase; and the target interconnect
charging circuit is further configured to draw a target
interconnect discharging current to the target interconnect during
the reset phase to remove any pre-existing charge on the target
interconnect and draw the target interconnect charging current from
the target interconnect during the measure phase.
4. The test structure of claim 3 wherein: the test interconnect
charging circuit is further configured to be responsive to test
interconnect charge and discharging control signals such that: in
the reset phase, the test interconnect discharging current is drawn
when the test interconnect charge and discharging control signals
respectively indicate that charging is not to occur and discharging
is to occur; in the measure phase the test interconnect charging
current is drawn when the test interconnect charge and discharging
control signals respectively indicate that charging is to occur and
discharging is not to occur; and the target interconnect charging
circuit is further configured to be responsive to target
interconnect charge and discharging control signals such that: in
the reset phase, the target interconnect discharging current is
drawn when the target interconnect charge and discharging control
signals respectively indicate that charging is not to occur and
discharging is to occur; and in the measure phase, the target
interconnect charging current is drawn when the target interconnect
charge and discharging control signals respectively indicate that
charging is to occur and discharging is not to occur.
5. The test structure of claim 4 wherein the target interconnect
charging circuit comprises first and second transistors connected
to the target interconnect and configured to be respectively
responsive to the target interconnect charge and discharging
control signals such that: in the reset phase, the first and second
transistors are respectively turned on and off when the target
interconnect charge and discharging control signals respectively
indicate that charging is to occur and discharging is not to occur
so as to draw the target interconnect charging current; in the
measure phase, the first and second transistors are respectively
turned off and on when the target interconnect charge and
discharging control signals respectively indicate that charging is
not to occur and discharging is to occur so as to draw the target
interconnect discharging current.
6. The test structure of claim 5 wherein the test interconnect
charging circuit comprises third and fourth transistors connected
to the test interconnect and configured to be respectively
responsive to the test interconnect charge and discharging control
signals such that: in the reset phase, the third and fourth
transistors are respectively turned on and off when the test
interconnect charge and discharging control signals respectively
indicate that charging is to occur and discharging is not to occur
so as to draw the test interconnect charging current; and in the
measure phase, the third and fourth transistors are respectively
turned off and on when the test interconnect charge and discharging
control signals respectively indicate that charging is not to occur
and discharging is to occur so as to draw the test interconnect
discharging current.
7. The test structure of claim 4 further comprising a control
signal generator formed on the IC chip and configured to generate
the test and target interconnect charging and discharging control
signals, the control signal generator being connected to the test
and target interconnect charging circuits to provide the test and
target interconnect charging and discharging control signals
thereto.
8. The test structure of claim 7 wherein the control signal
generator comrpises a frequency divider to divide the frequency of
a selected control signal of the test and target interconnect
charging and discharging control signals by a pre-selected factor
to generate a frequency divided signal, whereby the measurement of
the target capacitance may further be computed from a measurement
of the frequency of the frequency divided signal and the
pre-selected factor.
9. A test structure formed on an IC chip for modeling one or more
target interconnect capacitances, the test structure comprising: an
interconnect configuration formed on the IC chip and comprising a
test interconnect and one or more target interconnects, the
interconnect configuration having, for each target interconnect, a
corresponding target interconnect capacitance between the test
interconnect and the target interconnect; a test interconnect
charging circuit formed on the IC chip and connected to the test
interconnect, the test interconnect charging circuit being
configured to place a test charge on the test interconnect; and one
or more target interconnect charging circuits, each target
interconnect charging circuit being formed on the IC chip and
connected to a corresponding target interconnect, each target
interconnect charging circuit being configured to draw a target
interconnect charging current from the corresponding target
interconnect in response to the test charge to place an opposite
charge on the corresponding target interconnect that is induced by
the corresponding target interconnect capacitance, whereby a
measurement of the corresponding target interconnect capacitance
may be computed from a measurement of the target interconnect
charging current.
10. The test structure of claim 9 wherein the test interconnect
charging circuit is further configured to draw a test interconnect
charging current to the test interconnect to place the test charge
on the test interconnect.
11. The test structure of claim 10 wherein: the test structure has
reset and measure phases of operation; the test interconnect
charging circuit is further configured to draw a test interconnect
discharging current from the test interconnect during the reset
phase to remove any pre-existing charge on the test interconnect
and draw the test interconnect charging current to the test
interconnect during the measure phase; and each target interconnect
charging circuit is further configured to draw a target
interconnect discharging current to the corresponding target
interconnect during the reset phase to remove any pre-existing
charge on the corresponding target interconnect and draw the target
interconnect charging current from the corresponding target
interconnect during the measure phase.
12. The test structure of claim 11 wherein: the test interconnect
charging circuit is further configured to be responsive to test
interconnect charge and discharging control signals such that: in
the reset phase, the test interconnect discharging current is drawn
when the test interconnect charge and discharging control signals
respectively indicate that charging is not to occur and discharging
is to occur; in the measure phase the test interconnect charging
current is drawn when the test interconnect charge and discharging
control signals respectively indicate that charging is to occur and
discharging is not to occur; and each target interconnect charging
circuit is further configured to be responsive to target
interconnect charge and discharging control signals such that: in
the reset phase, the target interconnect discharging current is
drawn when the target interconnect charge and discharging control
signals respectively indicate that charging is not to occur and
discharging is to occur; and in the measure phase, the target
interconnect charging current is drawn when the target interconnect
charge and discharging control signals respectively indicate that
charging is to occur and discharging is not to occur.
13. The test structure of claim 12 wherein each target interconnect
charging circuit comprises first and second transistors connected
to the corresponding target interconnect and configured to be
respectively responsive to the target interconnect charge and
discharging control signals such that: in the reset phase, the
first and second transistors are respectively turned on and off
when the target interconnect charge and discharging control signals
respectively indicate that charging is to occur and discharging is
not to occur so as to draw the target interconnect charging
current; in the measure phase, the first and second transistors are
respectively turned off and on when the target interconnect charge
and discharging control signals respectively indicate that charging
is not to occur and discharging is to occur so as to draw the
target interconnect discharging current.
14. The test structure of claim 13 wherein the test interconnect
charging circuit comprises third and fourth transistors connected
to the test interconnect and configured to be respectively
responsive to the test interconnect charge and discharging control
signals such that: in the reset phase, the third and fourth
transistors are respectively turned on and off when the test
interconnect charge and discharging control signals respectively
indicate that charging is to occur and discharging is not to occur
so as to draw the test interconnect charging current; and in the
measure phase, the third and fourth transistors are respectively
turned off and on when the test interconnect charge and discharging
control signals respectively indicate that charging is not to occur
and discharging is to occur so as to draw the test interconnect
discharging current.
15. The test structure of claim 12 further comprising a control
signal generator formed on the IC chip and configured to generate
the test and target interconnect charging and discharging control
signals, the control signal generator being connected to the test
and one or more target interconnect charging circuits to provide
the test and target interconnect charging and discharging control
signals thereto.
16. The test structure of claim 15 wherein the control signal
generator comrpises a frequency divider to divide the frequency of
a selected control signal of the of the test and target
interconnect charging and discharging control signals by a
pre-selected factor to generate a frequency divided signal, whereby
the measurement of the target capacitance may further be computed
from a measurement of the frequency of the frequency divided signal
and the pre-selected factor.
17. An IC chip comprising a test structure formed on the IC chip
for modeling a target interconnect capacitance, the test structure
comprising: an interconnect configuration formed on the IC chip and
comprising a test interconnect and a target interconnect, the
interconnect configuration having the target interconnect
capacitance between the test and target interconnects; a test
interconnect charging circuit formed on the IC chip and connected
to the test interconnect, the test interconnect charging circuit
being configured to place a test charge on the test interconnect;
and a target interconnect charging circuit formed on the IC chip
and connected to the target interconnect, the target interconnect
charging circuit being configured to draw a target interconnect
charging current from the target interconnect in response to the
test charge to place an opposite charge on the target interconnect
that is induced by the target interconnect capacitance, whereby a
measurement of the target interconnect capacitance may be computed
from a measurement of the target interconnect charging current.
18. The IC chip of claim 17 further comprising an IC formed on the
IC chip that includes an interconnect configuration that is the
same as the interconnect configuration of the test structure.
19. The IC chip of claim 17 wherein the test interconnect charging
circuit is further configured to draw a test interconnect charging
current to the test interconnect to place the test charge on the
test interconnect.
20. The IC chip of claim 19 wherein: the test structure has reset
and measure phases of operation; the test interconnect charging
circuit is further configured to draw a test interconnect
discharging current from the test interconnect during the reset
phase to remove any pre-existing charge on the test interconnect
and draw the test interconnect charging current to the test
interconnect during the measure phase; and the target interconnect
charging circuit is further configured to draw a target
interconnect discharging current to the target interconnect during
the reset phase to remove any pre-existing charge on the target
interconnect and draw the target interconnect charging current from
the target interconnect during the measure phase.
21. The IC chip of claim 20 wherein: the test interconnect charging
circuit is further configured to be responsive to test interconnect
charge and discharging control signals such that: in the reset
phase, the test interconnect discharging current is drawn when the
test interconnect charge and discharging control signals
respectively indicate that charging is not to occur and discharging
is to occur; in the measure phase the test interconnect charging
current is drawn when the test interconnect charge and discharging
control signals respectively indicate that charging is to occur and
discharging is not to occur; and the target interconnect charging
circuit is further configured to be responsive to target
interconnect charge and discharging control signals such that: in
the reset phase, the target interconnect discharging current is
drawn when the target interconnect charge and discharging control
signals respectively indicate that charging is not to occur and
discharging is to occur; and in the measure phase, the target
interconnect charging current is drawn when the target interconnect
charge and discharging control signals respectively indicate that
charging is to occur and discharging is not to occur.
22. The IC chip of claim 21 wherein the target interconnect
charging circuit comprises first and second transistors connected
to the target interconnect and configured to be respectively
responsive to the target interconnect charge and discharging
control signals such that: in the reset phase, the first and second
transistors are respectively turned on and off when the target
interconnect charge and discharging control signals respectively
indicate that charging is to occur and discharging is not to occur
so as to draw the target interconnect charging current; in the
measure phase, the first and second transistors are respectively
turned off and on when the target interconnect charge and
discharging control signals respectively indicate that charging is
not to occur and discharging is to occur so as to draw the target
interconnect discharging current.
23. The IC chip of claim 22 wherein the test interconnect charging
circuit comprises third and fourth transistors connected to the
test interconnect and configured to be respectively responsive to
the test interconnect charge and discharging control signals such
that: in the reset phase, the third and fourth transistors are
respectively turned on and off when the test interconnect charge
and discharging control signals respectively indicate that charging
is to occur and discharging is not to occur so as to draw the test
interconnect charging current; and in the measure phase, the third
and fourth transistors are respectively turned off and on when the
test interconnect charge and discharging control signals
respectively indicate that charging is not to occur and discharging
is to occur so as to draw the test interconnect discharging
current.
24. The IC chip of claim 21 further comprising a control signal
generator formed on the IC chip and configured to generate the test
and target interconnect charging and discharging control signals,
the control signal generator being connected to the test and target
interconnect charging circuits to provide the test and target
interconnect charging and discharging control signals thereto.
25. The IC chip of claim 24 wherein the control signal generator
comrpises a frequency divider to divide the frequency of a selected
control signal of the test and target interconnect charging and
discharging control signals by a pre-selected factor to generate a
frequency divided signal, whereby the measurement of the target
capacitance may further be computed from a measurement of the
frequency of the frequency divided signal and the pre-selected
factor.
26. A method of modeling a target interconnect capacitance with a
test structure formed on an IC chip, the test structure comprising
an interconnect configuration with a test interconnect and a target
interconnect, the target interconnect capacitance existing between
the test and target interconnects, the method comprising the steps
of: placing a test charge on the test interconnect; drawing a
target interconnect charging current from the target interconnect
in response to the test charge to place an opposite charge on the
target interconnect that is induced by the target interconnect
capacitance; and making a measurement of the target interconnect
charging current, whereby a measurement of the target interconnect
capacitance may be computed from the measurement of the target
interconnect charging current.
27. The method of claim 26 wherein the test charge placing step
comprises the step of drawing a test interconnect charging current
to the test interconnect to place the test charge on the test
interconnect.
28. The method of claim 27 wherein: the test structure has reset
and measure phases of operation; the steps of drawing the test and
target interconnect charging currents occur during the measure
phase; the method further comprises the steps of: drawing a test
interconnect discharging current from the test interconnect during
the reset phase to remove any pre-existing charge on the test
interconnect; and draw a target interconnect discharging current to
the target interconnect during the reset phase to remove any
pre-existing charge on the target interconnect.
29. The method of claim 28 further comprising the step of:
generating test interconnect charge and discharging control signals
and target interconnect charge and discharging control signals; the
step of drawing the test interconnect discharging current occurring
during the reset phase when the test interconnect charge and
discharging control signals respectively indicate that charging is
not to occur and discharging is to occur; the step of drawing the
target interconnect discharging current occurring during the reset
phase when the target interconnect charge and discharging control
signals respectively indicate that charging is not to occur and
discharging is to occur; the step of drawing the test interconnect
charging current occurring during the measure phase when the test
interconnect charge and discharging control signals respectively
indicate that charging is to occur and discharging is not to occur;
the step of drawing the target interconnect charging current
occurring during the measure phase when the target interconnect
charge and discharging control signals respectively indicate that
charging is to occur and discharging is not to occur.
30. The method of claim 29 further comprising the steps of:
dividing the frequency of a selected control signal of the test and
target interconnect charging and discharging control signals by a
pre-selected factor to generate a frequency divided signal; and
making a measurement of the frequency of the frequency divided
signal, whereby the measurement of the target capacitance may
further be computed from the measurement of the frequency and the
pre-selected factor.
31. A system for modeling a target interconnect capacitance, the
system comprising: a test structure formed on an IC chip
comprising: an interconnect configuration formed on the IC chip and
comprising a test interconnect and a target interconnect, the
interconnect configuration having the target interconnect
capacitance between the test and target interconnects; a test
interconnect charging circuit formed on the IC chip and connected
to the test interconnect, the test interconnect charging circuit
being configured to place a test charge on the test interconnect;
and a target interconnect charging circuit formed on the IC chip
and connected to the target interconnect, the target interconnect
charging circuit being configured to draw a target interconnect
charging current from the target interconnect in response to the
test charge to place an opposite charge on the target interconnect
that is induced by the target interconnect capacitance; a current
meter connected to the target interconnect charging circuit and
configured to make a measurement of the target interconnect
charging current, whereby a measurement of the target interconnect
capacitance may be computed from the measurement of the target
interconnect charging current.
32. The system of claim 31 wherein the test interconnect charging
circuit is further configured to draw a test interconnect charging
current to the test interconnect to place the test charge on the
test interconnect.
33. The system of claim 32 wherein: the test structure has reset
and measure phases of operation; the test interconnect charging
circuit is further configured to draw a test interconnect
discharging current from the test interconnect during the reset
phase to remove any pre-existing charge on the test interconnect
and draw the test interconnect charging current to the test
interconnect during the measure phase; and the target interconnect
charging circuit is further configured to draw a target
interconnect discharging current to the target interconnect during
the reset phase to remove any pre-existing charge on the target
interconnect and draw the target interconnect charging current from
the target interconnect during the measure phase.
34. The system of claim 33 farther comprising: a control signal
generator to generate test interconnect charge and discharging
control signals and target interconnect charge and discharging
control signals; the test interconnect charging circuit being
connected to the control signal generator and further configured to
be responsive to the test interconnect charge and discharging
control signals such that: in the reset phase, the test
interconnect discharging current is drawn when the test
interconnect charge and discharging control signals respectively
indicate that charging is not to occur and discharging is to occur;
in the measure phase the test interconnect charging current is
drawn when the test interconnect charge and discharging control
signals respectively indicate that charging is to occur and
discharging is not to occur; and the target interconnect charging
circuit being connected to the control signal generator and further
configured to be responsive to the target interconnect charge and
discharging control signals such that: in the reset phase, the
target interconnect discharging current is drawn when the target
interconnect charge and discharging control signals respectively
indicate that charging is not to occur and discharging is to occur;
and in the measure phase, the target interconnect charging current
is drawn when the target interconnect charge and discharging
control signals respectively indicate that charging is to occur and
discharging is not to occur.
35. The system of claim 34 wherein the target interconnect charging
circuit comprises first and second transistors connected to the
target interconnect and configured to be respectively responsive to
the target interconnect charge and discharging control signals such
that: in the reset phase, the first and second transistors are
respectively turned on and off when the target interconnect charge
and discharging control signals respectively indicate that charging
is to occur and discharging is not to occur so as to draw the
target interconnect charging current; in the measure phase, the
first and second transistors are respectively turned off and on
when the target interconnect charge and discharging control signals
respectively indicate that charging is not to occur and discharging
is to occur so as to draw the target interconnect discharging
current.
36. The system of claim 35 wherein the test interconnect charging
circuit comprises third and fourth transistors connected to the
test interconnect and configured to be respectively responsive to
the test interconnect charge and discharging control signals such
that: in the reset phase, the third and fourth transistors are
respectively turned on and off when the test interconnect charge
and discharging control signals respectively indicate that charging
is to occur and discharging is not to occur so as to draw the test
interconnect charging current; and in the measure phase, the third
and fourth transistors are respectively turned off and on when the
test interconnect charge and discharging control signals
respectively indicate that charging is not to occur and discharging
is to occur so as to draw the test interconnect discharging
current.
37. The system of claim 34 wherein the control signal generator is
formed on the IC chip and the test structure comprises the control
signal generator.
38. The system of claim 37 wherein: the control signal generator
comrpises a frequency divider to divide the frequency of a selected
control signal of the test and target interconnect charging and
discharging control signals by a pre-selected factor to generate a
frequency divided signal; and the system further comprising a
frequency meter to make a measurement of the frequency of the
frequency divided signal, whereby the measurement of the target
capacitance may further be computed from the pre-selected factor
and the measurement of the frequency.
Description
BRIEF DESCRIPTION OF THE INVENTION
1. The present invention relates generally to techniques of
extracting parameter measurements for circuit simulations. In
particular, it pertains to an improved IC chip, on-chip test
structure, and corresponding method for modeling one or more
interconnect capacitances. Precise measurements of the interconnect
capacitances can be made with the test structure. These
measurements are then used to accurately extract interconnect
parameter measurements for circuit simulations.
BACKGROUND OF THE INVENTION
2. As integrated circuits become increasingly laden with metal or
polysilicon interconnects, the resulting interconnect capacitances
are rapidly becoming a bottleneck in the design of faster ICs. It
has therefore become very important to model these capacitances in
order to accurately simulate the performance of ICs. However, it is
difficult to make measurements of modeled interconnect capacitances
with high accuracy and resolution. As a result, the extraction of
interconnect parameters using these measurements is often not
precise. This causes circuit simulations performed without
correctly extracted interconnect parameters to be inaccurate and
unreliable.
3. In the past, on-chip test structures have been used in attempts
to model interconnect capacitances with higher accuracy and
resolution. However, many of these test structures suffer from
significant deficiencies which make them inefficient and/or result
in interconnect capacitance measurements made with them being
inaccurate and/or having low resolution.
4. For example, the on-chip test structures disclosed in Khalkhal,
A., et al., On-Chip Measurement of Interconnect Capacitances in a
CMOS Process, Proc. IEEE 1995 Int. Conf. on Microelectronic Test
Structures, vol. 8 (March 1995), Gaston, G. J., et al., Efficient
Extraction of Metal Parasitic Capacitances, Proc. IEEE 1995 Int.
Conf. on Microelectronic Test Structures, vol. 8 (March 1995),
Shyu, J. B., et al., Random Effects in Matched MOS Capacitors and
Current Sources, IEEE Journal of Solid State Circuits, vol.
sc-19(6):948-955 (December 1984), Kortekaas, C., On-Chip
Quasi-Static Floating-Gate Capacitance Measurement Method, Proc.
IEEE 1990 Int. Conf. on Microelectronic Test Structures, vol. 3
(March 1990), and Laquai, B., et al., A New Method and Test
Structure for Easy Determination of Femto-Farad On-Chip
Capacitances in a MOS Process, Proc. IEEE 1992 Int. Conf. on
Microelectronic Test Structures, vol. 5:62-66 (March 1992), require
a reference capacitor and/or a complicated test structure design
and measurement set-up. Moreover, these test structures provide
only picofarad or femptofarad resolution and occupy a large chip
area.
5. An improved test structure with attofared resolution is
disclosed in Chen, J. C., et al., An On-Chip, Attofared
Interconnect Charge-Based Capacitance Measurement (CBCM) Technique,
Proc. of IEDM 1996, pp. 69-72. This test structure has a reference
structure and a target structure. The reference structure is
identical to the target structure except that the interconnect
configuration of the reference structure does not include the
target interconnect capacitance to be modeled and measured. The
difference in current between charging (or discharging) the total
capacitances of the reference and target structures is then used to
compute a measurement of the target interconnect capacitance.
6. One problem with such a test structure is that it requires a
corresponding reference structure for the target structure. This
obviously increases the chip area of the entire test structure.
7. Another problem is that the test structure can only be used to
measure one target interconnect capacitance. Thus, if an IC
designed by an IC designer has a complicated interconnect
configuration with many interconnect capacitances in close
proximity to each other, a separate test structure is required for
each of these interconnect capacitances. This increases the chip
area of the IC chip on which all of the test structures are
formed.
8. Conversely, if only one test structure is used for a complicated
interconnect configuration, only one lumped interconnect
capacitance can be modeled and measured. This means that the
specific interconnect capacitances that comprise the lumped
capacitance cannot be separately modeled and measured.
9. In view of the foregoing, it would be highly desirable to
provide an improved test structure that has small chip area and is
capable of separately modeling all of the specific interconnect
capacitances in a complicated interconnect configuration. Ideally,
the interconnect capacitance measurements made with such a test
structure could be used to extract interconnect parameters for
accurately simulating ICs.
SUMMARY OF THE INVENTION
10. In summary, the present invention comprises a system, an IC
chip, a test structure formed on the IC chip, and a corresponding
method for modeling one or more target interconnect
capacitances.
11. The test structure comprises an interconnect configuration
formed on the IC chip. The interconnect configuration comprises a
test interconnect and one or more target interconnects. The
interconnect configuration has, for each target interconnect, a
corresponding target interconnect capacitance between the test
interconnect and the target interconnect.
12. The test structure also comprises a test interconnect charging
circuit formed on the IC chip and connected to the test
interconnect. The test interconnect charging circuit is configured
to place a test charge on the test interconnect.
13. The test structure further comprises one or more target
interconnect charging circuits. Each target interconnect charging
circuit is formed on the IC chip and connected to a corresponding
target interconnect. Each target interconnect charging circuit is
configured to draw a target interconnect charging current from the
corresponding target interconnect in response to the test charge.
This places an opposite charge on the corresponding target
interconnect that is induced by the corresponding target
interconnect capacitance.
14. A measurement of the target interconnect charging current can
be made with a current meter of the system. From this measurement,
a measurement of the corresponding target interconnect capacitance
may be computed.
BRIEF DESCRIPTION OF THE DRAWINGS
15. FIG. 1 is a circuit schematic of an on-chip test structure for
modeling one or more target interconnect capacitances.
16. FIG. 2 shows a cross sectional layout of an interconnect
configuration in the test structure of FIG. 1.
17. FIG. 3 provides a timing diagram of the control signals used in
the test structure of FIG. 1.
18. FIG. 4 shows an embodiment where the on-chip test structure of
FIG. 1 is formed on an IC chip together with an IC.
DETAILED DESCRIPTION OF THE INVENTION
19. Referring to FIG. 1, there is shown a system 100 for modeling
one or more target interconnect capacitances c.sub.1 to c.sub.N,
where N>1. The system comprises an on-chip test structure 101
formed on an IC chip 102. The test structure is used in conjunction
with the other components of the system, namely an off-chip current
meter (A) 138, an off-chip frequency meter (Hz) 139, off-chip
voltage sources 128 to 131, and probes 133 to 137, to make
measurements of the target interconnect capacitances. As will be
described in the following sections, measurements of these target
interconnect capacitances may be made and used to extract
interconnect parameter measurements for circuit simulation.
20. Test Structure Configuration
21. The test structure 101 comprises an interconnect configuration
(i.e., structure) 104 to model the target interconnect capacitances
c.sub.1 to c.sub.N. The interconnect configuration models the same
interconnect configuration that will appear in an IC. Thus, it is
designed and fabricated on the IC chip 102 according to the same
physical parameters and semiconductor process steps that are used
in designing and fabricating the IC.
22. The interconnect configuration 104 comprises a test
interconnect 105 and one or more target interconnects 106-1 to
106-N. These interconnects may be metal or polysilicon.
Furthermore, each target capacitance c.sub.n, where
1.ltoreq.n.ltoreq.N, exists between the test interconnect 105 and a
corresponding target interconnect 106-n.
23. A cross sectional view of how the interconnect configuration
104 is laid out on the IC chip 102 is shown in FIG. 2. The
interconnect configuration is formed on a semiconductor substrate
107 of the IC chip. In addition to the interconnects 105 and 106-1
to 106-N, the interconnect configuration also comprises an
insulating material 108, such as oxide, formed on the substrate.
The interconnects are patterned within the insulating material in a
simple or complicated configuration or geometry. For example, the
interconnect configuration may comprise only two parallel
interconnects 105 and 106-1. Or, it may comprise an interconnect
105 with many overlapping, parallel, intertwined, and/or snaking
interconnects 106-1 to 106-N. Each target capacitance c.sub.n is
formed by the test interconnect 105, the corresponding target
interconnect 106-n, and the insulating material 108 between these
two interconnects.
24. Referring back to FIG. 1, the test structure 101 also comprises
target interconnect charging circuits 109-1 to 109-N, output pads
110-1 to 110-N, and an input pad 111. The target interconnect
charging circuits, output pads, and input pad are all formed on the
IC chip 102 using conventional semiconductor process
techniques.
25. For each target interconnect 106-n, there is a corresponding
target interconnect charging circuit 109-n and a corresponding
output pad 110-n. Each target interconnect charging circuit 109-n
is configured to enable a measurement of the corresponding target
interconnect capacitance c.sub.n to be made. For this purpose, it
comprises two NMOS transistors 112 and 113.
26. The drain, gate, and source of the transistor 112 are
respectively connected to the corresponding target interconnect
106-n, a target interconnect charging control circuit 115, and the
corresponding output pad 110-n. The control circuit is located in a
control signal generator 114 of the test structure 101. It provides
a target interconnect charging control signal CHRG1 to the gate of
the transistor during operation of the test structure. During this
time, the output pad is connected to the local ground voltage
source 131 via the current meter 138 and the probe 133 connected to
the current meter. This connects the source of the transistor to
the ground voltage source so that it receives the ground voltage
V.sub.GND.
27. Similarly, the drain, gate, and source of the other transistor
113 are respectively connected to the corresponding interconnect
106-n, a target interconnect discharging control circuit 116 in the
control signal generator 114, and the input pad 111. During
operation of the test structure 101, the control circuit provides a
target interconnect discharging control signal DCHRG1 to the gate
of the transistor. During this time, the input pad is connected to
the global ground voltage source 129 with the probe 134 to receive
the ground voltage V.sub.GND. As a result, the source of the
transistor is connected to the ground voltage source and receives
the ground voltage V.sub.GND.
28. The test structure 101 also comprises a test interconnect
charging circuit 117 and an input pad 118 formed on the IC chip 102
using conventional semiconductor process techniques. The off-chip
supply voltage source 128 is connected between this input pad and
the global ground voltage source 129 during operation of the test
structure 101. This is done with the probe 135 connected to the
supply voltage source. As a result, the input pad receives a supply
voltage V.sub.DD from the voltage source.
29. The test interconnect charging circuit 117 comprises a PMOS
transistor 119. The source and gate of the transistor are
respectively connected to the input pad 118 and a test interconnect
charging control signal generator 121 in the control signal
generator 114. The input pad and probe 135 connect the source of
the transistor to the supply voltage source 128 during operation of
the test structure 101. This provides the supply voltage V.sub.DD
to the source of the transistor. And, during this time, the control
circuit provides a test interconnect charging control signal CHRG2
to the gate of the transistor.
30. The test interconnect charging circuit 117 also comprises an
NMOS transistor 120. The gate and the source of the transistor are
respectively connected to a test interconnect discharging control
circuit 122 in the control signal generator 114 and the input pad
111. During operation of the test structure 101, the control
circuit provides a test interconnect discharging control signal
DCHRG2 to the gate of the transistor. Since the input pad is
connected to the global ground voltage source 129 with the probe
134 during this time, the source of the transistor is connected to
the global ground voltage source and receives the ground voltage
V.sub.GND.
31. The drains of the transistors 119 and 120 are connected
together and to the test interconnect 104. This connection forms a
node 123 of the test interconnect charging circuit 117. The node is
used to charge and discharge the test interconnect during operation
of the test structure 101. The manner in which this is done is
described in the section covering the operation of the test
structure 101.
32. The control signal generator 114 and input and output pads 124
and 125 of the test structure 101 are formed on the IC chip 102
using conventional semiconductor process techniques as well. In
addition to the control circuits 115, 116, 121, and 122, the
control signal generator also comprises a clock circuit 126 and a
frequency divider (M) 127.
33. The clock circuit 126 is connected to the control circuits 115,
116, 121, and 122 and the input pads 111, 118, and 124. During
operation, the clock circuit is connected to the supply and global
ground voltage sources 128 and 129 with the input pads 118 and 111
and probes 135 and 134. It therefore receives the supply and ground
voltages V.sub.DD and V.sub.GND and in response generates a clock
signal CLK. The frequency of the clock signal is controlled with a
frequency control voltage V.sub.freq. During operation, the
off-chip variable voltage source 130 is connected between the input
pad 124 and the global ground voltage source 129. This is done with
the probe 136 connected to the variable voltage source and connects
the clock circuit to the variable voltage source to receive the
frequency control voltage. In response to variations in the
frequency control voltage, the clock circuit adjusts the frequency
of the clock signal.
34. The control circuits 115, 116, 121, and 122 are each connected
to the clock circuit 126 to receive the clock signal CLK. In
response, the control circuits generate their respective control
signals CHRG1, DCHRG1, CHRG2, and DCHRG2.
35. The frequency divider 127 is connected to the target
interconnect charging control circuit 115 to receive the target
interconnect charging control signal CHRG1. It divides the
frequency f.sub.CHRG1 of this control signal by a pre-selected
factor M so that it can be measured. The frequency divider is
connected to the output pad 125 to provide it with the resulting
measurable frequency signal FREQ. The frequency f.sub.CHRG1/M of
this signal is measured with the frequency meter 139 during
operation of the test structure when the frequency meter is
connected between this output pad and the global ground voltage
source 129. This is done with the probe 137 connected to the
frequency meter.
36. Test Structure Operation
37. The method of making a measurement of any target interconnect
capacitance c.sub.n during operation of the test structure 101 will
now be described with respect to FIGS. 1 and 3. Example waveforms
of the control signals CHRG1, DCHRG1, CHRG2, and DCHRG2 required
for making such a measurement are shown in the timing diagram of
FIG. 3. Over the various phases (i.e., modes or time periods) of
operation of the test structure, these control signals transition
back and forth between low at 0 V (volts) and high at V.sub.DD. As
alluded to earlier, the frequency f.sub.CHRG1 of these signals is
arbitrary and can be set with the frequency control signal
V.sub.freq. In the timing diagram of FIG. 1, this frequency is 1
MHz.
38. During a reset phase between 0 ns and 300 ns, the test
structure 101 is reset for measurement of the interconnect
capacitance c.sub.n. The discharge and charging control signals
DCHRG2 and CHRG2 are high during this phase and respectively
indicate that discharging is to occur and charging is not to occur
on the test interconnect 105. In other words, only discharging is
to occur. In the charging circuit 117, this turns on the transistor
120 while leaving the transistor 119 off. As a result, a
discharging current I.sub.DCHRG2 is drawn by the transistor 120
from the interconnect to the global ground voltage source 129. This
removes any pre-existing charge on the interconnect.
39. Similarly, the discharging control signal DCHRG1 is high and
the charging control signal CHRG1 is low during the reset phase and
together indicate that only discharging is to occur on the
corresponding interconnect 106-n. Thus, the discharging control
signal indicates that discharging is to occur while the charging
control signal indicates that charging is not to occur. In the
corresponding target interconnect charging circuit 109-n, this
turns on the transistor 113 and leaves the transistor 112 off. A
discharging current I.sub.DCHRG1 is therefore drawn by the
transistor 112 from the local ground voltage source 131 to the
target interconnect. Thus, any pre-existing charge on the target
interconnect is also removed.
40. During an off phase between 300 ns and 400 ns, the discharging
control signals DCHRG2 and DCHRG1 are low and indicate that
discharging is not to occur on the interconnects 105 and 106-n,
respectively. The charging control signals CHRG2 and CHRG1 remain
respectively high and low during this phase and indicate that
charging is not to occur on these interconnects as well. Thus, all
of the transistors 119, 120, 112, and 113 are turned off.
41. During an enable phase from 400 ns to 500 ns, the charging
control signal CHRG1 is high and indicates that charging on the
target interconnect 106-n is to occur. The charging control signal
CHRG2 remains high while the discharging control signals DCHRG2 and
DCHRG1 remain low. This turns on the transistor 112 and leaves the
other transistors 119, 120, and 113 off. The test structure 101 is
now enabled for measuring the target interconnect capacitance
c.sub.n.
42. Then, during a measure phase between 500 ns and 800 ns, the
charging control signal CHRG2 is low and indicates that charging on
the test interconnect 105 is to occur. The discharging control
signal DCHRG2 remains low. The transistor 119 is now turned on
while the transistor 120 is still off. Therefore, the transistor
119 draws a charging current I.sub.CHRG2 from the external voltage
source 128 to the test interconnect. This places a desired charge
(c.sub.n) (V.sub.DD) on the test interconnect.
43. Since the interconnects 105 and 106-n are coupled together by
the target interconnect capacitance c.sub.n, an equal but opposite
charge -(c.sub.n) (V.sub.DD) is induced on the target interconnect
106-n during the measure phase. The charging control signal CHRG1
is high during this time period so that the transistor 112 is kept
on. As a result, a measurable charging current I.sub.CHRG1 is drawn
from the target interconnect through the current meter 138 and to
the local ground voltage source 131. This places the opposite
charge on the target interconnect. A measurement of this current is
made with the current meter during this phase.
44. During a disabling phase between 800 ns and 900 ns, the
charging control signals CHRG2 and CHRG1 are high while the
discharging control signals DCHRG2 and DCHRG1 remain low. This
turns off the transistors 119 and 120 so that the test structure
101 is disabled from placing anymore charge on the test
interconnect 105. However, the transistors 112 and 113 are
respectively on and off so that the measurable charging current
I.sub.CHRG1 is still being drawn from the target interconnect 106-n
and measured with the current meter 138. This is done to ensure
that all of the opposite charge -(c.sub.n) (V.sub.DD) on the target
interconnect 106-n has been measured.
45. Then, the charging control signal CHRG2 is high and the
discharge and charging control signals DCHRG2, CHRG1, and DCHRG1
are low during another off phase between 900 ns and 1000 ns. Thus,
all of the transistors 119, 120, 112, and 113 are now turned off.
The measurement of the measurable charging current I.sub.CHRG1 is
complete for this cycle.
46. The process just described is then repeated over one or more
measurement cycles. Since a conventional current meter 138 is used,
it provides a measurement of the average current I.sub.AVG for the
measurable charging current I.sub.CHRG1 according to: 1 I AVG = 1 T
I CHRG1 ( t ) t ( 1 )
47. where t represents time and T is the time period of one
measurement cycle. While this is all occurring, the frequency meter
139 is used to make a measurement of the frequency f.sub.CHRG1/M of
the measure control signal in a conventional manner. From these
measurements and the known values for the supply voltage V.sub.DD
and the factor M, a measurement of the target interconnect
capacitance c.sub.n can then be computed according to: 2 c n = I
AVG ( V DD ) ( f CHRG1 / M ) ( M ) ( 2 )
48. This provides a highly accurate measurement with attofared
resolution.
49. The method just described may be performed similarly for any of
the other target interconnect capacitances c.sub.1, . . . ,
c.sub.n+1, . . . , c.sub.N in the interconnect configuration 104,
regardless of their size, position, configuration, and/or geometry.
Furthermore, the method may be performed serially for each target
interconnect capacitance c.sub.n by appropriately connecting the
current meter 138 to the corresponding measure sub-circuit 109-n.
Or, it may be performed simultaneously for all of the interconnect
capacitances c.sub.1 to c.sub.N with corresponding current meters
connected to the target interconnect charging circuits 109-n to
109-N. Thus, only one test structure 101 is required to measure all
of the interconnect capacitances in this specific interconnect
configuration. This minimizes the chip area required by the test
structure on the IC chip 102.
50. Alternative Embodiments
51. As those skilled in the art will recognize, alternative
embodiments to that shown in FIG. 1 do exist. For example, only
NMOS or only PMOS transistors may be used in the charging circuit
117. Of course, this would require a corresponding inversion of one
of the charge and discharge signals CHRG2 and DCHRG2. Similarly,
only PMOS transistors may be used in each target interconnect
charging circuit 109-n. This also would require inversion of the
charge and discharging control signals CHRG1 and DCHRG1.
52. Furthermore, the control signal generator 114 is shown in FIG.
1 as being located on the IC chip 102. In another embodiment, it
could also be located off-chip. In this case, the test structure
101 would include input pads to receive the respective control
signals CHRG1, DCHRG1, CHRG2, and DCHRG2. The input pads would be
formed on the IC chip using conventional semiconductor process
techniques and would be connected to the respective control
circuits 115, 116, 121, and 122 of the control signal generator
with corresponding probes. The input pads would also be connected
to the respective transistors 112, 113, 119, and 120 to provide
them with the respective control signals.
53. In the section covering the operation of the test structure
101, it is mentioned that a measurement of the frequency
f.sub.CHRG2 of the charging control signal CHRG2 is to be made in
order to make a measurement of the target interconnect capacitance
c.sub.n. In other embodiments, a measurement of the frequency of
any one of the other control signals CHRG1, DCHRG1, and DCHRG2 can
also be selected for this purpose. In this case, the corresponding
control circuit 115, 116, or 122 will be connected to the frequency
divider 127.
54. As mentioned in the section covering the configuration of the
test structure 101, the interconnect configuration 104 of the test
structure is used to model an interconnect configuration in an IC.
As shown in FIG. 4, this IC 132 may also be formed on the same IC
chip 102 with the test structure 101. In this way, the IC and the
test structure can be fabricated simultaneously with exactly the
same physical parameters and semiconductor process steps. Moreover,
the measurements of the interconnect capacitances c.sub.1 to
c.sub.N can be directly made by the manufacturer or a buyer of the
IC chip. Alternatively, the test structure may be formed on a
separate IC chip than the IC.
55. As will also be appreciated by those skilled in the art, the
test structure 101 may be formed on the IC chip 102 with other test
structures that include different interconnect configurations than
that of the test structure 101. These interconnect configurations
will also be formed according to the physical parameters and
semiconductor process steps that are used in designing and
fabricating the IC that will include them.
56. Conclusion
57. The invention disclosed herein comprises an improved on-chip
test structure 101 and corresponding method for modeling target
interconnect capacitances c.sub.1 to c.sub.N of a particular
interconnect configuration 104. The interconnect configuration may
have a simple or complicated configuration or geometry. The use of
a target interconnect charging circuit 109-n for each target
interconnect 106-n enables the corresponding target interconnect
capacitance c.sub.n to be measured with high accuracy and
resolution. Moreover, only one test structure is required for
making these measurements so that the chip area of the IC chip 102
on which it is formed is small.
58. The high accuracy and resolution of the measurements of the
interconnect capacitances c.sub.1 to c.sub.N enables interconnect
parameter measurements to be accurately extracted for circuit
simulations. The extracted interconnect parameter measurements
include measurements of interconnect heights and widths, oxide
thicknesses between interconnects, and the interconnect
capacitances. The circuit simulations in which the extracted
interconnect parameter measurements are used are therefore very
precise.
59. Finally, although the present invention has been described with
reference to a few specific embodiments, the description is
illustrative of the invention and is not to be construed as
limiting the invention. Various modifications may occur to those
skilled in the art without departing from the true spirit and scope
of the invention as defined by the appended claims and their
equivalents.
* * * * *