U.S. patent application number 09/735387 was filed with the patent office on 2001-05-03 for enbedded memory assembly.
This patent application is currently assigned to Micron Technology, Inc.. Invention is credited to Raad, George B..
Application Number | 20010000630 09/735387 |
Document ID | / |
Family ID | 25536004 |
Filed Date | 2001-05-03 |
United States Patent
Application |
20010000630 |
Kind Code |
A1 |
Raad, George B. |
May 3, 2001 |
Enbedded memory assembly
Abstract
Memory devices, such as random access memory, are affixed to an
electrical contact frame and coupled to signals lines on the
contact frame which is, in turn, mounted on a top surface of an
integrated circuit. The signal leads are coupled to electrical
contact pads disposed on the top surface of the integrated circuit.
The contact pads and signal leads transfer control and power
signals between the integrated circuit and the memory devices.
Inventors: |
Raad, George B.; (Boise,
ID) |
Correspondence
Address: |
Schwegman, Lundberg, Woessner & Kluth, P.A.
P.O. Box 2938
Minneapolis
MN
55402
US
|
Assignee: |
Micron Technology, Inc.
|
Family ID: |
25536004 |
Appl. No.: |
09/735387 |
Filed: |
December 12, 2000 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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09735387 |
Dec 12, 2000 |
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09143604 |
Aug 31, 1998 |
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6160312 |
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09143604 |
Aug 31, 1998 |
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08990303 |
Dec 15, 1997 |
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5869895 |
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Current U.S.
Class: |
257/577 ;
257/E23.079; 257/E25.011 |
Current CPC
Class: |
H01L 2924/14 20130101;
H01L 2224/48091 20130101; H01L 2224/49175 20130101; H01L 24/49
20130101; H01L 25/0652 20130101; H01L 2924/1433 20130101; H01L
23/32 20130101; H01L 2924/00014 20130101; H01L 23/50 20130101; H01L
2924/14 20130101; H01L 24/48 20130101; H01L 2924/00014 20130101;
H01L 2924/00014 20130101; H01L 2224/05554 20130101; H01L 2924/00014
20130101; H01L 2924/00014 20130101; H01L 2224/05599 20130101; H01L
2224/45015 20130101; H01L 2224/85399 20130101; H01L 2924/207
20130101; H01L 2924/00 20130101; H01L 2924/00014 20130101; H01L
2224/45099 20130101; H01L 2224/48091 20130101; H01L 25/18
20130101 |
Class at
Publication: |
257/577 |
International
Class: |
H01L 027/082; H01L
027/102; H01L 029/70 |
Claims
What is claimed is:
1. An enbedded memory assembly comprising: an integrated circuit
having a plurality of electrical contact pads disposed on a top
surface coupled to memory-related control and power signals in the
integrated circuit; an electrical contact frame mounted adjacent to
the top surface of the integrated circuit and having a plurality of
signal leads coupled to the plurality of electrical contact pads;
and a plurality of memory devices affixed to the contact frame and
coupled to the signal leads.
2. The enbedded memory assembly of claim 1, wherein the integrated
circuit is a microprocessor.
3. The enbedded memory assembly of claim 1, wherein the electrical
contact pads are disposed in the center of the top surface of the
integrated circuit.
4. The enbedded memory assembly of claim 1, wherein the electrical
contact pads are disposed around the perimeter of the top surface
of the integrated circuit.
5. The enbedded memory assembly of claim 1, wherein electrical vias
couple the signal leads to the electrical contact pads.
6. The enbedded memory assembly of claim 5, wherein the electrical
vias are ball bonds.
7. The enbedded memory assembly of claim 5, wherein the electrical
vias are electrically conductive pillars.
8. The enbedded memory assembly of claim 1, wherein the signal
leads are electrically isolated from the contact frame.
9. An enbedded memory assembly comprising: an integrated circuit
having a plurality of electrical contact pads disposed on a top
surface coupled to memory-related control and power signals in the
integrated circuit; a stack of electrical contact frames, each
electrical contact frame comprising a plurality of signal leads and
having affixed thereto a plurality of memory devices coupled to the
signal leads which are further coupled to the contact pads, wherein
one of the electrical contact frames is mounted adjacent to the top
surface of the integrated circuit.
10. The enbedded memory assembly of claim 9, wherein the integrated
circuit is a microprocessor.
11. The enbedded memory assembly of claim 9, wherein the electrical
contact pads are disposed in the center of the top surface of the
integrated circuit.
12. The enbedded memory assembly of claim 9, wherein the electrical
contact pads are disposed around the perimeter of the top surface
of the integrated circuit.
13. The enbedded memory assembly of claim 9, wherein the signal
leads are electrically isolated from the contact frames.
14. A computer system having an enbedded memory assembly, the
computer system comprising: a motherboard; a microprocessor mounted
on the motherboard, the microprocessor having a plurality of
electrical contact pads disposed on a top surface coupled to
memory-related control and power signals in the microprocessor; an
electrical contact frame mounted adjacent to the top surface of the
microprocessor and having a plurality of signal leads coupled to
the plurality of electrical contact pads; and a plurality of memory
devices affixed to the frame and coupled to the signal leads.
15. The enbedded memory assembly of claim 14, wherein the
electrical contact pads are disposed in the center of the top
surface of the integrated circuit.
16. The enbedded memory assembly of claim 14, wherein the
electrical contact pads are disposed around the perimeter of the
top surface of the integrated circuit.
17. The enbedded memory assembly of claim 14, wherein the plurality
of signal leads are electrically isolated from the contact
frame.
18. A method of enbedding memory devices in an integrated circuit
assembly, the method comprising the steps of: depositing a
plurality of electrical contact pads on a top surface of an
integrated circuit; coupling the electrical contact pads to
memory-related control and power signals in the integrated circuit;
affixing a plurality of memory devices onto an electrical contact
frame; coupling the memory devices to a plurality of signal leads
on the contact frame; mounting the electrical contact frame
adjacent to the top surface of the integrated circuit; and further
coupling the signal leads to the electrical contact pads.
19. The method of claim 18 further comprising the step of
electrically isolating the signal leads from the contact frame.
20. An enbedded memory assembly comprising: an integrated circuit
means for generating memory-related control and power signals, the
integrated circuit means having a plurality of contact means
disposed on a top surface coupled to the memory-related control and
power signals; a frame means comprising a plurality of signal means
for transferring the memory-related control and power signals, the
frame means mounted adjacent to the top surface of the integrated
circuit means and having the signal means coupled to the contact
means; and a plurality of memory means affixed to the frame means
and coupled to the signal means.
Description
FIELD OF THE INVENTION
1. The present invention is related to integrated circuit packaging
and in particular to enbedding memory in the same package as an
integrated circuit.
BACKGROUND OF THE INVENTION
2. One of the limitations of speed on a personal computer are the
signal leads or traces on the motherboard that connect the
microprocessor to memory devices such as random access memory. The
length of the traces directly affects the speed at which signals
can be exchanged between the microprocessor and the memory.
Therefore, computer designers locate the memory as close to the
microprocessor as possible within design constraints imposed by
other components and the configuration of standard motherboards. As
the complexity of personal computers increases and the size of the
computer chassis decreases, the layout of the motherboard becomes a
critical design limitation because of the clearances required
between components on the motherboard, and between the motherboard
and other integrated circuit boards in the chassis.
3. One solution to minimize the length of the traces has been to
package the memory and the microprocessor together in the same
assembly. However, doing so without radically modifying the
configuration of the motherboard requires changing the die sizes of
either the memory, the microprocessor, or both.
4. Therefore, there is a need for a combined microprocessor/memory
assembly that minimizes the length of the traces without requiring
changes to the die sizes of the microprocessor, the memory, or to
the configuration of the motherboard.
SUMMARY OF THE INVENTION
5. Memory devices, such as random access memory, are affixed onto
an electrical contact frame and coupled to signals lines on the
frame which is, in turn, mounted on a top surface of an integrated
circuit,, such as a microprocessor, a controller chip, or an ASIC
(application-specific integrated circuit). The signal leads are
coupled to electrical contact pads disposed on the top surface of
the integrated circuit. The signal leads carry the control and
power signals between the integrated circuit and the memory.
6. The electrical contact pads are arranged in the center of the
top surface of the integrated circuit. The signal leads are coupled
to the electrical contact pads through ball bonds or metal pillars.
Alternatively, the electrical contact pads are disposed around the
perimeter of the top surface of the integrated circuit coupled to
the signal leads through conventional bonding techniques.
7. The enbedded memory assembly minimizes the signal leads running
between the integrated circuit and the memory without requiring
changes to the die sizes of the integrated circuit or the memory.
Therefore, the profile of the integrated circuit is increased only
minimally by the contact frame and the memory, requiring few, if
any, changes in existing manufacturing techniques while increasing
signal transfer speed between the integrated circuit and the
memory.
8. When the enbedded memory assembly is used in conjunction with a
microprocessor for a computer, major modifications to the
configuration of the motherboard and to the computer chassis are
unnecessary. Thus, the enbedded memory assembly allows a computer
manufacturer greater design freedom without sacrificing computer
performance.
BRIEF DESCRIPTION OF THE DRAWINGS
9. FIG. 1 is a perspective view of one embodiment of an enbedded
memory assembly having a microprocessor and memory devices.
10. FIG. 2 is a partially exploded view of one embodiment of the
enbedded memory assembly of FIG. 1.
11. FIG. 3 is a sectional view of the enbedded memory assembly of
FIG. 1 taken on the line 3-3.
12. FIG. 4 is a perspective view of an alternate embodiment of the
enbedded memory assembly.
13. FIG. 5 is a perspective view of a personal computer having a
motherboard on which is mounted the enbedded memory assembly of
FIG. 1.
14. FIG. 6A is a partially exploded view of an alternate embodiment
of the enbedded memory assembly showing a stacking arrangement for
the memory devices.
15. FIG. 6B is a sectional view of the enbedded memory assembly of
FIG. 6A.
DESCRIPTION OF THE EMBODIMENTS
16. In the following detailed description of the embodiments,
reference is made to the accompanying drawings which form a part
hereof, and in which is shown by way of illustration specific
embodiments in which the invention may be practiced. These
embodiments are described in sufficient detail to enable those
skilled in the art to practice the invention, and it is to be
understood that other embodiments may be utilized and that
structural, logical and electrical changes may be made without
departing from the spirit and scope of the present inventions. The
following detailed description is, therefore, not to be taken in a
limiting sense, and the scope of the present inventions is defined
only by the appended claims.
17. The leading digit(s) of reference numbers appearing in the
Figures corresponds to the Figure number, with the exception that
the same reference number is used throughout to refer to an
identical component which appears in multiple Figures. Signals and
connections may be referred to by the same reference number or
label, and the actual meaning will be clear from its use in the
context of the description.
18. An enbedded memory assembly places memory devices adjacent to a
top surface of an integrated circuit such as a microprocessor,
controller chip, or an ASIC (application-specific integrated
circuit), and couples leads from the memory devices to
memory-related signals from the integrated circuit through
electrical contact pads located on the top of the integrated
circuit.
19. FIG. 1 is a perspective view of one embodiment of the enbedded
memory assembly 100 having a microprocessor 101 and a plurality of
memory devices 103. The memory devices 103 can be dynamic random
access memory (DRAM), static random access memory (SRAM),
electrically programmable read-only memory (EPROM), or other types
of memory as will be readily apparent to one skilled in the art. A
plurality of electrical contact pads 105 are disposed on a top
surface 107 of the microprocessor 101 to transfer control and power
signals from the microprocessor to the memory devices 103. The
electrical contact pads 105 are formed of a solder alloy or a
conductive polymer adhesive such as commonly used in flip chip
assembly technology to attach a flip chip to a substrate. The
microprocessor has standard bond pads 112 bonded to its lead frame
and external leads 113 that transfer non-memory related signals to
other computer components.
20. An electrical contact frame 109 is mounted adjacent to the top
surface 107 of the microprocessor 101. The frame 109 is bonded to
the microprocessor using an material such as an epoxy adhesive
commonly used for die attachments. A plurality of signal leads 111
are coupled to the plurality of electrical contact pads 105 on the
microprocessor 101. The electrical contact frame 109 is grounded
through a tab 115. The memory devices 103 are affixed upside down
on the electrical contact frame 109 and coupled to the plurality of
signal leads 111. The electrical contact frame 109 can be a
standard LOC (lead-on-chip or lead-over-chip) lead frame as
illustrated in FIG. 1, or similarly constructed integrated circuit
board having electrical traces acting as the signal leads 111. The
traces are formed from solder or other conductive material, and are
arranged in a pattern to route the control and power signals to the
appropriate connectors on the memory devices 103. Some of the
control and power signals are common to all the memory devices 103
while others are specific to a single memory device. A simplistic
arrangement of the signal leads 111 is show in FIG. 1 for the sake
of clarity, but alternate embodiments will be readily apparent to
one skilled in the art. The memory devices 103 are bonded to the
electrical contact frame 109 and coupled to the signal leads 111
using any one of a number of well-known techniques for attaching
integrated circuits to lead frames or circuit boards.
21. The plurality of electrical contact pads 105 are coupled to the
plurality of signal leads 111 through electrical vias 201,
generically illustrated as electrically conductive pillars in FIG.
2. In an alternate embodiment, the electrical vias are ball bonds.
Additional coupling mechanisms will be readily apparent to those
skilled in the art.
22. The signal leads 111 are formed as part of the manufacturing of
the lead frame 109 and tie bar 207 maintains the structural
integrity of the lead frame 109. The tie bar 207 is removed to
electrically isolate the signal leads 111 from the lead frame 109
after the memory devices 103 are bonded to the lead frame 109 or
after the lead frame 109 with the attached memory devices 103 is
affixed to the microprocessor 101. In an alternate embodiment, the
tie bar 107 is made of non-conductive material and therefore does
not have to be removed to electrically isolate the signal leads 111
from the lead frame 109.
23. FIG. 3 is a sectional view of the enbedded memory assembly 100
of FIG. 1 showing one of the electrical vias 201 extending between
the signal leads 111 and the microprocessor 101 to transfer the
control and power signals. The memory devices 103 are mounted
upside down so that electrical contacts on the memory devices 103
couple with electrically conductive ball bonds 301 which in turn
couple to the signal leads 111. Non-conductive ball bonds 303
support portions of the memory devices 103 adjacent to the lead
frame 109. A die coat 203 is used to electrically isolate the
contact frame 109 from the top surface of the microprocessor 101.
The electrical contact frame 109 is adhered to adhesive tape 205
placed on the die coat 203.
24. In another alternate embodiment, the electrical contact pads
105 are disposed around the perimeter of the top surface 107 of the
microprocessor as shown in FIG. 4. The signal leads 401 are coupled
to the contact pads 105 using conventional bonding technology
well-known in the art. In this embodiment, tie bars 403 are removed
from the lead frame 109 to electrically isolate the memory devices
103 from the lead frame 109. In an alternate embodiment, the tie
bars 403 are non-conductive and remain in place.
25. FIG. 5 is a perspective view of a personal computer 500 having
a motherboard 501 on which is mounted the enbedded memory assembly
100 of FIG. 1.
26. The electrical contact frame is also suitable for stacking one
atop another as shown in FIGS. 6A and 6B. Such a stacking
arrangement can be used to enbed more memory devices in an
integrated circuit package than will fit on a single contact frame.
FIGS. 6A and 6B do not illustrate the coupling of the signal lines
from all the frames to the integrated circuit due to the complexity
of the interconnections in a stacked arrangement. Such couplings
are easily understood by one skilled in the art based the single
contact frame embodiments shown in FIGS. 1-4 and the corresponding
descriptions.
27. Another aspect of the invention is a method of enbedding memory
devices 103 in an integrated circuit assembly 100. The method
deposits a plurality of electrical contact pads 105 on a top
surface 107 of the integrated circuit 101. The electrical contact
pads 105 are coupled to memory-related control and power signals in
the integrated circuit 101. The memory devices 103 are affixed to
an electrical contact frame 109 which carries a plurality of signal
leads 111. The memory devices 103 are coupled to the signal leads
111. The electrical contact frame 109 is mounted adjacent to the
top surface 107 of the integrated circuit 101, and the signal leads
111 are coupled to the electrical contact pads 105 to complete
control and power circuits between the integrated circuit 101 and
the memory devices 103.
28. Other mechanisms for affixing the frame to the integrated
circuit, and the memory to the frame, will be apparent to those
skilled in the art, as will the use of alternate materials and
manufacturing methods for making the enbedded memory assembly.
29. It is to be understood that the above description is intended
to be illustrative, and not restrictive. Many other embodiments
will be apparent to those of skill in the art upon reviewing the
above description. The scope of the invention should, therefore, be
determined with reference to the appended claims, along with the
full scope of equivalents to which such claims are entitled.
* * * * *