U.S. patent application number 09/734522 was filed with the patent office on 2001-04-26 for apparatus and method for power management of embedded subsystems.
This patent application is currently assigned to Conexant Systems, Inc.. Invention is credited to Rhodes, F. Matthew, Zhao, Dongfeng.
Application Number | 20010000542 09/734522 |
Document ID | / |
Family ID | 22600457 |
Filed Date | 2001-04-26 |
United States Patent
Application |
20010000542 |
Kind Code |
A1 |
Zhao, Dongfeng ; et
al. |
April 26, 2001 |
Apparatus and method for power management of embedded
subsystems
Abstract
An apparatus and method for power management of embedded
electronic subsystems. A power management control circuit for
managing power to an embedded subsystem includes a subsystem power
node connected to a first section of the embedded electronic
subsystem and a bias voltage node connected to a second section of
the embedded electronic subsystem. A power switch is connected
between a power supply and the subsystem power node. By separating
the power subsystem node from the bias voltage node, power can be
removed from the subsystem, while still providing the necessary
bias voltage to the electronic static discharge (ESD) diodes. This
prevents the voltages applied to the system bus by the subsystem
from causing bus contention or system bus lock-ups. A power removal
and restoration procedure is also disclosed.
Inventors: |
Zhao, Dongfeng; (Irvine,
CA) ; Rhodes, F. Matthew; (Irvine, CA) |
Correspondence
Address: |
LYON & LYON LLP
SUITE 4700
633 WEST FIFTH STREET
LOS ANGELES
CA
90071-2066
US
|
Assignee: |
Conexant Systems, Inc.
4311 Jamboree Road
Newport Beach
CA
92660
|
Family ID: |
22600457 |
Appl. No.: |
09/734522 |
Filed: |
December 11, 2000 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
09734522 |
Dec 11, 2000 |
|
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|
09165781 |
Oct 2, 1998 |
|
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|
6163845 |
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Current U.S.
Class: |
713/320 |
Current CPC
Class: |
G06F 1/3287 20130101;
G06F 13/4081 20130101; Y02D 10/00 20180101; G06F 1/3203 20130101;
Y02D 10/171 20180101 |
Class at
Publication: |
713/320 |
International
Class: |
G06F 001/26; G06F
001/32 |
Claims
What is claimed is:
1. A power management control circuit for managing power of an
embedded electronic subsystem, the circuit comprising: a subsystem
power node connected to a first section of the embedded electronic
subsystem; a bias voltage node connected to a second section of the
embedded electronic subsystem; and a power switch connected between
a power supply and the subsystem power node.
2. The circuit of claim 1, wherein the second section comprises at
least one electronic static discharge (ESD) diode.
3. The circuit of claim 1, wherein the second section comprises two
electronic static discharge (ESD) diodes.
4. The circuit of claim 3, wherein the bias voltage node is further
connected to a bias voltage to bias the ESD diodes.
5. The circuit of claim 4, wherein the power switch is a field
effect transistor (FET).
6. The circuit of claim 5, wherein the power switch is switched to
remove power to the subsystem power node when the subsystem is not
in use.
7. The circuit of claim 6, wherein the subsystem is a modem.
8. The circuit of claim 6, wherein the subsystem has a tri-state
isolated gate transistor output driver.
9. A power management control method for removing power from an
embedded electronic subsystem connected to a system bus, the
subsystem comprising a subsystem power node, a bias power node, and
a power switch, the method comprising the steps of: halting all
system bus activities; maintaining a bias voltage to the bias power
node; halting all subsystem activities; switching the power switch
to remove power to the subsystem power node; and resuming system
bus activities after a sufficient time interval.
10. A power management control method for restoring power to an
embedded electronic subsystem connected to a system bus, the
subsystem comprising a subsystem power node, a bias power node and
a power switch, the method comprising the steps of: halting all
system bus activities; halting all subsystem activities; switching
the power switch to supply power to the subsystem power node;
resuming system bus activities after a sufficient time interval;
and resetting the embedded subsystem.
11. The method of claim 9, wherein the embedded subsystem is a
modem.
12. The method of claim 10, wherein the embedded subsystem is a
modem.
13. A power management method for managing power supplied to an
embedded electronic subsystem connected to a system bus, the
subsystem comprising: a subsystem power node connected to a first
section of the embedded electronic subsystem; a bias voltage node
connected to a second section of the embedded electronic subsystem;
and a power switch connected between a power supply and the
subsystem power node; wherein in order to remove power to the
subsystem, the method comprises the steps of: halting all system
bus activities; maintaining a bias voltage to the bias power node;
halting all subsystem activities; switching the power switch to
remove power to the subsystem power node; and resuming system bus
activities after a sufficient time interval; and wherein in order
to restore power to the subsystem, the method comprises the steps
of: halting all system bus activities; halting all subsystem
activities; switching the power switch to supply power to the
subsystem power node; resuming system bus activities after a
sufficient time interval; and resetting the embedded subsystem.
14. The method of claim 13, wherein the second section comprises at
least one electronic static discharge (ESD) diode.
15. The method of claim 13, wherein the second section comprises
two electronic static discharge (ESD) diodes.
16. The method of claim 15, wherein the bias voltage node is
further connected to a bias voltage to bias the ESD diodes.
17. The method of claim 16, wherein the power switch is a field
effect transistor (FET).
18. The method of claim 13, wherein the subsystem is a modem.
19. The method of claim 13, wherein the subsystem has a tri-state
isolated gate transistor output driver.
Description
BACKGROUND OF THE INVENTION
1. 1. Field of the Invention
2. The present invention relates to the field of power management,
and more particularly, to power management of embedded subsystems
such as embedded modems.
3. 2. Description of Related Art
4. With the proliferation of portable, battery-powered electronic
devices, power management has become a critical issue for device
performance. In order to extend the usable life of the battery
power source, sophisticated power management techniques have been
employed. In personal computers, the system microprocessor (Intel)
and operating system (Microsoft) work together to conserve system
power by controlling system resources. Various system devices may
be monitored, and power use regulated by cutting or reducing power
to inactive devices. For example, after a specified period of
inactivity, a timer in the operating system may trigger the system
display monitor to enter a "sleep" mode to reduce power
consumption. After another interval, the monitor may be completely
shutdown, further reducing power consumption. Similarly, power to
peripheral devices or plug-in cards can be controlled. These power
management techniques work due to the wide adoption of the
Intel/Microsoft implemented solutions.
5. In the embedded device market, however, these solutions are
inadequate since many different microprocessors and operating
systems are used, each with a different power management scheme.
With increased circuit integration, many manufacturers are
producing a "system-on-a-chip." In other words, many functions that
used to be performed by separate circuitry, are now performed on a
single chip. For example, modems may now be embedded into a device,
without being a separate peripheral. Unless power management
techniques are utilized, the various embedded subsystems can
severely drain the battery if they are powered on, but are not
used. In the case of a modem, power is continually being consumed
even though the user may only access the modem 10% of the time.
Since the modem is embedded, in cannot simply be removed Thus, the
"stand-by" power consumption of the embedded systems is a
significant source of power drain. In fact, testing has shown that
an embedded modem may draw 6-8 mA of current even in a "stop"
mode.
6. In many prior art attempts to manage power usage in an embedded
subsystem, additional power management circuitry is used. This
additional circuitry, however, is itself a source of power drain.
Also, merely cutting the power to the subsystem does not provide
satisfactory results. As shown in FIG. 1, a modem subsystem 2 is
connected to a power node 24. In order to disable power to the
subsystem when the subsystem is no in use, power supplied through
the power node 24 is simply cut-off. This may cause several
problems, however. First, since the signal applied to the system
bus is indeterminate, the system bus may crash, thereby locking-up
the system. The modem may also lock-up or otherwise fail, without
special power down processing. Thus, there is a need for an
improved power management system for embedded subsystems, such as
modems.
SUMMARY OF THE INVENTION
7. The present invention is an apparatus and method for power
management of embedded electronic subsystems. A power management
control circuit for managing power to an embedded subsystem
includes a subsystem power node connected to a first section of the
embedded electronic subsystem and a bias voltage node connected to
a second section of the embedded electronic subsystem. A power
switch is connected between a power supply and the subsystem power
node. By separating the power subsystem node from the bias voltage
node, power can be removed from the subsystem, while still
providing the necessary bias voltage to the electronic static
discharge (ESD) diodes. This prevents the signals applied to the
system bus by the subsystem from causing bus contention or system
bus lock-ups.
8. In order to take full advantage of the present invention, the
power needs to be removed and restored in a specific order. In
order to remove power from a subsystem, all system bus activities
must first be halted. The bias voltage to the bias voltage node is
maintained. All subsystem activity is suspended and then the power
switch is switched to remove power to the power subsystem node. All
system bus activities may then be resumed after a sufficient time
interval to insure the subsystem discharge has stabilized.
9. To restore power to the subsystem, all system bus and subsystem
activities are halted. Power is restored to the subsystem power
nodes and system bus activities are resumed after a sufficient time
interval. The host system then resets the embedded subsystem.
BRIEF DESCRIPTION OF THE DRAWINGS
10. The exact nature of this invention, as well as its objects and
advantages, will become readily apparent from consideration of the
following specification as illustrated in the accompanying
drawings, in which like reference numerals designate like parts
throughout the figures thereof, and wherein:
11. FIG. 1 is a schematic illustrating a prior art solution to
power management;
12. FIG. 2 is a schematic illustrating a power management scheme
according to the present invention;
13. FIG. 3 is a high-level block diagram of a modem subsystem
incorporating the present invention;
14. FIG. 4 is a schematic illustrating the operation of a power
switch according to the present invention;
15. FIG. 5 is a flowchart of the power management procedure
according to the present invention;
16. FIG. 6 illustrates the steps of the power down procedure
according to the present invention; and
17. FIG. 7 illustrates the steps of the power on procedure
according to the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
18. The following description is provided to enable any person
skilled in the art to make and use the invention and sets forth the
best modes contemplated by the inventor for carrying out the
invention. Various modifications, however, will remain readily
apparent to those skilled in the art, since the basic principles of
the present invention have been defined herein specifically to
provide an apparatus and method for power management, and more
particularly, to power management of embedded subsystems such as
embedded modems.
19. A preferred embodiment of the present invention will now be
described with reference to FIG. 2, illustrating a modem subsystem.
As those skilled in the art will recognize, however, the present
invention may be applied to any similar electronic embedded
subsystem. The modem subsystem 30 is divided into two separately
powered subsections 36, 38. The output section 36 is powered via a
modem subsystem power node 34, while the input section 38 is
powered via bias voltage node 32. In order to power down the modem
subsystem, power is removed from the modem subsystem power node 34.
The power to the bias voltage node 32 is held constant, however.
This prevents bus contention on the system bus by maintaining the
proper bias voltages to the electrical static discharge (ESD)
diodes 14, 16 in the input section 38. Notice that in the prior art
circuit of FIG. 1, when power is removed from the modem subsystem,
the diodes are no longer biased. Thus, the present circuit removes
power to non-essential circuitry of the embedded modem subsystem,
while still maintaining the proper bias voltages required by the
ESD diodes 14, 16.
20. FIG. 3 is a high-level block diagram of a modem subsystem
incorporating the present invention. The power to the modem
subsystem 40 is controlled by a switch 42. The switch may be
implemented using a single field effect transistor (FET). As shown
in FIG. 4, the FET switch 42 may connect the modem subsystem 40 to
either the host power supply, ground, or it may leave the node
floating, as desired. The ESD diodes (not shown) are always
connected to the bias voltage, without interruption. Notice that
the present invention can be implemented using only a single FET
and one extra power node. With one additonal power control pin from
the host microcontroller (to control the power switch 42), the
power ON and power OFF procedures can easily be implemented in a
variety of operating systems. Thus, the present invention does not
require significant additional power consuming power circuitry in
order to provide power management capabilities. In addition, the
present invention may be implemented with minimal cost.
21. FIG. 5 is a flow chart illustrating the subsystem power
procedure according to the present invention. At step 50, normal
bus activity occurs and the subsystem power is on. At decision
block 52, if the modem subsystem can be turned off (according to
some predetermined inactivity parameters), the power down procedure
is implemented at step 54. The power down procedure is illustrated
in detail in FIG. 6. First, all system bus activities are halted to
insure that there are no bus contention problems. All ESD bias
voltages are held constant. Then, all subsystem activities are
halted. The power to the subsystem power node is then removed (step
56). After a sufficient time interval to insure that the subsystem
discharge has stabilized, the system bus activities may be
restored. Since the ESD bias voltages to the subsystem have been
held constant, there are no bus contention problems caused by
floating nodes.
22. At step 58, with the subsystem off, the system engages in
normal bus activity. Once a power on request is detected, however,
the power on procedure (step 62) is performed. This power on
procedure is illustrated in detail in FIG. 7. First, all the system
bus activities are halted, and then all subsystem activities (if
any) are halted. The power to the subsystem is then restored by
applying power to the subsystem power node (step 64). The system
bus and the subsystem activities are restored after a sufficient
time interval to allow all voltage levels to stabilize. Finally,
the subsystem functions are reset (by the host) to insure that the
subsystem is in a known operational state in order to prevent
lock-ups.
23. According to testing, implementation of the present invention
can reduce the current drain of an embedded modem subsystem to
approximately 0.1 .mu.A in the powered down state. As stated
previously, prior art power management techniques draw
approximately 6-8 mA. Thus, the present invention provides a
significant improvement in power management for embedded
subsystems. The present invention is also independent of any
specific microcontroller or operating system, and may therefore be
applied to many different configurations.
24. The present invention has been described with reference to a
preferred embodiment, specifically an embedded modem subsystem. As
those skilled in the art will recognize, however, the present
invention may be applied to any similar electronic embedded
subsystem which has a similar tri-state output driver isolated gate
FET connected to the interface bus.
25. Those skilled in the art will appreciate that various
adaptations and modifications of the just-described preferred
embodiments can be configured without departing from the scope and
spirit of the invention. Therefore, it is to be understood that
within the scope of the appended claims, the invention may be
practiced other than as specifically described herein.
* * * * *