Yeh; Ching-Fa

Patent Applications and Registrations

Patent applications and USPTO patent grants for Yeh; Ching-Fa.The latest application filed is for "method for fabrication of polycrystalline silicon thin film transistors".

Company Profile

0.12.6

Yeh; Ching-Fa - Hsinchu TW
Yeh; Ching-Fa - N/A

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for fabrication of polycrystalline silicon thin film transistors Grant 7,115,449 - Yeh , et al. October 3, 2	2006-10-03
Method for fabrication of polycrystallin silicon thin film transistors Grant 7,109,075 - Yeh , et al. September 19, 2	2006-09-19
Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure Grant 6,903,029 - Yeh , et al. June 7, 2	2005-06-07
Method for fabrication of polycrystalline silicon thin film transistors App 20040266074 - Yeh, Ching-Fa ; et al.	2004-12-30
Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure App 20040258932 - Yeh, Ching-Fa ; et al.	2004-12-23
Method for fabrication of polycrystallin silicon thin film transistors App 20040241921 - Yeh, Ching-Fa ; et al.	2004-12-02
Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure Grant 6,774,461 - Yeh , et al. August 10, 2	2004-08-10
Method for liquid phase deposition Grant 6,653,245 - Liang , et al. November 25, 2	2003-11-25
Process For Preparing Cu Damascene Interconnection App 20020182851 - Yeh, Ching-Fa ; et al.	2002-12-05
Process for preparing Cu damascene interconnection Grant 6,486,057 - Yeh , et al. November 26, 2	2002-11-26
Method and apparatus for liquid phase deposition App 20020173170 - Liang, Muh-Wang ; et al.	2002-11-21
Method of reducing thick film stress of spin-on dielectric and the resulting sandwich dielectric structure App 20020142580 - Yeh, Ching-Fa ; et al.	2002-10-03
Method of sidewall capping for degradation-free damascene trenches of low dielectric constant dielectric by selective liquid-phase deposition Grant 6,251,753 - Yeh , et al. June 26, 2	2001-06-26
Method for forming a polyoxide film on doped polysilicon by anodization Grant 6,039,857 - Yeh , et al. March 21, 2	2000-03-21
Method of making a grooved gate structure of semiconductor device Grant 5,776,835 - Yeh , et al. July 7, 1	1998-07-07
Method for fabricating a polysilicon transistor having a buried-gate structure Grant 5,661,051 - Yeh , et al. August 26, 1	1997-08-26
Method for enhancing the growth rate of a silicon dioxide layer grown by liquid phase deposition Grant 5,648,128 - Yeh , et al. July 15, 1	1997-07-15
Method of improving electrical characteristics of a liquid phase deposited silicon dioxide film by plasma treatment Grant 5,614,270 - Yeh , et al. March 25, 1	1997-03-25

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