Yamoto; Hiroaki
Patent Applications and Registrations
Patent applications and USPTO patent grants for Yamoto; Hiroaki.The latest application filed is for "test method, test system and assist board".
- Yamoto; Hiroaki - Sunnyvale CA
- Yamoto; Hiroaki - Santa Clara CA
Trademarks
| Patent | Date |
|---|---|
| Test method, test system and assist board Grant 7,596,730 - Watanabe , et al. September 29, 2 | 2009-09-29 |
| Test method, test system and assist board App 20070234146 - Watanabe; Yuya ; et al. | 2007-10-04 |
| Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing Grant 7,178,115 - Rajsuman , et al. February 13, 2 | 2007-02-13 |
| Method for design validation of complex IC Grant 7,089,517 - Yamoto , et al. August 8, 2 | 2006-08-08 |
| Event based IC test system Grant 7,089,135 - Rajsuman , et al. August 8, 2 | 2006-08-08 |
| Method of evaluating core based system-on-a-chip Grant 6,944,808 - Rajsuman , et al. September 13, 2 | 2005-09-13 |
| High speed semiconductor test system using radially arranged pin cards Grant 6,791,316 - Rajsuman , et al. September 14, 2 | 2004-09-14 |
| High speed semiconductor test system App 20040056677 - Rajsuman, Rochit ; et al. | 2004-03-25 |
| Intangible property enumerating method and system App 20040019550 - Rajsuman, Rochit ; et al. | 2004-01-29 |
| Event based semiconductor test system Grant 6,678,643 - Turnquist , et al. January 13, 2 | 2004-01-13 |
| Method and apparatus for SoC design validation Grant 6,678,645 - Rajsuman , et al. January 13, 2 | 2004-01-13 |
| Event based IC test system App 20030217345 - Rajsuman, Rochit ; et al. | 2003-11-20 |
| Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing App 20030217343 - Rajsuman, Rochit ; et al. | 2003-11-20 |
| Architecture and design of universal IC test system App 20030217341 - Rajsuman, Rochit ; et al. | 2003-11-20 |
| Modular architecture for memory testing on event based test system Grant 6,651,204 - Rajsuman , et al. November 18, 2 | 2003-11-18 |
| Application specific event based semiconductor memory test system Grant 6,631,340 - Sugamori , et al. October 7, 2 | 2003-10-07 |
| Event based test system having improved semiconductor characterization map App 20030093737 - Purtell, Michael ; et al. | 2003-05-15 |
| Application specific event based semiconductor memory test system App 20030074153 - Sugamori, Shigeru ; et al. | 2003-04-17 |
| Method of evaluating core based system-on-a-chip App 20030056163 - Rajsuman, Rochit ; et al. | 2003-03-20 |
| Event based semiconductor test system Grant 6,532,561 - Turnquist , et al. March 11, 2 | 2003-03-11 |
| Method and apparatus for design validation of complex IC without using logic simulation App 20020173942 - Rajsuman, Rochit ; et al. | 2002-11-21 |
| Semiconductor integrated circuit design and evaluation system using cycle base timing Grant 6,370,675 - Matsumura , et al. April 9, 2 | 2002-04-09 |
| Method for design validation of complex IC App 20020040288 - Yamoto, Hiroaki ; et al. | 2002-04-04 |
| Method and structure for testing embedded cores based system-on-a-chip Grant 6,249,893 - Rajsuman , et al. June 19, 2 | 2001-06-19 |
| Method and structure for testing embedded memories Grant 6,249,889 - Rajsuman , et al. June 19, 2 | 2001-06-19 |
| High speed test pattern evaluation apparatus Grant 6,249,891 - Matsumura , et al. June 19, 2 | 2001-06-19 |
| Semiconductor integrated circuit evaluation system Grant 6,061,283 - Takahashi , et al. May 9, 2 | 2000-05-09 |
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