Yamoto, Hiroaki
USPTO Trademark & Patent Filings
Trademark applications and grants for Yamoto, Hiroaki. Yamoto, Hiroaki has 1 trademark applications. The latest application filed is for "CERTILITE"
- Company Aliases
- Yamoto, Hiroaki
- hiroaki yamoto
- Yamoto; Hiroaki - Sunnyvale CA
- Yamoto, Hiroaki - Santa Clara CA
- Yamoto; Hiroaki - Santa Clara CA
| Entity Type | INDIVIDUAL |
| Address | 336-1, Ohwa, Meiwa-cho Ohragun Gunma, 370-0718 JAPAN |
Trademarks Patents
| Patent Application | Date |
|---|---|
| Test method, test system and assist board 20070234146 - 11/394814 Watanabe; Yuya ; et al. | 2007-10-04 |
| High speed semiconductor test system 20040056677 - 10/253724 Rajsuman, Rochit ; et al. | 2004-03-25 |
| Intangible property enumerating method and system 20040019550 - 10/206713 Rajsuman, Rochit ; et al. | 2004-01-29 |
| Event based IC test system 20030217345 - 10/150777 Rajsuman, Rochit ; et al. | 2003-11-20 |
| Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing 20030217343 - 10/412143 Rajsuman, Rochit ; et al. | 2003-11-20 |
| Test method, test system and assist board 7,596,730 - 11/394,814 Watanabe , et al. September 29, 2 | 2009-09-29 |
| Manufacturing method and apparatus to avoid prototype-hold in ASIC/SOC manufacturing 7,178,115 - 10/412,143 Rajsuman , et al. February 13, 2 | 2007-02-13 |
| Method for design validation of complex IC 7,089,517 - 09/941,396 Yamoto , et al. August 8, 2 | 2006-08-08 |
| Event based IC test system 7,089,135 - 10/150,777 Rajsuman , et al. August 8, 2 | 2006-08-08 |
| Method of evaluating core based system-on-a-chip 6,944,808 - 10/225,930 Rajsuman , et al. September 13, 2 | 2005-09-13 |
Mark Image Registration | Serial | Trademark Application Date |
|---|---|
"CERTILITE" 76640968 |
CERTILITE 2005-06-15 |
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