loadpatents
name:-0.049927949905396
name:-0.050848960876465
name:-0.037330150604248
Vega; Reinaldo Patent Filings

Vega; Reinaldo

Patent Applications and Registrations

Patent applications and USPTO patent grants for Vega; Reinaldo.The latest application filed is for "phase-change memory device with reduced programming voltage".

Company Profile
30.45.50
  • Vega; Reinaldo - Mahopac NY
  • Vega; Reinaldo - Yorktown Heights NY
  • Vega; Reinaldo - Wappingers Falls NY
  • Vega; Reinaldo - Berkeley CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Resistive switching memory cell
Grant 11,456,416 - Adusumilli , et al. September 27, 2
2022-09-27
Phase-change Memory Device With Reduced Programming Voltage
App 20220293853 - Adusumilli; Praneet ;   et al.
2022-09-15
Resistance drift mitigation in non-volatile memory cell
Grant 11,430,954 - Adusumilli , et al. August 30, 2
2022-08-30
NCFETS with complimentary capacitance matching using stacked n-type and p-type nanosheets
Grant 11,424,362 - Ando , et al. August 23, 2
2022-08-23
Field Effect Transistor (fet) Devices
App 20220209018 - Vega; Reinaldo ;   et al.
2022-06-30
Ncfets With Complimentary Capacitance Matching Using Stacked N-type And P-type Nanosheets
App 20220190167 - Ando; Takashi ;   et al.
2022-06-16
Contact Resistance Reduction In Nanosheet Device Structure
App 20220181439 - Wu; Heng ;   et al.
2022-06-09
Decoupling Capacitor Inside Gate Cut Trench
App 20220181252 - Vega; Reinaldo ;   et al.
2022-06-09
Resistance Drift Mitigation In Non-volatile Memory Cell
App 20220173312 - Adusumilli; Praneet ;   et al.
2022-06-02
Resistive Switching Memory Cell
App 20220158092 - Adusumilli; Praneet ;   et al.
2022-05-19
Resistive Switching Memory Cell
App 20220158091 - Ando; Takashi ;   et al.
2022-05-19
Vertical resistive memory device with embedded selectors
Grant 11,335,730 - Ando , et al. May 17, 2
2022-05-17
Contact resistance reduction in nanosheet device structure
Grant 11,289,573 - Wu , et al. March 29, 2
2022-03-29
Reducing parasitic capacitance within semiconductor devices
Grant 11,244,864 - Xie , et al. February 8, 2
2022-02-08
Gate-all-around field effect transistor having multiple threshold voltages
Grant 11,245,020 - Bao , et al. February 8, 2
2022-02-08
Resistive Memory With Embedded Metal Oxide Fin For Gradual Switching
App 20220006009 - Ando; Takashi ;   et al.
2022-01-06
Transistor Having Stacked Source/drain Regions With Formation Assistance Regions And Multi-region Wrap-around Source/drain Contacts
App 20210408233 - Xie; Ruilong ;   et al.
2021-12-30
Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts
Grant 11,211,452 - Xie , et al. December 28, 2
2021-12-28
Vertical intercalation device for neuromorphic computing
Grant 11,211,429 - Tang , et al. December 28, 2
2021-12-28
Tapered resistive memory with interface dipoles
Grant 11,189,786 - Vega , et al. November 30, 2
2021-11-30
Resistive memory with embedded metal oxide fin for gradual switching
Grant 11,177,436 - Ando , et al. November 16, 2
2021-11-16
Vertical intercalation device for neuromorphic computing
Grant 11,164,908 - Tang , et al. November 2, 2
2021-11-02
Reducing Parasitic Capacitance Within Semiconductor Devices
App 20210327762 - Xie; Ruilong ;   et al.
2021-10-21
Resistive memory with core and shell oxides and interface dipoles
Grant 11,145,811 - Ando , et al. October 12, 2
2021-10-12
Device test pad probe card structure with individual probe manipulation capability
Grant 11,137,418 - Sinha , et al. October 5, 2
2021-10-05
Test probe assembly with fiber optic leads and photodetectors
Grant 11,125,780 - Sinha , et al. September 21, 2
2021-09-21
Test probe assembly with fiber optic leads and photodetectors for testing semiconductor wafers
Grant 11,119,148 - Nieves , et al. September 14, 2
2021-09-14
Cbram With Controlled Bridge Location
App 20210242402 - Tang; Jianshi ;   et al.
2021-08-05
CBRAM with controlled bridge location
Grant 11,050,023 - Tang , et al. June 29, 2
2021-06-29
Vertical Resistive Memory Device With Embedded Selectors
App 20210167128 - Ando; Takashi ;   et al.
2021-06-03
Resistive Memory with Core and Shell Oxides and Interface Dipoles
App 20210119122 - Ando; Takashi ;   et al.
2021-04-22
Tapered Resistive Memory with Interface Dipoles
App 20210098698 - Vega; Reinaldo ;   et al.
2021-04-01
Intercalation cells for multi-task learning
Grant 10,915,811 - Ando , et al. February 9, 2
2021-02-09
External resistance reduction with embedded bottom source/drain for vertical transport FET
Grant 10,903,318 - Lee , et al. January 26, 2
2021-01-26
Semiconductor device with mitigated local layout effects
Grant 10,892,181 - Zhou , et al. January 12, 2
2021-01-12
Cbram With Controlled Bridge Location
App 20210005813 - Tang; Jianshi ;   et al.
2021-01-07
Paired intercalation cells for drift migration
Grant 10,885,979 - Tang , et al. January 5, 2
2021-01-05
Vertical Intercalation Device For Neuromorphic Computing
App 20200373354 - Tang; Jianshi ;   et al.
2020-11-26
Nanowire enabled substrate bonding and electrical contact formation
Grant 10,833,048 - Hung , et al. November 10, 2
2020-11-10
Resistive Memory With Embedded Metal Oxide Fin For Gradual Switching
App 20200343448 - Ando; Takashi ;   et al.
2020-10-29
Multi-threshold vertical FETs with common gates
Grant 10,811,413 - Ando , et al. October 20, 2
2020-10-20
Paired Intercalation Cells For Drift Migration
App 20200327941 - Tang; Jianshi ;   et al.
2020-10-15
Stacked Resistive Random Access Memory With Integrated Access Transistor And High Density Layout
App 20200312912 - VEGA; REINALDO ;   et al.
2020-10-01
Device Test Pad Probe Card Structure With Individual Probe Manipulation Capability
App 20200284823 - Sinha; Kushagra ;   et al.
2020-09-10
Stacked resistive random access memory with integrated access transistor and high density layout
Grant 10,770,512 - Vega , et al. Sep
2020-09-08
Contact Resistance Reduction In Nanosheet Device Structure
App 20200279918 - Wu; Heng ;   et al.
2020-09-03
Vertical Intercalation Device For Neuromorphic Computing
App 20200273911 - TANG; Jianshi ;   et al.
2020-08-27
Gate-all-around Field Effect Transistor Having Multiple Threshold Voltages
App 20200258995 - A1
2020-08-13
Gate-all-around Field Effect Transistor Having Multiple Threshold Voltages
App 20200251568 - Kind Code
2020-08-06
Method Of Fin Oxidation By Flowable Oxide Fill And Steam Anneal To Mitigate Local Layout Effects
App 20200203214 - Zhou; Huimei ;   et al.
2020-06-25
Fin isolation to mitigate local layout effects
Grant 10,685,866 - Zhou , et al.
2020-06-16
External Resistance Reduction With Embedded Bottom Source/drain For Vertical Transport Fet
App 20200168706 - Lee; Choonghyun ;   et al.
2020-05-28
Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effects
Grant 10,658,224 - Zhou , et al.
2020-05-19
Rram Crossbar Array Structure For Multi-task Learning
App 20200143233 - Ando; Takashi ;   et al.
2020-05-07
External resistance reduction with embedded bottom source/drain for vertical transport FET
Grant 10,636,874 - Lee , et al.
2020-04-28
Structure And Methodology For High Intensity Test Probe Alignment To Device Test Pads
App 20200124663 - Nieves; Pablo ;   et al.
2020-04-23
Structure And Methodology For Determining Test Pad Integrity
App 20200124638 - Sinha; Kushagra ;   et al.
2020-04-23
Fin Isolation To Mitigate Local Layout Effects
App 20200083088 - Zhou; Huimei ;   et al.
2020-03-12
Fin Oxidation By Flowable Oxide Fill And Steam Anneal To Mitigate Local Layout Effects
App 20200083089 - Zhou; Huimei ;   et al.
2020-03-12
Gate-all-around field effect transistor having multiple threshold voltages
Grant 10,586,854 - Bao , et al.
2020-03-10
External Resistance Reduction With Embedded Bottom Source/drain For Vertical Transport Fet
App 20200075723 - Lee; Choonghyun ;   et al.
2020-03-05
Multi-threshold Vertical Fets With Common Gates
App 20200051979 - Ando; Takashi ;   et al.
2020-02-13
Nanowire Enabled Substrate Bonding And Electrical Contact Formation
App 20190319006 - HUNG; Li-Wen ;   et al.
2019-10-17
Data readout via reflected ultrasound signals
Grant 10,168,427 - Hung , et al. J
2019-01-01
Three-dimensional stacked junctionless channels for dense SRAM
Grant 10,170,485 - Guillorn , et al. J
2019-01-01
Three-Dimensional Stacked Junctionless Channels For Dense SRAM
App 20180342525 - Guillorn; Michael A. ;   et al.
2018-11-29
Gate-all-around field effect transistor having multiple threshold voltages
Grant 10,128,347 - Bao , et al. November 13, 2
2018-11-13
Gate-all-around Field Effect Transistor Having Multiple Threshold Voltages
App 20180308945 - Bao; Ruqiang ;   et al.
2018-10-25
Three-dimensional stacked junctionless channels for dense SRAM
Grant 10,096,607 - Guillorn , et al. October 9, 2
2018-10-09
Data Readout Via Reflected Ultrasound Signals
App 20180239016 - Hung; Li-Wen ;   et al.
2018-08-23
Gate-all-around Field Effect Transistor Having Multiple Threshold Voltages
App 20180190782 - Bao; Ruqiang ;   et al.
2018-07-05
Data readout via reflected ultrasound signals
Grant 10,001,561 - Hung , et al. June 19, 2
2018-06-19
Formation of metal resistor and e-fuse
Grant 9,997,411 - Tran , et al. June 12, 2
2018-06-12
Methods of forming uniform and pitch independent fin recess
Grant 9,875,939 - Ke , et al. January 23, 2
2018-01-23
Vertical field effect transistors with metallic source/drain regions
Grant 9,859,384 - Mallela , et al. January 2, 2
2018-01-02
Data Readout Via Reflected Ultrasound Signals
App 20170329003 - Hung; Li-Wen ;   et al.
2017-11-16
Vertical Field Effect Transistors With Metallic Source/drain Regions
App 20170317177 - Mallela; Hari V. ;   et al.
2017-11-02
Vertical field effect transistors with metallic source/drain regions
Grant 9,728,466 - Mallela , et al. August 8, 2
2017-08-08
Anisotropic dielectric material gate spacer for a field effect transistor
Grant 9,390,928 - Alptekin , et al. July 12, 2
2016-07-12
Anisotropic dielectric material gate spacer for a field effect transistor
Grant 9,337,041 - Alptekin , et al. May 10, 2
2016-05-10
Formation of metal resistor and e-fuse
Grant 9,312,185 - Tran , et al. April 12, 2
2016-04-12
Formation of air-gap spacer in transistor
Grant 9,305,835 - Alptekin , et al. April 5, 2
2016-04-05
Formation Of Metal Resistor And E-fuse
App 20150364419 - Tran; Cung ;   et al.
2015-12-17
Formation Of Metal Resistor And E-fuse
App 20150325483 - Tran; Cung ;   et al.
2015-11-12
Formation Of Air-gap Spacer In Transistor
App 20150243544 - Alptekin; Emre ;   et al.
2015-08-27
FinFET having suppressed leakage current
Grant 9,082,851 - Ramachandran , et al. July 14, 2
2015-07-14
FinFET HAVING SUPPRESSED LEAKAGE CURRENT
App 20150145064 - Ramachandran; Ravikumar ;   et al.
2015-05-28
Anisotropic Dielectric Material Gate Spacer For A Field Effect Transistor
App 20150108590 - Alptekin; Emre ;   et al.
2015-04-23
Anisotropic Dielectric Material Gate Spacer For A Field Effect Transistor
App 20150111350 - Alptekin; Emre ;   et al.
2015-04-23
Contact structures for semiconductor transistors
Grant 8,853,862 - Alptekin , et al. October 7, 2
2014-10-07
Contact Structures For Semiconductor Transistors
App 20130154026 - Alptekin; Emre ;   et al.
2013-06-20
Multi-valued logic/memory cells and methods thereof
Grant 7,548,455 - Vega , et al. June 16, 2
2009-06-16
Multi-valued Logic/memory Cells And Methods Thereof
App 20080037316 - Vega; Reinaldo ;   et al.
2008-02-14

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed