Utomo; Henry K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Utomo; Henry K..The latest application filed is for "semiconductor manufactured nano-structures for microbe or virus trapping or destruction".

Company Profile

14.64.69

Utomo; Henry K. - Ridgefield CT
Utomo; Henry K. - Newburgh NY
Utomo; Henry K. - Newbergh NY
Utomo; Henry K - Newburgh NY
Utomo; Henry K. - Hopewell Junction NY US
Utomo; Henry K. - Poughkeepsie NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor manufactured nano-structures for microbe or virus trapping or destruction Grant 11,150,168 - Astier , et al. October 19, 2	2021-10-19
FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth Grant 11,081,583 - Harley , et al. August 3, 2	2021-08-03
Semiconductor manufactured nano-structures for microbe or virus trapping or destruction Grant 11,060,960 - Astier , et al. July 13, 2	2021-07-13
Embedded source/drain structure for tall FinFet and method of formation Grant 10,896,976 - Basker , et al. January 19, 2	2021-01-19
Contact via structures Grant 10,777,735 - Yang , et al. Sept	2020-09-15
Contact via structures Grant 10,686,124 - Yang , et al.	2020-06-16
Semiconductor Manufactured Nano-structures For Microbe Or Virus Trapping Or Destruction App 20200141845 - Astier; Yann ; et al.	2020-05-07
FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth Grant 10,615,279 - Harley , et al.	2020-04-07
Contact Via Structures App 20200083426 - YANG; Chih-Chao ; et al.	2020-03-12
Contact Via Structures App 20200083436 - YANG; Chih-Chao ; et al.	2020-03-12
Forming self-aligned contacts on pillar structures Grant 10,586,921 - Annunziata , et al.	2020-03-10
Forming self-aligned contacts on pillar structures Grant 10,586,920 - Annunziata , et al.	2020-03-10
Finfet With Dielectric Isolation After Gate Module For Improved Source And Drain Region Epitaxial Growth App 20200066908 - HARLEY; ERIC C. ; et al.	2020-02-27
Semiconductor manufactured nano-structures for microbe or virus trapping or destruction Grant 10,557,779 - Astier , et al. Feb	2020-02-11
Embedded source/drain structure for tall FinFET and method of formation Grant 10,559,690 - Basker , et al. Feb	2020-02-11
Embedded Source/drain Structure For Tall Finfet And Method Of Formation App 20190371941 - Basker; Veeraraghavan S. ; et al.	2019-12-05
Semiconductor Manufactured Nano-structures For Microbe Or Virus Trapping Or Destruction App 20190310171 - Astier; Yann ; et al.	2019-10-10
Semiconductor manufactured nano-structures for microbe or virus trapping or destruction Grant 10,393,635 - Astier , et al. A	2019-08-27
Embedded Source/drain Structure For Tall Finfet And Method Of Formation App 20190252548 - Basker; Veeraraghavan S. ; et al.	2019-08-15
Semiconductor manufactured nano-structures for microbe or virus trapping or destruction Grant 10,246,730 - Astier , et al.	2019-04-02
FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth Grant 10,243,077 - Harley , et al.	2019-03-26
Semiconductor fin isolation by a well trapping fin portion Grant 10,242,980 - Utomo , et al.	2019-03-26
Embedded Source/drain Structure For Tall Finfet And Method Of Formation App 20190051751 - Basker; Veeraraghavan S. ; et al.	2019-02-14
Forming Self-aligned Contacts On Pillar Structures App 20180308897 - Annunziata; Anthony J. ; et al.	2018-10-25
Forming Self-aligned Contacts On Pillar Structures App 20180308898 - Annunziata; Anthony J. ; et al.	2018-10-25
Forming self-aligned contacts on pillar structures Grant 10,109,675 - Annunziata , et al. October 23, 2	2018-10-23
Forming Self-aligned Contacts On Pillar Structures App 20180261649 - Annunziata; Anthony J. ; et al.	2018-09-13
Asymmetric semiconductor device and method of forming same Grant 10,049,942 - Chou , et al. August 14, 2	2018-08-14
Finfet With Dielectric Isolation After Gate Module For Improved Source And Drain Region Epitaxial Growth App 20180097113 - HARLEY; ERIC C. ; et al.	2018-04-05
Junction butting structure using nonuniform trench shape Grant 9,923,082 - Chou , et al. March 20, 2	2018-03-20
FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth Grant 9,917,190 - Harley , et al. March 13, 2	2018-03-13
Fin-type field-effect transistors with strained channels Grant 9,905,694 - Utomo , et al. February 27, 2	2018-02-27
Fin-type Field-effect Transistors With Strained Channels App 20180026137 - Utomo; Henry K. ; et al.	2018-01-25
Methods of forming uniform and pitch independent fin recess Grant 9,875,939 - Ke , et al. January 23, 2	2018-01-23
Embedded source/drain structure for tall finFET and method of formation Grant 9,818,877 - Basker , et al. November 14, 2	2017-11-14
Semiconductor Manufactured Nano-structures For Microbe Or Virus Trapping Or Destruction App 20170191913 - Astier; Yann ; et al.	2017-07-06
Semiconductor Manufactured Nano-structures For Microbe Or Virus Trapping Or Destruction App 20170191106 - Astier; Yann ; et al.	2017-07-06
Semiconductor Manufactured Nano-structures For Microbe Or Virus Trapping Or Destruction App 20170189570 - Astier; Yann ; et al.	2017-07-06
Semiconductor manufactured nano-structures for microbe or virus trapping or destruction App 20170191912 - Astier; Yann ; et al.	2017-07-06
Junction Butting Structure Using Nonuniform Trench Shape App 20170179257 - Chou; Anthony I. ; et al.	2017-06-22
Fin-type field-effect transistors with strained channels Grant 9,680,019 - Utomo , et al. June 13, 2	2017-06-13
Conformal buffer layer in source and drain regions of fin-type transistors Grant 9,634,084 - Sheraw , et al. April 25, 2	2017-04-25
Junction butting structure using nonuniform trench shape Grant 9,627,480 - Chou , et al. April 18, 2	2017-04-18
Asymmetric Semiconductor Device And Method Of Forming Same App 20170076991 - Chou; Anthony I. ; et al.	2017-03-16
FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions Grant 9,577,100 - Cheng , et al. February 21, 2	2017-02-21
Diamond shaped source drain epitaxy with underlying buffer layer Grant 9,577,099 - Basker , et al. February 21, 2	2017-02-21
Semiconductor Fin Isolation By A Well Trapping Fin Portion App 20170040320 - Utomo; Henry K. ; et al.	2017-02-09
Forming fins of different semiconductor materials on the same substrate Grant 9,536,900 - Ramachandran , et al. January 3, 2	2017-01-03
Semiconductor fin isolation by a well trapping fin portion Grant 9,496,258 - Utomo , et al. November 15, 2	2016-11-15
Diamond Shaped Source Drain Epitaxy With Underlying Buffer Layer App 20160268413 - Basker; Veeraraghavan S. ; et al.	2016-09-15
Embedded Source/drain Structure For Tall Finfet And Method Of Formation App 20160260833 - Basker; Veeraraghavan S. ; et al.	2016-09-08
Method for fabricating semiconductor device Grant 9,412,842 - Kim , et al. August 9, 2	2016-08-09
Finfet With Dielectric Isolation After Gate Module For Improved Source And Drain Region Epitaxial Growth App 20160197186 - HARLEY; ERIC C. ; et al.	2016-07-07
Methods of Forming Field Effect Transistors Having Silicon-Germanium Source/Drain Regions Therein App 20160172361 - Rhee; Hwa-Sung ; et al.	2016-06-16
finFET with dielectric isolation after gate module for improved source and drain region epitaxial growth Grant 9,312,364 - Harley , et al. April 12, 2	2016-04-12
Partial Fin On Oxide For Improved Electrical Isolation Of Raised Active Regions App 20160079397 - Cheng; Kangguo ; et al.	2016-03-17
Finfet With Dielectric Isolation After Gate Module For Improved Source And Drain Region Epitaxial Growth App 20160035878 - HARLEY; ERIC C. ; et al.	2016-02-04
Junction Butting Structure Using Nonuniform Trench Shape App 20150380488 - Chou; Anthony I. ; et al.	2015-12-31
Partial FIN on oxide for improved electrical isolation of raised active regions Grant 9,219,114 - Cheng , et al. December 22, 2	2015-12-22
Finfet And Nanowire Semiconductor Devices With Suspended Channel Regions And Gate Structures Surrounding The Suspended Channel Regions App 20150364603 - Cheng; Kangguo ; et al.	2015-12-17
Finfet With Dielectric Isolation After Gate Module For Improved Source And Drain Region Epitaxial Growth App 20150349093 - Harley; ERIC C. ; et al.	2015-12-03
Forming Fins Of Different Semiconductor Materials On The Same Substrate App 20150340381 - Ramachandran; Ravikumar ; et al.	2015-11-26
Fin field effect transistors having heteroepitaxial channels Grant 9,190,406 - Alptekin , et al. November 17, 2	2015-11-17
Fin Field Effect Transistors Having Heteroepitaxial Channels App 20150206876 - Alptekin; Emre ; et al.	2015-07-23
FinFET having suppressed leakage current Grant 9,082,851 - Ramachandran , et al. July 14, 2	2015-07-14
FinFET HAVING SUPPRESSED LEAKAGE CURRENT App 20150145064 - Ramachandran; Ravikumar ; et al.	2015-05-28
Silicon-germanium fins and silicon fins on a bulk substrate Grant 9,029,913 - Utomo , et al. May 12, 2	2015-05-12
Prevention of faceting in epitaxial source drain transistors Grant 8,987,827 - Montanini , et al. March 24, 2	2015-03-24
Semiconductor Fin Isolation By A Well Trapping Fin Portion App 20150021625 - Utomo; Henry K. ; et al.	2015-01-22
Partial FIN On Oxide For Improved Electrical Isolation Of Raised Active Regions App 20150014773 - Cheng; Kangguo ; et al.	2015-01-15
Semiconductor fin isolation by a well trapping fin portion Grant 8,933,528 - Utomo , et al. January 13, 2	2015-01-13
Method For Fabricating Semiconductor Device App 20150011070 - Kim; Jin-Bum ; et al.	2015-01-08
Self-aligned contact employing a dielectric metal oxide spacer Grant 8,927,408 - Li , et al. January 6, 2	2015-01-06
Forming silicon-carbon embedded source/drain junctions with high substitutional carbon level Grant 8,927,375 - Alptekin , et al. January 6, 2	2015-01-06
Strained finFET with an electrically isolated channel Grant 8,928,086 - Utomo , et al. January 6, 2	2015-01-06
Strained Finfet With An Electrically Isolated Channel App 20140377924 - Utomo; Henry K. ; et al.	2014-12-25
Bottled Epitaxy In Source And Drain Regions Of Fets App 20140353741 - Montanini; Pietro ; et al.	2014-12-04
Silicon-germanium Fins And Silicon Fins On A Bulk Substrate App 20140252413 - Utomo; Henry K. ; et al.	2014-09-11
Semiconductor Fin Isolation By A Well Trapping Fin Portion App 20140252479 - Utomo; Henry K. ; et al.	2014-09-11
Strained Finfet With An Electrically Isolated Channel App 20140191297 - Utomo; Henry K. ; et al.	2014-07-10
Forming Silicon-carbon Embedded Source/drain Junctions With High Substitutional Carbon Level App 20140099763 - ALPTEKIN; EMRE ; et al.	2014-04-10
Method of forming a shallow trench isolation embedded polysilicon resistor Grant 8,685,818 - Shang , et al. April 1, 2	2014-04-01
Self-aligned contact employing a dielectric metal oxide spacer Grant 8,637,941 - Li , et al. January 28, 2	2014-01-28
Method of forming E-fuse in replacement metal gate manufacturing process Grant 8,492,286 - Utomo , et al. July 23, 2	2013-07-23
Self-aligned Contact Employing A Dielectric Metal Oxide Spacer App 20130178053 - Li; Ying ; et al.	2013-07-11
Methods Of Forming Field Effect Transistors Having Silicon-germanium Source/drain Regions Therein App 20130149830 - RHEE; Hwa-Sung ; et al.	2013-06-13
Structure and method for replacement metal gate field effect transistors Grant 8,420,491 - Utomo , et al. April 16, 2	2013-04-16
Planar silicide semiconductor structure Grant 8,236,637 - Utomo , et al. August 7, 2	2012-08-07
Methods of forming p-channel field effect transistors having SiGe source/drain regions Grant 8,198,194 - Yang , et al. June 12, 2	2012-06-12
Method Of Forming E-fuse In Replacement Metal Gate Manufacturing Process App 20120129312 - Utomo; Henry K. ; et al.	2012-05-24
Self-aligned Contact Employing A Dielectric Metal Oxide Spacer App 20120119307 - Li; Ying ; et al.	2012-05-17
Controlled Contact Formation Process App 20120112290 - Utomo; Henry K. ; et al.	2012-05-10
Planar Silicide Semiconductor Structure App 20120074503 - Utomo; Henry K. ; et al.	2012-03-29
Method of forming source and drain of field-effect-transistor and structure thereof Grant 8,138,053 - Utomo , et al. March 20, 2	2012-03-20
Method of Forming a Shallow Trench Isolation Embedded Polysilicon Resistor App 20110318897 - Shang; Huiling ; et al.	2011-12-29
Methods of Forming P-Channel Field Effect Transistors Having SiGe Source/Drain Regions App 20110237039 - Yang; Jong-Ho ; et al.	2011-09-29
Structure and method to form multilayer embedded stressors Grant 7,960,798 - Luo , et al. June 14, 2	2011-06-14
Semiconductor fabrication process including an SiGe rework method Grant 7,955,936 - Tan , et al. June 7, 2	2011-06-07
Hybrid orientation substrate and method for fabrication thereof Grant 7,892,899 - Yang , et al. February 22, 2	2011-02-22
Method of enhancing hole mobility Grant 7,863,653 - Utomo , et al. January 4, 2	2011-01-04
Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer Grant 7,781,800 - Chen , et al. August 24, 2	2010-08-24
Structure And Method To Form Multilayer Embedded Stressors App 20100059764 - Luo; Zhijiong ; et al.	2010-03-11
Semiconductor Fabrication Process Including An SiGe Rework Method App 20100009502 - Tan; Yong Siang ; et al.	2010-01-14
Structure and method for making strained channel field effect transistor using sacrificial spacer Grant 7,645,656 - Chen , et al. January 12, 2	2010-01-12
Structure and method to form multilayer embedded stressors Grant 7,618,866 - Luo , et al. November 17, 2	2009-11-17
Complementary Metal-oxide-semiconductor Device With Embedded Stressor App 20090242989 - CHAN; KEVIN K. ; et al.	2009-10-01
Integrated Circuit System Employing Diffused Source/drain Extensions App 20090146181 - Lai; Chung Woh ; et al.	2009-06-11
Methods for forming CMOS devices with intrinsically stressed metal silicide layers Grant 7,504,336 - Purtell , et al. March 17, 2	2009-03-17
Hybrid Orientation Substrate And Method For Fabrication Thereof App 20090029531 - Yang; Haining S. ; et al.	2009-01-29
Hybrid orientation substrate and method for fabrication of thereof Grant 7,482,209 - Yang , et al. January 27, 2	2009-01-27
Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer Grant 7,446,350 - Chen , et al. November 4, 2	2008-11-04
Embedded Silicon Germanium Using A Double Buried Oxide Silicon-on-insulator Wafer App 20080265281 - Chen; Huajie ; et al.	2008-10-30
SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET App 20080246056 - Chan; Victor W. C. ; et al.	2008-10-09
Method Of Forming Source And Drain Of Field-effect-transistor And Structure Thereof App 20080166847 - Utomo; Henry K. ; et al.	2008-07-10
Method Of Enhancing Hole Mobility App 20080116484 - Utomo; Henry K. ; et al.	2008-05-22
Hybrid Orientation Substrate And Method For Fabrication Thereof App 20080111214 - Yang; Haining S. ; et al.	2008-05-15
Structure And Method To Form Multilayer Embedded Stressors App 20080006818 - Luo; Zhijiong ; et al.	2008-01-10
Structure And Method For Forming Cmos Devices With Intrinsically Stressed Silicide Using Silicon Nitride Cap App 20070269970 - Purtell; Robert J. ; et al.	2007-11-22
Low Modulus Spacers For Channel Stress Enhancement App 20070096170 - Chidambarrao; Dureseti ; et al.	2007-05-03
In situ doped embedded sige extension and source/drain for enhanced PFET performance Grant 7,176,481 - Chen , et al. February 13, 2	2007-02-13
Structure And Method For Making Strained Channel Field Effect Transistor Using Sacrificial Spacer App 20060292779 - Chen; Huajie ; et al.	2006-12-28
Embedded Silicon Germanium Using A Double Buried Oxide Silicon-on-insulator Wafer App 20060255330 - Chen; Huajie ; et al.	2006-11-16
Structure and method for making strained channel field effect transistor using sacrificial spacer Grant 7,135,724 - Chen , et al. November 14, 2	2006-11-14
In Situ Doped Embedded Sige Extension And Source/drain For Enhanced Pfet Performance App 20060151837 - Chen; Huajie ; et al.	2006-07-13
Chemical treatment to retard diffusion in a semiconductor overlayer Grant 7,071,103 - Chan , et al. July 4, 2	2006-07-04
Structure And Method For Making Strained Channel Field Effect Transistor Using Sacrificial Spacer App 20060065914 - Chen; Huajie ; et al.	2006-03-30
Chemical Treatment To Retard Diffusion In A Semiconductor Overlayer App 20060024934 - Chan; Kevin K. ; et al.	2006-02-02