Uehling; Trent S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Uehling; Trent S..The latest application filed is for "semiconducitive catechol group encapsulant adhesion promoter for a packaged electronic device".

Company Profile

0.31.36

Uehling; Trent S. - New Braunfels TX US
Uehling; Trent S. - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and structures for detecting low strength in an interlayer dielectric structure Grant 9,659,831 - Uehling , et al. May 23, 2	2017-05-23
Heat spreader and method for forming Grant 9,548,256 - Uehling January 17, 2	2017-01-17
Semiconducitive Catechol Group Encapsulant Adhesion Promoter For A Packaged Electronic Device App 20160372339 - UEHLING; TRENT S.	2016-12-22
Substrate core via structure Grant 9,496,212 - Uehling November 15, 2	2016-11-15
Semiconducitive catechol group encapsulant adhesion promoter for a packaged electronic device Grant 9,466,544 - Uehling October 11, 2	2016-10-11
Heat Spreader And Method For Forming App 20160247744 - UEHLING; TRENT S.	2016-08-25
Heat sink having a through-opening Grant 9,385,064 - Uehling July 5, 2	2016-07-05
Substrate Core Via Structure App 20160181191 - UEHLING; TRENT S.	2016-06-23
Collapsible probe tower device and method of forming thereof Grant 9,373,539 - Uehling , et al. June 21, 2	2016-06-21
Semiconductor devices with compliant interconnects Grant 9,324,667 - Uehling , et al. April 26, 2	2016-04-26
Methods And Structures For Detecting Low Strength In An Interlayer Dielectric Structure App 20160027705 - UEHLING; TRENT S. ; et al.	2016-01-28
Heat Sink Having A Restrictive Region App 20150311136 - UEHLING; TRENT S.	2015-10-29
Collapsible Probe Tower Device and Method of Forming Thereof App 20150287654 - Uehling; Trent S. ; et al.	2015-10-08
Copper Tube Interconnect App 20150205041 - Neelakantan; Sriram ; et al.	2015-07-23
Heat conductive substrate for integrated circuit package Grant 9,070,657 - Pham , et al. June 30, 2	2015-06-30
Heat Conductive Substrate For Integrated Circuit Package App 20150097280 - Pham; Tim V. ; et al.	2015-04-09
Low-temperature flip chip die attach Grant 8,994,190 - Uehling March 31, 2	2015-03-31
Semiconductor wafer plating bus and method for forming Grant 8,895,409 - Uehling November 25, 2	2014-11-25
Semiconducitive Catechol Group Encapsulant Adhesion Promoter For A Packaged Electronic Device App 20140210063 - Uehling; Trent S.	2014-07-31
Packaged integrated circuit having large solder pads and method for forming Grant 8,766,453 - Uehling , et al. July 1, 2	2014-07-01
Packaged Integrated Circuit Having Large Solder Pads And Method For Forming App 20140117554 - Uehling; Trent S. ; et al.	2014-05-01
Semiconductor package structure having an air gap and method for forming Grant 8,704,370 - Uehling , et al. April 22, 2	2014-04-22
Semiconductor Package Structure Having An Air Gap And Method For Forming App 20140001632 - Uehling; Trent S. ; et al.	2014-01-02
Low-temperature Flip Chip Die Attach App 20130313726 - Uehling; Trent S.	2013-11-28
Semiconductor Wafer Plating Bus And Method For Forming App 20130309860 - UEHLING; TRENT S.	2013-11-21
Passivated Test Structures To Enable Saw Singulation Of Wafer App 20130299947 - Uehling; Trent S.	2013-11-14
Semiconductor wafer plating bus Grant 8,519,513 - Uehling August 27, 2	2013-08-27
Semiconductor Devices With Compliant Interconnects App 20130181340 - UEHLING; Trent S. ; et al.	2013-07-18
Semiconductor Wafer Plating Bus App 20130168830 - Uehling; Trent S.	2013-07-04
Fused buss for plating features on a semiconductor die Grant 8,368,172 - Leal , et al. February 5, 2	2013-02-05
Fused Buss For Plating Features On A Semiconductor Die App 20130020674 - LEAL; GEORGE R. ; et al.	2013-01-24
Fused Buss For Plating Features On A Semiconductor Die App 20130023091 - Leal; George R. ; et al.	2013-01-24
Fused buss for plating features on a semiconductor die Grant 8,349,666 - Leal , et al. January 8, 2	2013-01-08
Anchored conductive via and method for forming Grant 8,314,026 - Uehling November 20, 2	2012-11-20
Anchored Conductive Via And Method For Forming App 20120211883 - Uehling; Trent S.	2012-08-23
Dynamic pad size to reduce solder fatigue Grant 8,008,786 - Pham , et al. August 30, 2	2011-08-30
Dynamic Pad Size To Reduce Solder Fatigue App 20100264542 - Pham; Tim V. ; et al.	2010-10-21
Dynamic pad size to reduce solder fatigue Grant 7,772,104 - Pham , et al. August 10, 2	2010-08-10
Dynamic pad size to reduce solder fatigue App 20080185735 - Pham; Tim V. ; et al.	2008-08-07
Die level metal density gradient for improved flip chip package reliability Grant 7,276,435 - Pozder , et al. October 2, 2	2007-10-02
Scribe street structure for backend interconnect semiconductor wafer integration Grant 7,129,566 - Uehling , et al. October 31, 2	2006-10-31
Scribe street structure for backend interconnect semiconductor wafer integration App 20060001144 - Uehling; Trent S. ; et al.	2006-01-05
Metal reduction in wafer scribe area Grant 6,951,801 - Pozder , et al. October 4, 2	2005-10-04
Metal reduction in wafer scribe area App 20040147097 - Pozder, Scott K. ; et al.	2004-07-29
Apparatus for connecting a semiconductor die to a substrate and method therefor App 20020079595 - Carpenter, Burton J. ; et al.	2002-06-27

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