loadpatents
Patent applications and USPTO patent grants for Tseng; Yuan-Ping.The latest application filed is for "method for fabricating wafer-level chip scale packages".
Patent | Date |
---|---|
Method for fabricating anisotropic conductive substrate Grant 7,140,101 - Cheng , et al. November 28, 2 | 2006-11-28 |
Method for manufacturing probes of a probe card Grant 7,005,054 - Cheng , et al. February 28, 2 | 2006-02-28 |
Method for fabricating anisotropic conductive substrate App 20050066521 - Cheng, S. J. ;   et al. | 2005-03-31 |
Method for fabricating wafer-level chip scale packages App 20050070049 - Cheng, S. J. ;   et al. | 2005-03-31 |
Probe card assembly Grant 6,853,205 - Cheng , et al. February 8, 2 | 2005-02-08 |
Probe Card Assembly App 20050012513 - Cheng, Shih-Jye ;   et al. | 2005-01-20 |
Manufacturing process of memory module with direct die-attachment App 20050014308 - Tseng, Yuan-Ping ;   et al. | 2005-01-20 |
Modularized probe card with coaxial transmitters Grant 6,812,720 - Cheng , et al. November 2, 2 | 2004-11-02 |
Modularized Probe Card With Coaxial Transmitters App 20040207420 - Cheng, S. J. ;   et al. | 2004-10-21 |
Modularized probe card with compressible electrical connection device Grant 6,781,392 - Cheng , et al. August 24, 2 | 2004-08-24 |
Method and system for performing memory repair analysis Grant 6,751,760 - Tseng , et al. June 15, 2 | 2004-06-15 |
Method for manufacturing probes of a probe card App 20040035706 - Cheng, S. J. ;   et al. | 2004-02-26 |
Flip-chip type semiconductor device for reducing signal skew Grant 6,686,615 - Cheng , et al. February 3, 2 | 2004-02-03 |
Probe card with full wafer contact configuration App 20040012405 - Cheng, S. J. ;   et al. | 2004-01-22 |
Modular probe card assembly Grant 6,621,710 - Cheng , et al. September 16, 2 | 2003-09-16 |
Wafer level packaging for making flip-chips Grant 6,605,480 - Liu , et al. August 12, 2 | 2003-08-12 |
Wafer Level Packaging For Making Flip-chips App 20030098494 - Liu, An-Hong ;   et al. | 2003-05-29 |
System and method for avoiding waiting repair analysis for semiconductor testing equipment App 20030101388 - Tseng, Yuan-Ping ;   et al. | 2003-05-29 |
Method and system for performing memory repair analysis App 20030097626 - Tseng, Yuan-Ping ;   et al. | 2003-05-22 |
Semiconductor Wafer Designed To Avoid Probed Marks While Testing App 20020180026 - Liu, An-Hong ;   et al. | 2002-12-05 |
Manufacturing process of semiconductor devices Grant 6,395,622 - Liu , et al. May 28, 2 | 2002-05-28 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.