Tsao; Alwin J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tsao; Alwin J..The latest application filed is for "deep collector vertical bipolar transistor with enhanced gain".

Company Profile

0.11.7

Tsao; Alwin J. - Garland TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Deep collector vertical bipolar transistor with enhanced gain Grant 9,397,164 - Hornung , et al. July 19, 2	2016-07-19
Well resistors and polysilicon resistors Grant 9,379,176 - Heinrich-Barna , et al. June 28, 2	2016-06-28
Deep Collector Vertical Bipolar Transistor With Enhanced Gain App 20160079364 - Hornung; Brian E. ; et al.	2016-03-17
Well Resistors And Polysilicon Resistors App 20160056227 - Heinrich-Barna; Stephen Keith ; et al.	2016-02-25
Deep collector vertical bipolar transistor with enhanced gain Grant 9,245,755 - Hornung , et al. January 26, 2	2016-01-26
Well Resistors And Polysilicon Resistors App 20150349046 - Heinrich-Barna; Stephen Keith ; et al.	2015-12-03
Well resistors and polysilicon resistors Grant 9,202,859 - Heinrich-Barna , et al. December 1, 2	2015-12-01
Deep Collector Vertical Bipolar Transistor With Enhanced Gain App 20150187760 - Hornung; Brian E. ; et al.	2015-07-02
Tri-gate low power device and method for manufacturing the same Grant 7,274,046 - Adam , et al. September 25, 2	2007-09-25
Tri-gate low power device and method for manufacturing the same Grant 7,141,480 - Adam , et al. November 28, 2	2006-11-28
Tri-gate low power device and method for manufacturing the same App 20050227439 - Adam, Lahir Shaik ; et al.	2005-10-13
Tri-gate low power device and method for manufacturing the same App 20050215022 - Adam, Lahir Shaik ; et al.	2005-09-29
Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity Grant 6,693,357 - Borst , et al. February 17, 2	2004-02-17
System to minimize the temperature coefficient of resistance of passive resistors in an integrated circuit process flow App 20010000122 - Baldwin, Greg C. ; et al.	2001-04-05
System to minimize the temperature coefficient of resistance of passive resistors in an integrated circuit process flow Grant 6,211,769 - Baldwin , et al. April 3, 2	2001-04-03
Method to optimize copper chemical-mechanical polishing in a copper damascene interconnect process for integrated circuit applications Grant 6,162,728 - Tsao , et al. December 19, 2	2000-12-19
On-chip ESD protection in dual voltage CMOS Grant 6,143,594 - Tsao , et al. November 7, 2	2000-11-07
On-chip ESD protection in dual voltage CMOS Grant 6,137,144 - Tsao , et al. October 24, 2	2000-10-24

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