loadpatents
Patent applications and USPTO patent grants for TSAI; Cheng-Hsiung.The latest application filed is for "semiconductor device structure and methods of forming the same".
Patent | Date |
---|---|
Semiconductor Device Structure And Methods Of Forming The Same App 20220277995 - CHU; Hwei-Jay ;   et al. | 2022-09-01 |
Semiconductor structure and method for forming the same Grant 11,393,718 - Chu , et al. July 19, 2 | 2022-07-19 |
Self-aligned Via Structures And Methods App 20220165661 - Wu; Chieh-Han ;   et al. | 2022-05-26 |
Substrate Position Calibration For Substrate Supports In Substrate Processing Systems App 20220099426 - MATSUSHITA; Tomoharu ;   et al. | 2022-03-31 |
Self-aligned via structures with barrier layers Grant 11,251,118 - Wu , et al. February 15, 2 | 2022-02-15 |
Substrate position calibration for substrate supports in substrate processing systems Grant 11,201,078 - Matsushita , et al. December 14, 2 | 2021-12-14 |
Semiconductor Structure And Method For Forming The Same App 20210242078 - CHU; Hwei-Jay ;   et al. | 2021-08-05 |
Two piece shutter disk assembly with self-centering feature Grant 11,043,406 - Tsai , et al. June 22, 2 | 2021-06-22 |
Physical vapor deposition (PVD) electrostatic chuck with improved thermal coupling for temperature sensitive processes Grant 11,031,273 - Chia , et al. June 8, 2 | 2021-06-08 |
PVD buffer layers for LED fabrication Grant 11,011,676 - Zhu , et al. May 18, 2 | 2021-05-18 |
Self-Aligned Via Structures and Methods App 20210082804 - Wu; Chieh-Han ;   et al. | 2021-03-18 |
Method and apparatus for processing a substrate using non-contact temperature measurement Grant 10,950,475 - Ramachandran , et al. March 16, 2 | 2021-03-16 |
Interconnect Structures with Low-Aspect-Ratio Contact Vias App 20210057333 - Tsai; Cheng-Hsiung ;   et al. | 2021-02-25 |
Method And Apparatus For Processing A Substrate Using Non-contact Temperature Measurement App 20210057244 - RAMACHANDRAN; VINODH ;   et al. | 2021-02-25 |
Interconnect Structure Having an Etch Stop Layer Over Conductive Lines App 20210035856 - Tsai; Cheng-Hsiung ;   et al. | 2021-02-04 |
Interconnect structure having an etch stop layer over conductive lines Grant 10,861,742 - Tsai , et al. December 8, 2 | 2020-12-08 |
Inline Microwave Batch Degas Chamber App 20200378006 - GAUTAM; RIBHU ;   et al. | 2020-12-03 |
Methods and apparatus for shutter disk assembly detection Grant 10,851,453 - Tsai , et al. December 1, 2 | 2020-12-01 |
Spacer Etching Process For Integrated Circuit Design App 20200286738 - LIU; RU-GUN ;   et al. | 2020-09-10 |
High conductance process kit Grant 10,763,086 - Chia , et al. Sep | 2020-09-01 |
Base plate for a processing chamber substrate support Grant D893,441 - Rao , et al. A | 2020-08-18 |
Method and Apparatus for cleaning a substrate App 20200230782 - AGARWAL; Pulkit ;   et al. | 2020-07-23 |
Apparatus to improve substrate temperature uniformity Grant 10,711,348 - Tsai , et al. | 2020-07-14 |
Process kit design for in-chamber heater and wafer rotating mechanism Grant 10,704,147 - Rasheed , et al. | 2020-07-07 |
Deposition ring for physical vapor deposition chamber Grant D888,903 - Gunther , et al. | 2020-06-30 |
Process Kit Having Tall Deposition Ring For Pvd Chamber App 20200194243 - GUNTHER; DAVID ;   et al. | 2020-06-18 |
Physical Vapor Deposition (pvd) Electrostatic Chuck With Improved Thermal Coupling For Temperature Sensitive Processes App 20200185247 - CHIA; BONNIE T ;   et al. | 2020-06-11 |
Spacer etching process for integrated circuit design Grant 10,665,467 - Liu , et al. | 2020-05-26 |
Two Piece Shutter Disk Assembly With Self-centering Feature App 20190326154 - TSAI; CHENG-HSIUNG ;   et al. | 2019-10-24 |
Substrate Support With Edge Seal App 20190326152 - KE; CHANG ;   et al. | 2019-10-24 |
Methods And Apparatus For Shutter Disk Assembly Detection App 20190316251 - TSAI; CHENG-HSIUNG ;   et al. | 2019-10-17 |
Interconnect Structure Having an Etch Stop Layer Over Conductive Lines App 20190287848 - Tsai; Cheng-Hsiung ;   et al. | 2019-09-19 |
Interconnect structure having an etch stop layer over conductive lines Grant 10,312,139 - Tsai , et al. | 2019-06-04 |
Apparatus and method for reducing substrate sliding in process chambers Grant 10,262,877 - Thirunavukarasu , et al. | 2019-04-16 |
Substrate Support For Reduced Damage Substrate Backside App 20190080951 - HUSTON; Joel M. ;   et al. | 2019-03-14 |
Substrate support with improved RF return Grant 10,134,615 - Kamath , et al. November 20, 2 | 2018-11-20 |
Substrate Position Calibration For Substrate Supports In Substrate Processing Systems App 20180233396 - MATSUSHITA; TOMOHARU ;   et al. | 2018-08-16 |
Semiconductor device including a target integrated circuit pattern Grant 10,049,919 - Wu , et al. August 14, 2 | 2018-08-14 |
Lithography using high selectivity spacers for pitch reduction Grant 10,014,175 - Chang , et al. July 3, 2 | 2018-07-03 |
Method of forming an interconnect structure for a semiconductor device Grant 9,997,404 - Wu , et al. June 12, 2 | 2018-06-12 |
Process Kit Design For In-chamber Heater And Wafer Rotating Mechanism App 20180155838 - RASHEED; Muhammad M. ;   et al. | 2018-06-07 |
High Conductance Process Kit App 20180130644 - CHIA; Bonnie T. ;   et al. | 2018-05-10 |
Self-aligned double spacer patterning process Grant 9,911,646 - Tsai , et al. March 6, 2 | 2018-03-06 |
Substrate support with multiple heating zones Grant 9,888,528 - Matsushita , et al. February 6, 2 | 2018-02-06 |
Lithography Using High Selectivity Spacers for Pitch Reduction App 20180012761 - Chang; Yu-Sheng ;   et al. | 2018-01-11 |
High conductance process kit Grant 9,865,437 - Chia , et al. January 9, 2 | 2018-01-09 |
Self-aligned double spacer patterning process Grant 9,831,117 - Wu , et al. November 28, 2 | 2017-11-28 |
In situ plasma clean for removal of residue from pedestal surface without breaking vacuum Grant 9,818,585 - Green , et al. November 14, 2 | 2017-11-14 |
Interconnect Structure Having an Etch Stop Layer Over Conductive Lines App 20170287775 - Tsai; Cheng-Hsiung ;   et al. | 2017-10-05 |
Lithography using high selectivity spacers for pitch reduction Grant 9,773,676 - Chang , et al. September 26, 2 | 2017-09-26 |
Semiconductor device manufacturing methods Grant 9,768,031 - Huang , et al. September 19, 2 | 2017-09-19 |
Metal lines for interconnect structure and method of manufacturing same Grant 9,735,052 - Tsai , et al. August 15, 2 | 2017-08-15 |
Self-Aligned Double Spacer Patterning Process App 20170200641 - Tsai; Cheng-Hsiung ;   et al. | 2017-07-13 |
Apparatus And Method For Reducing Substrate Sliding In Process Chambers App 20170186631 - THIRUNAVUKARASU; SRISKANTHARAJAH ;   et al. | 2017-06-29 |
Interconnect structure having an etch stop layer over conductive lines Grant 9,685,368 - Tsai , et al. June 20, 2 | 2017-06-20 |
Method Of Spacer Patterning To Form A Target Integrated Circuit Pattern App 20170162435 - WU; Chieh-Han ;   et al. | 2017-06-08 |
Semiconductor integrated circuit with nano gap Grant 9,653,349 - Tsai , et al. May 16, 2 | 2017-05-16 |
Structure and method for interconnection Grant 9,627,215 - Huang , et al. April 18, 2 | 2017-04-18 |
Integrated circuit interconnects and methods of making same Grant 9,627,256 - Tsai , et al. April 18, 2 | 2017-04-18 |
Method for Interconnect Scheme App 20170103915 - Tsai; Cheng-Hsiung ;   et al. | 2017-04-13 |
Pad design for electrostatic chuck surface Grant 9,613,846 - Raj , et al. April 4, 2 | 2017-04-04 |
Structure and Method for Interconnection App 20170092580 - HUANG; CHIEN-HUA ;   et al. | 2017-03-30 |
Self-aligned double spacer patterning process Grant 9,607,850 - Tsai , et al. March 28, 2 | 2017-03-28 |
Apparatus and method for reducing substrate sliding in process chambers Grant 9,595,464 - Thirunavukarasu , et al. March 14, 2 | 2017-03-14 |
Spacer Etching Process for Integrated Circuit Design App 20170069505 - LIU; RU-GUN ;   et al. | 2017-03-09 |
Method for interconnect scheme Grant 9,589,890 - Yao , et al. March 7, 2 | 2017-03-07 |
Method of spacer patterning to form a target integrated circuit pattern Grant 9,576,814 - Wu , et al. February 21, 2 | 2017-02-21 |
Interconnect structure and method of forming the same Grant 9,564,397 - Tsai , et al. February 7, 2 | 2017-02-07 |
Method for Interconnect Scheme App 20170025346 - Yao; Hsin-Chieh ;   et al. | 2017-01-26 |
Interconnect Structure Having an Etch Stop Layer Over Conductive Lines App 20160379871 - Tsai; Cheng-Hsiung ;   et al. | 2016-12-29 |
Method Of Forming An Interconnect Structure For A Semiconductor Device App 20160365276 - WU; Yung-Hsu ;   et al. | 2016-12-15 |
Spacer etching process for integrated circuit design Grant 9,502,261 - Liu , et al. November 22, 2 | 2016-11-22 |
Integrated circuit interconnects and methods of making same Grant 9,490,205 - Tsai , et al. November 8, 2 | 2016-11-08 |
Methods and Apparatus for Cleaning a Substrate App 20160322239 - AGARWAL; Pulkit ;   et al. | 2016-11-03 |
Method of semiconductor integrated circuit fabrication Grant 9,478,430 - Yao , et al. October 25, 2 | 2016-10-25 |
Pvd Buffer Layers For Led Fabrication App 20160293798 - Zhu; Mingwei ;   et al. | 2016-10-06 |
Apparatus To Improve Substrate Temperature Uniformity App 20160258061 - TSAI; CHENG-HSIUNG ;   et al. | 2016-09-08 |
Method of forming an interconnect structure for a semiconductor device Grant 9,431,297 - Wu , et al. August 30, 2 | 2016-08-30 |
Substrate Support With Improved Rf Return App 20160240426 - KAMATH; ARAVIND MIYAR ;   et al. | 2016-08-18 |
PVD buffer layers for LED fabrication Grant 9,396,933 - Zhu , et al. July 19, 2 | 2016-07-19 |
Substrate Support With Multiple Heating Zones App 20160192444 - MATSUSHITA; TOMOHARU ;   et al. | 2016-06-30 |
High Conductance Process Kit App 20160189936 - CHIA; Bonnie T. ;   et al. | 2016-06-30 |
Semiconductor patterning Grant 9,355,865 - Tsai , et al. May 31, 2 | 2016-05-31 |
Methods of manufacturing semiconductor devices Grant 9,349,595 - Tsai , et al. May 24, 2 | 2016-05-24 |
Interconnect Structure and Method of Forming The Same App 20160118334 - Tsai; Cheng-Hsiung ;   et al. | 2016-04-28 |
Method Of Forming An Interconnect Structure For A Semiconductor Device App 20160099174 - Wu; Yung-Hsu ;   et al. | 2016-04-07 |
Air gap formation by damascene process Grant 9,299,603 - Tsai , et al. March 29, 2 | 2016-03-29 |
Integrated circuit formed using spacer-like copper deposition Grant 9,275,960 - Yao , et al. March 1, 2 | 2016-03-01 |
In situ chamber clean with inert hydrogen helium mixture during wafer process Grant 9,269,562 - Dinsmore , et al. February 23, 2 | 2016-02-23 |
Lithography Using High Selectivity Spacers for Pitch Reduction App 20160035571 - Chang; Yu-Sheng ;   et al. | 2016-02-04 |
Apparatus And Method For Reducing Substrate Sliding In Process Chambers App 20160020134 - THIRUNAVUKARASU; SRISKANTHARAJAH ;   et al. | 2016-01-21 |
Method For Integrated Circuit Patterning App 20160005617 - Wu; Chieh-Han ;   et al. | 2016-01-07 |
Spacer Etching Process for Integrated Circuit Design App 20160005614 - LIU; RU-GUN ;   et al. | 2016-01-07 |
Interconnect structure and method of forming the same Grant 9,230,911 - Tsai , et al. January 5, 2 | 2016-01-05 |
Self-Aligned Double Spacer Patterning Process App 20150380300 - Wu; Yung-Hsu ;   et al. | 2015-12-31 |
Semiconductor Device Manufacturing Methods App 20150340233 - Huang; Tsung-Min ;   et al. | 2015-11-26 |
Self-Aligned Double Spacer Patterning Process App 20150340240 - Tsai; Cheng-Hsiung ;   et al. | 2015-11-26 |
Lithography using high selectivity spacers for pitch reduction Grant 9,177,797 - Chang , et al. November 3, 2 | 2015-11-03 |
Spacer etching process for integrated circuit design Grant 9,153,478 - Liu , et al. October 6, 2 | 2015-10-06 |
Method for integrated circuit patterning Grant 9,136,106 - Wu , et al. September 15, 2 | 2015-09-15 |
Integrated Circuit Interconnects and Methods of Making Same App 20150255389 - Tsai; Cheng-Hsiung ;   et al. | 2015-09-10 |
Self-aligned double spacer patterning process Grant 9,129,906 - Wu , et al. September 8, 2 | 2015-09-08 |
Integrated circuit device having a copper interconnect Grant 9,129,967 - Tsai , et al. September 8, 2 | 2015-09-08 |
Self-aligned double spacer patterning process Grant 9,123,776 - Tsai , et al. September 1, 2 | 2015-09-01 |
Semiconductor device manufacturing methods Grant 9,099,400 - Huang , et al. August 4, 2 | 2015-08-04 |
Semiconductor Integrated Circuit With Nano Gap App 20150214143 - Tsai; Cheng-Hsiung ;   et al. | 2015-07-30 |
Interconnect Structure and Method of Forming the Same App 20150187696 - Tsai; Cheng-Hsiung ;   et al. | 2015-07-02 |
Method For Integrated Circuit Patterning App 20150179435 - Wu; Chieh-Han ;   et al. | 2015-06-25 |
Self-Aligned Double Spacer Patterning Process App 20150162205 - Wu; Yung-Hsu ;   et al. | 2015-06-11 |
Lithography Using High Selectivity Spacers for Pitch Reduction App 20150155171 - Chang; Yu-Sheng ;   et al. | 2015-06-04 |
Self-Aligned Double Spacer Patterning Process App 20150155198 - Tsai; Cheng-Hsiung ;   et al. | 2015-06-04 |
Semiconductor Patterning App 20150155184 - Tsai; Cheng-Hsiung ;   et al. | 2015-06-04 |
Pad Design For Electrostatic Chuck Surface App 20150146339 - RAJ; Govinda ;   et al. | 2015-05-28 |
Integrated circuit interconnects and methods of making same Grant 9,034,756 - Tsai , et al. May 19, 2 | 2015-05-19 |
Air Gap Formation by Damascene Process App 20150132952 - Tsai; Cheng-Hsiung ;   et al. | 2015-05-14 |
Semiconductor Device Manufacturing Methods App 20150093899 - Huang; Tsung-Min ;   et al. | 2015-04-02 |
Method of Semiconductor Integrated Circuit Fabrication App 20150056812 - Yao; Hsin-Chieh ;   et al. | 2015-02-26 |
Semiconductor patterning Grant 8,952,502 - Tsai , et al. February 10, 2 | 2015-02-10 |
In Situ Plasma Clean For Removal Of Residue From Pedestal Surface Without Breaking Vacuum App 20140366912 - GREEN; Richard J. ;   et al. | 2014-12-18 |
Addition of carboxyl groups plasma during etching for interconnect reliability enhancement Grant 8,901,007 - Tsai , et al. December 2, 2 | 2014-12-02 |
Method of fabricating an air gap using a damascene process and structure of same Grant 8,900,989 - Tsai , et al. December 2, 2 | 2014-12-02 |
In situ plasma clean for removal of residue from pedestal surface without breaking vacuum Grant 8,900,471 - Green , et al. December 2, 2 | 2014-12-02 |
Air-Gap Formation in Interconnect Structures App 20140349481 - Tsai; Cheng-Hsiung ;   et al. | 2014-11-27 |
Method of semiconducotr integrated circuit fabrication Grant 8,890,321 - Yao , et al. November 18, 2 | 2014-11-18 |
Air-gap formation in interconnect structures Grant 8,866,297 - Tsai , et al. October 21, 2 | 2014-10-21 |
Spacer Etching Process For Integrated Circuit Design App 20140273442 - Liu; Ru-Gun ;   et al. | 2014-09-18 |
Method Of Fabricating An Air Gap Using A Damascene Process And Structure Of Same App 20140252633 - Tsai; Cheng-Hsiung ;   et al. | 2014-09-11 |
Integrated Circuit Interconnects And Methods Of Making Same App 20140239501 - Tsai; Cheng-Hsiung ;   et al. | 2014-08-28 |
In Situ Chamber Clean With Inert Hydrogen Helium Mixture During Wafer Process App 20140196746 - Dinsmore; Robert ;   et al. | 2014-07-17 |
Addition Of Carboxyl Groups Plasma During Etching For Interconnect Reliability Enhancement App 20140187044 - Tsai; Cheng-Hsiung ;   et al. | 2014-07-03 |
Air-Gap Formation in Interconnect Structures App 20140151888 - Tsai; Cheng-Hsiung ;   et al. | 2014-06-05 |
Method of Semiconducotr integrated Circuit Fabrication App 20140138838 - Yao; Hsin-Chieh ;   et al. | 2014-05-22 |
Semiconductor Patterning App 20140138801 - Tsai; Cheng-Hsiung ;   et al. | 2014-05-22 |
Integrated Circuit Device Having A Copper Interconnect App 20140124932 - Tsai; Cheng-Hsiung ;   et al. | 2014-05-08 |
Integrated Circuit Formed Using Spacer-Like Copper Deposition App 20140084479 - Yao; Hsin-Chieh ;   et al. | 2014-03-27 |
Air-gap formation in interconnect structures Grant 8,664,743 - Tsai , et al. March 4, 2 | 2014-03-04 |
Integrated Circuit Interconnects and Methods of Making Same App 20140027908 - Tsai; Cheng-Hsiung ;   et al. | 2014-01-30 |
Methods of Manufacturing Semiconductor Devices App 20140017894 - Tsai; Cheng-Hsiung ;   et al. | 2014-01-16 |
Pvd Buffer Layers For Led Fabrication App 20130285065 - Zhu; Mingwei ;   et al. | 2013-10-31 |
Semiconductor patterning Grant 8,518,836 - Tsai , et al. August 27, 2 | 2013-08-27 |
Electrostatic chuck assembly Grant 8,390,980 - Sansoni , et al. March 5, 2 | 2013-03-05 |
Detachable electrostatic chuck for supporting a substrate in a process chamber Grant 7,907,384 - Brown , et al. March 15, 2 | 2011-03-15 |
In Situ Plasma Clean For Removal Of Residue From Pedestal Surface Without Breaking Vacuum App 20100218785 - Green; Richard J. ;   et al. | 2010-09-02 |
Detachable electrostatic chuck Grant 7,697,260 - Brown , et al. April 13, 2 | 2010-04-13 |
Electrostatic Chuck Assembly App 20100039747 - Sansoni; Steven V. ;   et al. | 2010-02-18 |
Detachable electrostatic chuck for supporting a substrate in a process chamber App 20090201622 - Brown; Karl ;   et al. | 2009-08-13 |
Oxygen plasma clean to remove carbon species deposited on a glass dome surface Grant 7,550,090 - Gu , et al. June 23, 2 | 2009-06-23 |
Detachable electrostatic chuck for supporting a substrate in a process chamber Grant 7,480,129 - Brown , et al. January 20, 2 | 2009-01-20 |
Oxygen Plasma Clean To Remove Carbon Species Deposited On A Glass Dome Surface App 20080173326 - GU; QUANCHENG ;   et al. | 2008-07-24 |
Detachable electrostatic chuck for supporting a substrate in a process chamber App 20060002053 - Brown; Karl ;   et al. | 2006-01-05 |
Detachable electrostatic chuck App 20050219786 - Brown, Karl ;   et al. | 2005-10-06 |
Pedestal assembly with enhanced thermal conductivity Grant 6,563,686 - Tsai , et al. May 13, 2 | 2003-05-13 |
Substrate support with multilevel heat transfer mechanism Grant 6,506,291 - Tsai , et al. January 14, 2 | 2003-01-14 |
Substrate Support With Multilevel Heat Transfer Mechanism App 20020189940 - Tsai, Cheng-Hsiung ;   et al. | 2002-12-19 |
Pedestal assembly with enhanced thermal conductivity App 20020129475 - Tsai, Cheng-Hsiung ;   et al. | 2002-09-19 |
Connectors For An Eletrostatic Chuck App 20020022403 - CHENG, WING L. ;   et al. | 2002-02-21 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.