Tran; Chanh Vi
Patent Applications and Registrations
Patent applications and USPTO patent grants for Tran; Chanh Vi.The latest application filed is for "delay locked loop circuitry for clock delay adjustment".
- Tran; Chanh Vi - San Jose CA
| Patent | Date |
|---|---|
| Delay locked loop circuitry for clock delay adjustment Grant 7,308,065 - Donnelly , et al. December 11, 2 | 2007-12-11 |
| Delay locked loop circuitry for clock delay adjustment App 20060188051 - Donnelly; Kevin S. ; et al. | 2006-08-24 |
| Delay locked loop circuitry for clock delay adjustment Grant 7,039,147 - Donnelly , et al. May 2, 2 | 2006-05-02 |
| Delay locked loop circuitry for clock delay adjustment App 20040223571 - Donnelly, Kevin S. ; et al. | 2004-11-11 |
| Delay locked loop circuitry for clock delay adjustment Grant 6,539,072 - Donnelly , et al. March 25, 2 | 2003-03-25 |
| Delay-locked loop circuitry for clock delay adjustment Grant 6,125,157 - Donnelly , et al. September 26, 2 | 2000-09-26 |
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