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Toyama; Fumiaki Patent Filings

Toyama; Fumiaki

Patent Applications and Registrations

Patent applications and USPTO patent grants for Toyama; Fumiaki.The latest application filed is for "three-dimensional memory device having support-die-assisted source power distribution and method of making thereof".

Company Profile
21.54.43
  • Toyama; Fumiaki - Cupertino CA
  • Toyama; Fumiaki - San Jose CA
  • Toyama; Fumiaki - Fukushima-ken JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Non-volatile memory with different use of metal lines in word line hook up regions
Grant 11,424,207 - Shao , et al. August 23, 2
2022-08-23
Non-volatile memory with multiple wells for word line switch transistors
Grant 11,404,123 - Shao , et al. August 2, 2
2022-08-02
Bonded assembly of semiconductor dies containing pad level across-die metal wiring and method of forming the same
Grant 11,342,244 - Kim , et al. May 24, 2
2022-05-24
Three-dimensional memory device containing multiple size drain contact via structures and method of making same
Grant 11,251,191 - Weng , et al. February 15, 2
2022-02-15
Three-dimensional Memory Device Having Support-die-assisted Source Power Distribution And Method Of Making Thereof
App 20220013518 - KIM; Kwang-Ho ;   et al.
2022-01-13
Bonded assembly with vertical power and control signal connection adjacent to sense amplifier regions and methods of forming the same
Grant 11,211,370 - Kim , et al. December 28, 2
2021-12-28
Three-dimensional memory device containing horizontal and vertical word line interconnections and methods of forming the same
Grant 11,139,237 - Shao , et al. October 5, 2
2021-10-05
Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof
Grant 11,133,297 - Kim , et al. September 28, 2
2021-09-28
Three-dimensional memory device containing width-modulated connection strips and methods of forming the same
Grant 11,114,459 - Iwai , et al. September 7, 2
2021-09-07
Multi-tier three-dimensional memory device containing dielectric well structures for contact via structures and methods of forming the same
Grant 11,081,443 - Mizutani , et al. August 3, 2
2021-08-03
Bonded Assembly With Vertical Power And Control Signal Connection Adjacent To Sense Amplifier Regions And Methods Of Forming The Same
App 20210233900 - KIM; Jee-Yeon ;   et al.
2021-07-29
Bonded Assembly Of Semiconductor Dies Containing Pad Level Across-die Metal Wiring And Method Of Forming The Same
App 20210225736 - KIM; Jee-Yeon ;   et al.
2021-07-22
Three-dimensional memory device including contact-level bit-line-connection structures and methods of making the same
Grant 11,011,209 - Kim , et al. May 18, 2
2021-05-18
Three-dimensional Memory Device Containing Width-modulated Connection Strips And Methods Of Forming The Same
App 20210134827 - IWAI; Takaaki ;   et al.
2021-05-06
Word line decoder circuitry under a three-dimensional memory array
Grant 10,991,429 - Ogawa , et al. April 27, 2
2021-04-27
Three-dimensional Memory Device Including Contact-level Bit-line-connection Structures And Methods Of Making The Same
App 20210098029 - KIM; Jee-Yeon ;   et al.
2021-04-01
Three-dimensional Memory Device Containing Horizontal And Vertical Word Line Interconnections And Methods Of Forming The Same
App 20210057336 - SHAO; Shiqian ;   et al.
2021-02-25
Three-dimensional memory device including signal and power connection lines extending through dielectric regions and methods of making the same
Grant 10,872,899 - Kim , et al. December 22, 2
2020-12-22
Three-dimensional memory device including signal and power connection lines extending through dielectric regions and methods of making the same
Grant 10,861,873 - Kim , et al. December 8, 2
2020-12-08
Through-array conductive via structures for a three-dimensional memory device and methods of making the same
Grant 10,840,260 - Kai , et al. November 17, 2
2020-11-17
Three-dimensional Memory Device Including Signal And Power Connection Lines Extending Through Dielectric Regions And Methods Of Making The Same
App 20200357811 - KIM; Jee-Yeon ;   et al.
2020-11-12
Three-dimensional Memory Device Including Signal And Power Connection Lines Extending Through Dielectric Regions And Methods Of Making The Same
App 20200357814 - KIM; Jee-Yeon ;   et al.
2020-11-12
Word Line Decoder Circuitry Under A Three-dimensional Memory Array
App 20200294599 - OGAWA; Hiroyuki ;   et al.
2020-09-17
Increased terrace configuration for non-volatile memory
Grant 10,726,921 - Hsiung , et al.
2020-07-28
Through-array Conductive Via Structures For A Three-dimensional Memory Device And Methods Of Making The Same
App 20200235120 - KAI; James ;   et al.
2020-07-23
Word line decoder circuitry under a three-dimensional memory array
Grant 10,720,213 - Ogawa , et al.
2020-07-21
Three-dimensional Memory Device Containing Multiple Size Drain Contact Via Structures And Method Of Making Same
App 20200203365 - WENG; Lishan ;   et al.
2020-06-25
Memory die having wafer warpage reduction through stress balancing employing rotated three-dimensional memory arrays and method of making the same
Grant 10,658,381 - Yu , et al.
2020-05-19
Three-dimensional memory device containing dummy antenna diodes
Grant 10,580,787 - Nishikawa , et al.
2020-03-03
Three-dimensional Memory Device Having Support-die-assisted Source Power Distribution And Method Of Making Thereof
App 20200066703 - KIM; Kwang-Ho ;   et al.
2020-02-27
Three-dimensional memory device having support-die-assisted source power distribution and method of making thereof
Grant 10,510,738 - Kim , et al. Dec
2019-12-17
Three-dimensional Memory Device Containing Antenna Diodes And Method Of Making Thereof
App 20190371800 - NISHIKAWA; Masatoshi ;   et al.
2019-12-05
Through-memory-level via structures for a three-dimensional memory device
Grant 10,381,371 - Ogawa , et al. A
2019-08-13
Three-dimensional Memory Device Having Support-die-assisted Source Power Distribution And Method Of Making Thereof
App 20190221557 - KIM; Kwang-Ho ;   et al.
2019-07-18
Metal contact via structure surrounded by an air gap and method of making thereof
Grant 10,319,680 - Sel , et al.
2019-06-11
Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof
Grant 10,256,248 - Lu , et al.
2019-04-09
Increased Terrace Configuration For Non-volatile Memory
App 20190088335 - Hsiung; Chia-Lin ;   et al.
2019-03-21
Word Line Decoder Circuitry under a Three-Dimensional Memory Array
App 20190057741 - OGAWA; Hiroyuki ;   et al.
2019-02-21
Three-dimensional memory device having non-uniform spacing among memory stack structures and method of making thereof
Grant 9,929,174 - Mizutani , et al. March 27, 2
2018-03-27
Architecture for CMOS under array
Grant 9,922,716 - Hsiung , et al. March 20, 2
2018-03-20
Three-dimensional memory device containing separately formed drain select transistors and method of making thereof
Grant 9,922,987 - Mizutani , et al. March 20, 2
2018-03-20
Field effect transistor with elevated active regions and methods of manufacturing the same
Grant 9,859,422 - Nishikawa , et al. January 2, 2
2018-01-02
Through-memory-level Via Structures Between Staircase Regions In A Three-dimensional Memory Device And Method Of Making Thereof
App 20170352678 - LU; Zhenyu ;   et al.
2017-12-07
Through-memory-level via structures for a three-dimensional memory device
Grant 9,818,693 - Toyama , et al. November 14, 2
2017-11-14
Through-memory-level via structures for a three-dimensional memory device
Grant 9,806,093 - Toyama , et al. October 31, 2
2017-10-31
Architecture For Cmos Under Array
App 20170309339 - Hsiung; Chia-Lin ;   et al.
2017-10-26
Three dimensional memory device having well contact pillar and method of making thereof
Grant 9,768,186 - Shimabukuro , et al. September 19, 2
2017-09-19
Word Line Decoder Circuitry Under A Three-dimensional Memory Array
App 20170243650 - OGAWA; Hiroyuki ;   et al.
2017-08-24
Word line decoder circuitry under a three-dimensional memory array
Grant 9,721,663 - Ogawa , et al. August 1, 2
2017-08-01
Through-memory-level Via Structures For A Three-dimensional Memory Device
App 20170179026 - Toyama; Fumiaki ;   et al.
2017-06-22
Through-memory-level Via Structures For A Three-dimensional Memory Device
App 20170179152 - TOYAMA; Fumiaki ;   et al.
2017-06-22
Through-memory-level Via Structures For A Three-dimensional Memory Device
App 20170179153 - OGAWA; Hiroyuki ;   et al.
2017-06-22
Field Effect Transistor With A Multilevel Gate Electrode For Integration With A Multilevel Memory Device
App 20170125430 - NISHIKAWA; Masatoshi ;   et al.
2017-05-04
Field effect transistor with a multilevel gate electrode for integration with a multilevel memory device
Grant 9,620,512 - Nishikawa , et al. April 11, 2
2017-04-11
Field Effect Transistor With Elevated Active Regions And Methods Of Manufacturing The Same
App 20160351709 - NISHIKAWA; Masatoshi ;   et al.
2016-12-01
Three Dimensional Memory Device Having Well Contact Pillar And Method Of Making Thereof
App 20160329341 - Shimabukuro; Seiji ;   et al.
2016-11-10
Conductive line structure with openings
Grant 9,478,461 - Shishido , et al. October 25, 2
2016-10-25
Non-volatile storage systems and methods
Grant 9,449,701 - Hsiung , et al. September 20, 2
2016-09-20
Three dimensional memory device having well contact pillar and method of making thereof
Grant 9,412,749 - Shimabukuro , et al. August 9, 2
2016-08-09
Methods For Reducing Body Effect And Increasing Junction Breakdown Voltage
App 20160118128 - Hsiung; Chia-Lin ;   et al.
2016-04-28
Methods for reducing body effect and increasing junction breakdown voltage
Grant 9,312,015 - Hsiung , et al. April 12, 2
2016-04-12
Conductive Line Structure with Openings
App 20160086848 - Shishido; Kiyokazu ;   et al.
2016-03-24
NAND flash memory integrated circuits and processes with controlled gate height
Grant 9,245,898 - Fujikura , et al. January 26, 2
2016-01-26
NAND Flash Memory Integrated Circuits and Processes with Controlled Gate Height
App 20150380420 - Fujikura; Eiichi ;   et al.
2015-12-31
Wide and narrow patterning using common process
Grant 9,224,744 - Yokota , et al. December 29, 2
2015-12-29
Vertical NAND device with shared word line steps
Grant 9,224,747 - Mizutani , et al. December 29, 2
2015-12-29
Non-volatile memory including bit line switch transistors formed in a triple-well
Grant 9,208,889 - Toyama , et al. December 8, 2
2015-12-08
Vertical Nand Device With Shared Word Line Steps
App 20150279852 - Mizutani; Yuki ;   et al.
2015-10-01
System to reduce stress on word line select transistor during erase operation
Grant 9,142,305 - Dunga , et al. September 22, 2
2015-09-22
Bit line resistance compensation
Grant 8,988,917 - Kim , et al. March 24, 2
2015-03-24
Back-biasing word line switch transistors
Grant 8,917,554 - Toyama , et al. December 23, 2
2014-12-23
Non-Volatile Memory Including Bit Line Switch Transistors Formed In A Triple-Well
App 20140226415 - Toyama; Fumiaki ;   et al.
2014-08-14
Bit Line Resistance Compensation
App 20140133231 - Kim; Kwang Ho ;   et al.
2014-05-15
Semiconductor device and method for manufacturing thereof
Grant 8,669,606 - Toyama , et al. March 11, 2
2014-03-11
System To Reduce Stress On Word Line Select Transistor During Erase Operation
App 20140003150 - Dunga; Mohan Vamsi ;   et al.
2014-01-02
Semiconductor device and method for manufacturing
Grant 8,552,523 - Toyama , et al. October 8, 2
2013-10-08
Semiconductor device and method for controlling
Grant 8,537,622 - Toyama , et al. September 17, 2
2013-09-17
Back-biasing Word Line Switch Transistors
App 20130107627 - Toyama; Fumiaki ;   et al.
2013-05-02
Semiconductor Device And Method For Controlling
App 20130064024 - Toyama; Fumiaki ;   et al.
2013-03-14
Semiconductor Device And Method For Manufacturing
App 20110291227 - TOYAMA; Fumiaki ;   et al.
2011-12-01
Semiconductor Device And Method For Manufacturing Thereof
App 20110233638 - TOYAMA; Fumiaki ;   et al.
2011-09-29
Semiconductor device and method for controlling
Grant 8,004,901 - Toyama , et al. August 23, 2
2011-08-23
Semiconductor device and method for manufacturing
Grant 7,994,007 - Toyama , et al. August 9, 2
2011-08-09
Semiconductor device and method for manufacturing thereof
Grant 7,981,746 - Toyama , et al. July 19, 2
2011-07-19
Mirror bit memory device applying a gate voltage alternately to gate
Grant 7,956,424 - Toyama June 7, 2
2011-06-07
Semiconductor device and method for manufacturing
Grant 7,902,592 - Mikasa , et al. March 8, 2
2011-03-08
Semiconductor Device And Method For Controlling
App 20100002517 - TOYAMA; Fumiaki ;   et al.
2010-01-07
Semiconductor Device And Method For Manufacturing Thereof
App 20090321812 - TOYAMA; Fumiaki ;   et al.
2009-12-31
Semiconductor Device And Method For Manufacturing
App 20090315098 - Toyama; Fumiaki ;   et al.
2009-12-24
Semiconductor Device And Method For Manufacturing
App 20090315097 - MIKASA; Yoshihiro ;   et al.
2009-12-24
Mirror Bit Memory Device Applying A Gate Voltage Alternately To Gate
App 20090212348 - TOYAMA; Fumiaki
2009-08-27

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