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Method of preparing a semiconductor substrate utilizing plural implants under an isolation region to isolate adjacent wells Grant 7,662,690 - Tang , et al. February 16, 2 | 2010-02-16 |
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Design method and system for optimum performance in integrated circuits that use power management Grant 7,216,310 - Chatterjee , et al. May 8, 2 | 2007-05-08 |
Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) Grant 7,045,436 - Chatterjee , et al. May 16, 2 | 2006-05-16 |
Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) App 20060024910 - Chatterjee; Amitava ;   et al. | 2006-02-02 |
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Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance Grant 6,930,007 - Bu , et al. August 16, 2 | 2005-08-16 |
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Design method and system for optimum performance in integrated circuits that use power management App 20050149887 - Chatterjee, Amitava ;   et al. | 2005-07-07 |
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Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance App 20050059228 - Bu, Haowen ;   et al. | 2005-03-17 |
Process to reduce gate edge drain leakage in semiconductor devices Grant 6,855,984 - Wu , et al. February 15, 2 | 2005-02-15 |
High performance PNP bipolar device fully compatible with CMOS process Grant 6,794,730 - Kim , et al. September 21, 2 | 2004-09-21 |
Methods for improving well to well isolation App 20040097051 - Wu, Zhiqiang ;   et al. | 2004-05-20 |
High-dielectric constant capacitor and memory Grant 6,462,931 - Tang , et al. October 8, 2 | 2002-10-08 |
High performance PNP bipolar device fully compatible with CMOS process App 20020084495 - Kim, Youngmin ;   et al. | 2002-07-04 |