Sun; Sey-Shing

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sun; Sey-Shing.The latest application filed is for "low voltage embedded memory having conductive oxide and electrode stacks".

Company Profile

0.37.26

Sun; Sey-Shing - Portland OR US
Sun, Sey-Shing - Beaverton OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Low voltage embedded memory having conductive oxide and electrode stacks Grant 9,647,208 - Karpov , et al. May 9, 2	2017-05-09
Low Voltage Embedded Memory Having Conductive Oxide And Electrode Stacks App 20160079523 - Karpov; Elijah V. ; et al.	2016-03-17
Low voltage embedded memory having conductive oxide and electrode stacks Grant 9,231,204 - Karpov , et al. January 5, 2	2016-01-05
Low Voltage Embedded Memory Having Conductive Oxide And Electrode Stacks App 20140092666 - Karpov; Elijah V. ; et al.	2014-04-03
Alternate Pad Structures/passivation Integration Schemes To Reduce Or Eliminate Imc Cracking In Post Wire Bonded Dies During Cu/low-k Beol Processing App 20140030541 - Bhatt; Hemanshu ; et al.	2014-01-30
Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing Grant 8,552,560 - Bhatt , et al. October 8, 2	2013-10-08
Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow Grant 8,384,165 - Carter , et al. February 26, 2	2013-02-26
Reduction of macro level stresses in copper/low-K wafers Grant 8,076,779 - Sun , et al. December 13, 2	2011-12-13
Bi-axial texturing of high-K dielectric films to reduce leakage currents Grant 7,956,401 - Lo , et al. June 7, 2	2011-06-07
Self-aligned cell integration scheme Grant 7,915,122 - Carter , et al. March 29, 2	2011-03-29
Bi-axial Texturing Of High-k Dielectric Films To Reduce Leakage Currents App 20100022060 - LO; Wai ; et al.	2010-01-28
Bi-axial texturing of high-K dielectric films to reduce leakage currents Grant 7,619,272 - Lo , et al. November 17, 2	2009-11-17
Method for redirecting void diffusion away from vias in an integrated circuit design Grant 7,582,566 - Allman , et al. September 1, 2	2009-09-01
Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing Grant 7,531,442 - Pallinti , et al. May 12, 2	2009-05-12
Application Of Gate Edge Liner To Maintain Gate Length Cd In A Replacement Gate Transistor Flow App 20080308882 - Carter; Richard J. ; et al.	2008-12-18
Method and apparatus for diverting void diffusion in integrated circuit conductors Grant 7,436,040 - Allman , et al. October 14, 2	2008-10-14
Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow Grant 7,405,116 - Carter , et al. July 29, 2	2008-07-29
Nano structure electrode design Grant 7,402,770 - Sun , et al. July 22, 2	2008-07-22
DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIAL App 20080150090 - Lin; Hong ; et al.	2008-06-26
Method For Redirecting Void Diffusion Away From Vias In An Integrated Circuit Design App 20080132065 - Allman; Derryl D. J. ; et al.	2008-06-05
Damascene replacement metal gate process with controlled gate profile and length using Si.sub.1-xGe.sub.x as sacrificial material Grant 7,365,015 - Lin , et al. April 29, 2	2008-04-29
Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design Grant 7,361,965 - Allman , et al. April 22, 2	2008-04-22
Incorporating dopants to enhance the dielectric properties of metal silicates Grant 7,312,127 - Lo , et al. December 25, 2	2007-12-25
Integrated barrier and seed layer for copper interconnect technology Grant 7,300,869 - Sun , et al. November 27, 2	2007-11-27
Method and apparatus for diverting void diffusion in integrated circuit conductors App 20070259518 - Allman; Derryl D.J. ; et al.	2007-11-08
Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design App 20070155160 - Allman; Derryl D. J. ; et al.	2007-07-05
Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing App 20070123024 - Pallinti; Jayanthi ; et al.	2007-05-31
Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing App 20070114667 - Bhatt; Hemanshu ; et al.	2007-05-24
Reduction of macro level stresses in copper/Low-K wafers by altering aluminum pad/passivation stack to reduce or eliminate IMC cracking in post wire bonded dies App 20070102812 - Sun; Sey-Shing ; et al.	2007-05-10
Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing Grant 7,205,673 - Pallinti , et al. April 17, 2	2007-04-17
Method and structure for creating ultra low resistance damascene copper wiring Grant 7,196,420 - Burke , et al. March 27, 2	2007-03-27
Method for fabricating planar semiconductor wafers Grant 7,179,736 - Kwak , et al. February 20, 2	2007-02-20
Self-aligned cell integration scheme App 20060281256 - Carter; Richard J. ; et al.	2006-12-14
Nano structure electrode design App 20060278902 - Sun; Sey-Shing ; et al.	2006-12-14
Incorporating dopants to enhance the dielectric properties of metal silicates App 20060166496 - Lo; Wai ; et al.	2006-07-27
Incorporating dopants to enhance the dielectric properties of metal silicates Grant 7,064,062 - Lo , et al. June 20, 2	2006-06-20
Bi-axial texturing of high-K dielectric films to reduce leakage currents App 20060118919 - Lo; Wai ; et al.	2006-06-08
Method for fabricating planar semiconductor wafers App 20060084267 - Kwak; Byung-Sung Leo ; et al.	2006-04-20
Integrated barrier and seed layer for copper interconnect technology App 20060063375 - Sun; Sey-Shing ; et al.	2006-03-23
Bimetallic oxide compositions for gate dielectrics Grant 7,015,096 - Zubkov , et al. March 21, 2	2006-03-21
Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow App 20060035425 - Carter; Richard J. ; et al.	2006-02-16
Method for creating barrier layers for copper diffusion Grant 6,998,343 - Sun , et al. February 14, 2	2006-02-14
Damascene replacement metal gate process with controlled gate profile and length using Si1-xGex as sacrificial material App 20060011994 - Lin; Hong ; et al.	2006-01-19
Method and structure for creating ultra low resistance damascene copper wiring Grant 6,987,059 - Burke , et al. January 17, 2	2006-01-17
Carbon nanotube memory cell for integrated circuit structure with removable side spacers to permit access to memory cell and process for forming such memory cell Grant 6,955,937 - Burke , et al. October 18, 2	2005-10-18
Method for improved local planarity control during electropolishing App 20050224358 - Kwak, Byung-Sung ; et al.	2005-10-13
Incorporating dopants to enhance the dielectric properties of metal silicates App 20050127458 - Lo, Wai ; et al.	2005-06-16
Method of fabricating an alloy cap layer over CU wires to improve electromigration performance of CU interconnects App 20040207093 - Sun, Sey-Shing ; et al.	2004-10-21
Thin-film electroluminescent phosphor App 20020043925 - Sun, Sey-Shing ; et al.	2002-04-18
Electroluminescent phosphor thin films with increased brightness that includes an alkali halide Grant 6,169,359 - Sun , et al. January 2, 2	2001-01-02
Alternating current thin film electroluminescent device having blue light emitting alkaline earth phosphor Grant 6,043,602 - Sun , et al. March 28, 2	2000-03-28
Alternating current thin film electroluminescent device having blue light emitting alkaline earth phosphor Grant 5,939,825 - Sun , et al. August 17, 1	1999-08-17
TFEL phosphor having metal overlayer Grant 5,677,594 - Sun , et al. October 14, 1	1997-10-14
Oxygen-doped thiogallate phosphor Grant 5,656,888 - Sun , et al. August 12, 1	1997-08-12
TFEL device with injection layer Grant 5,581,150 - Rack , et al. December 3, 1	1996-12-03
Multi-source reactive deposition process for the preparation of blue light emitting phosphor layers for AC TFEL devices Grant 5,505,986 - Velthaus , et al. April 9, 1	1996-04-09
AC TFEL device having blue light emitting thiogallate phosphor Grant 5,309,070 - Sun , et al. May 3, 1	1994-05-03

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