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Multiple patterning with mandrel cuts defined by block masks
Grant 11,417,525 - O'Toole , et al. August 16, 2 | 2022-08-16 |
Structure and method to improve overlay performance in semiconductor devices
Grant 10,833,022 - Tran , et al. November 10, 2 | 2020-11-10 |
Multiple patterning with lithographically-defined cuts
Grant 10,784,119 - Srivastava , et al. Sept | 2020-09-22 |
Chamferless interconnect vias of semiconductor devices
Grant 10,770,344 - Ren , et al. Sep | 2020-09-08 |
Chamferless Interconnect Vias Of Semiconductor Devices
App 20200219763 - REN; YUPING ; et al. | 2020-07-09 |
Interconnects with variable space mandrel cuts formed by block patterning
Grant 10,692,812 - Srivastava , et al. | 2020-06-23 |
Multiple Patterning With Mandrel Cuts Defined By Block Masks
App 20200111668 - O'Toole; Martin ; et al. | 2020-04-09 |
Multiple Patterning With Lithographically-defined Cuts
App 20200111677 - Srivastava; Ravi Prakash ; et al. | 2020-04-09 |
Structure And Method To Improve Overlay Performance In Semiconductor Devices
App 20200051923 - Tran; Cung D. ; et al. | 2020-02-13 |
Structure and method to improve overlay performance in semiconductor devices
Grant 10,504,851 - Tran , et al. Dec | 2019-12-10 |
Interconnects With Variable Space Mandrel Cuts Formed By Block Patterning
App 20190355658 - Srivastava; Ravi Prakash ; et al. | 2019-11-21 |
Structure And Method To Improve Overlay Performance In Semiconductor Devices
App 20190267329 - Tran; Cung D. ; et al. | 2019-08-29 |
Air Gap Formation In Back-end-of-line Structures
App 20190237356 - Srivastava; Ravi Prakash ; et al. | 2019-08-01 |
Dual Developing Methods For Lithography Patterning
App 20190079408 - Mehta; Sohan Singh ; et al. | 2019-03-14 |
Self-aligned multiple patterning processes using bi-layer mandrels and cuts formed with block masks
Grant 10,192,780 - Wang , et al. Ja | 2019-01-29 |
Methods And Devices For Metal Filling Processes
App 20170186688 - SINGH; Sunil Kumar ; et al. | 2017-06-29 |
Methods and devices for back end of line via formation
Grant 9,691,654 - Singh , et al. June 27, 2 | 2017-06-27 |
Methods And Devices For Back End Of Line Via Formation
App 20170178953 - SINGH; Sunil Kumar ; et al. | 2017-06-22 |
Methods and devices for metal filling processes
Grant 9,613,909 - Singh , et al. April 4, 2 | 2017-04-04 |
Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same
Grant 9,576,894 - Singh , et al. February 21, 2 | 2017-02-21 |
Methods And Devices For Metal Filling Processes
App 20170047290 - SINGH; Sunil Kumar ; et al. | 2017-02-16 |
Integrated Circuits Including Organic Interlayer Dielectric Layers And Methods For Fabricating The Same
App 20160358851 - Singh; Sunil Kumar ; et al. | 2016-12-08 |
Methods of fabricating BEOL interlayer structures
Grant 9,362,162 - Singh , et al. June 7, 2 | 2016-06-07 |
Methods Of Fabricating Beol Interlayer Structures
App 20160049327 - SINGH; Sunil Kumar ; et al. | 2016-02-18 |
Method to reduce depth delta between dense and wide features in dual damascene structures
Grant 8,822,342 - Srivastava , et al. September 2, 2 | 2014-09-02 |
Integrated circuit system with ultra-low k dielectric and method of manufacture thereof
Grant 8,420,947 - Srivastava April 16, 2 | 2013-04-16 |
Method To Reduce Depth Delta Between Dense And Wide Features In Dual Damascene Structures
App 20120168957 - SRIVASTAVA; Ravi Prakash ; et al. | 2012-07-05 |
Integrated Circuit System With Ultra-low K Dielectric And Method Of Manufacture Thereof
App 20120168203 - Srivastava; Ravi Prakash | 2012-07-05 |
Method to improve reliability (EM and TDDB) with post silylation plasma treatment process for copper damascene structures
App 20120100716 - Srivastava; Ravi Prakash ; et al. | 2012-04-26 |
Methods and structures to enable self-aligned via etch for Cu damascene structure using trench first metal hard mask (TFMHM) scheme
Grant 8,114,769 - Srivastava , et al. February 14, 2 | 2012-02-14 |
Methods of patterning insulating layers using etching techniques that compensate for etch rate variations
Grant 8,058,176 - Park , et al. November 15, 2 | 2011-11-15 |
Method Of Minimizing Via Sidewall Damages During Dual Damascene Trench Reactive Ion Etching In A Via First Scheme
App 20090087992 - SRIVASTAVA; Ravi Prakash ; et al. | 2009-04-02 |
Methods of Patterning Insulating Layers Using Etching Techniques that Compensate for Etch Rate Variations
App 20090081873 - Park; Wan-jae ; et al. | 2009-03-26 |
Generation of three dimensional fractal subsurface structure by Voronoi Tessellation and computation of gravity response of such fractal structure
App 20040201585 - Srivastava, Ravi Prakash ; et al. | 2004-10-14 |
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