SINHA; Anubhav

Patent Applications and Registrations

Patent applications and USPTO patent grants for SINHA; Anubhav.The latest application filed is for "device under test synchronization with automated test equipment check cycle".

Company Profile

5.4.8

SINHA; Anubhav - Hyderabad IN
Sinha; Anubhav - Cambridge MA
Sinha; Anubhav - Telangana IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Device Under Test Synchronization With Automated Test Equipment Check Cycle App 20220155370 - HU; Yongkang ; et al.	2022-05-19
High-speed Functional Protocol Based Test And Debug App 20220120811 - SINHA; Anubhav ; et al.	2022-04-21
Packetized Power-on-self-test Controller For Built-in Self-test App 20220108760 - SINHA; Anubhav ; et al.	2022-04-07
Test architecture for die to die interconnect for three dimensional integrated circuits Grant 11,257,560 - Chakravarty , et al. February 22, 2	2022-02-22
Multiplexed Signal Amplified FISH Via Splinted Ligation Amplification and Sequencing App 20210395796 - Chen; Fei ; et al.	2021-12-23
Multiplexed signal amplified FISH via splinted ligation amplification and sequencing Grant 10,995,361 - Chen , et al. May 4, 2	2021-05-04
Dynamic independent test partition clock Grant 10,473,720 - Datla Jagannadha , et al. Nov	2019-11-12
Design For Test Architecture For Die To Die Interconnect For Three Dimensional Integrated Circuits App 20190096503 - CHAKRAVARTY; Sreejit ; et al.	2019-03-28
Multiplexed Signal Amplified FISH via Splinted Ligation Amplification and Sequencing App 20180216161 - Chen; Fei ; et al.	2018-08-02
Dynamic Independent Test Partition Clock App 20170115351 - Datla Jagannadha; Pavan Kumar ; et al.	2017-04-27
Global low power capture scheme for cores Grant 9,222,981 - Puvvada , et al. December 29, 2	2015-12-29
Global Low Power Capture Scheme For Cores App 20140189454 - Puvvada; Satya ; et al.	2014-07-03

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