Shirasu; Tetsuya

Patent Applications and Registrations

Patent applications and USPTO patent grants for Shirasu; Tetsuya.The latest application filed is for "bonded structure including a performance-optimized support chip and a stress-optimized three-dimensional memory chip and method ".

Company Profile

3.9.13

Shirasu; Tetsuya - Yokkaichi JP
Shirasu; Tetsuya - Kawasaki N/A JP
SHIRASU; Tetsuya - Yokohama JP
Shirasu; Tetsuya - Tokyo JP
Shirasu; Tetsuya - Kawasaki-Shi JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Bonded structure including a performance-optimized support chip and a stress-optimized three-dimensional memory chip and method for making the same Grant 11,011,506 - Hosoda , et al. May 18, 2	2021-05-18
Bonded Structure Including A Performance-optimized Support Chip And A Stress-optimized Three-dimensional Memory Chip And Method App 20200258876 - A1	2020-08-13
Bonded structure including a performance-optimized support chip and a stress-optimized three-dimensional memory chip and method for making the same Grant 10,665,580 - Hosoda , et al.	2020-05-26
Method for fabricating semiconductor device Grant 8,991,042 - Sakamoto , et al. March 31, 2	2015-03-31
Method For Fabricating Semiconductor Device App 20130012019 - SAKAMOTO; Manabu ; et al.	2013-01-10
Polishing Pad And Method Of Fabricating Semiconductor Device App 20120196512 - SHIRASU; Tetsuya	2012-08-02
Method for manufacturing semiconductor device and polisher used in the method for manufacturing semiconductor device Grant 7,842,614 - Kanki , et al. November 30, 2	2010-11-30
Semiconductor Device Fabricating Method, And Semiconductor Fabricating Device App 20100035523 - Shirasu; Tetsuya ; et al.	2010-02-11
Polishing Machine, Workpiece Supporting Table Pad, Polishing Method And Manufacturing Method Of Semiconductor Device App 20090264054 - SHIRASU; Tetsuya ; et al.	2009-10-22
Fabrication process of semiconductor device and polishing method Grant 7,597,606 - Shirasu October 6, 2	2009-10-06
Method For Fabricating Semiconductor Device App 20090056102 - SAKAMOTO; Manabu ; et al.	2009-03-05
Method For Manufacturing Semiconductor Device And Polisher Used In The Method For Manufacturing Semiconductor Device App 20080166877 - Kanki; Tsuyoshi ; et al.	2008-07-10
Fabrication process of semiconductor device and polishing method App 20080146128 - Shirasu; Tetsuya	2008-06-19
Semiconductor device manufacture method App 20080119050 - Shirasu; Tetsuya ; et al.	2008-05-22
Fabrication process of semiconductor device and polishing method Grant 7,348,276 - Shirasu March 25, 2	2008-03-25
Semiconductor device manufacture method Grant 7,338,905 - Shirasu , et al. March 4, 2	2008-03-04
Polishing machine, workpiece supporting table pad, polishing method and manufacturing method of semiconductor device Grant 7,258,599 - Shirasu August 21, 2	2007-08-21
Polishing machine, workpiece supporting table pad, polishing method and manufacturing method of semiconductor device App 20070123047 - Shirasu; Tetsuya ; et al.	2007-05-31
Polishing Machine, Workpiece Supporting Table Pad, Polishing Method And Manufacturing Method Of Semiconductor Device App 20070060024 - Shirasu; Tetsuya ; et al.	2007-03-15
Fabrication process of semiconductor device and polishing method App 20060219662 - Shirasu; Tetsuya	2006-10-05
Semiconductor device manufacture method App 20050159005 - Shirasu, Tetsuya ; et al.	2005-07-21

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