Sequence Design, Inc.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sequence Design, Inc..The latest application filed is for "automatic voltage drop optimization".

Company Profile

0.24.6

Sequence Design, Inc. - Sunnyvale CA
Sequence Design, Inc. - Santa Clara CA
Sequence Design, Inc. -

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks

Patent Activity

Patent	Date
Design method and architecture for power gate switch placement Grant 7,590,962 - Frenkil , et al. September 15, 2	2009-09-15
Design method and architecture for power gate switch placement and interconnection using tapless libraries Grant 7,509,613 - Frenkil March 24, 2	2009-03-24
Automatic Voltage Drop Optimization App 20080098335 - Allen; David L. ; et al.	2008-04-24
Automatic extension of clock gating technique to fine-grained power gating Grant 7,323,909 - Mamidipaka January 29, 2	2008-01-29
Design method and architecture for power gate switch placement and interconnection using tapless libraries App 20070168899 - Frenkil; Gerald L.	2007-07-19
Method and apparatus for interconnect-driven optimization of integrated circuit design Grant 7,222,311 - Kaufman , et al. May 22, 2	2007-05-22
Circuit optimization for minimum path timing violations Grant 7,222,318 - Srinivasan May 22, 2	2007-05-22
Vectorless instantaneous current estimation Grant 7,185,300 - Frenkil February 27, 2	2007-02-27
Automatic extension of clock gating technique to fine-grained power gating App 20070024318 - Mamidipaka; Mahesh	2007-02-01
Current scheduling system and method for optimizing multi-threshold CMOS designs Grant 7,117,457 - Frenkil October 3, 2	2006-10-03
Method for determining load capacitance Grant 7,003,741 - Srinivasan February 21, 2	2006-02-21
Current scheduling system and method for optimizing multi-threshold CMOS designs App 20050138588 - Frenkil, Gerald L.	2005-06-23
RTL power analysis using gate-level cell power models Grant 6,901,565 - Sokolov May 31, 2	2005-05-31
Vectorless instantaneous current estimation Grant 6,807,660 - Frenkil October 19, 2	2004-10-19
Method for optimal driver selection Grant 6,754,877 - Srinivasan June 22, 2	2004-06-22
Circuit optimization for minimum path timing violations App 20040088664 - Srinivasan, Adi	2004-05-06
Method for match delay buffer insertion Grant 6,701,506 - Srinivasan , et al. March 2, 2	2004-03-02
Circuit optimization for minimum path timing violations Grant 6,701,505 - Srinivasan March 2, 2	2004-03-02
Method for determining a zero-skew buffer insertion point Grant 6,701,507 - Srinivasan March 2, 2	2004-03-02
Method for balanced-delay clock tree insertion Grant 6,698,006 - Srinivasan , et al. February 24, 2	2004-02-24
Method and system for extraction of parasitic interconnect impedance including inductance Grant 6,643,831 - Chang , et al. November 4, 2	2003-11-04
Method and apparatus for interconnect-driven optimization of integrated circuit design App 20030177455 - Kaufman, Douglas ; et al.	2003-09-18
RTL power analysis using gate-level cell power models Grant 6,598,209 - Sokolov July 22, 2	2003-07-22
Method and apparatus for interconnect-driven optimization of integrated circuit design Grant 6,591,407 - Kaufman , et al. July 8, 2	2003-07-08
Method and apparatus for logic synthesis (word oriented netlist) Grant 6,574,787 - Anderson June 3, 2	2003-06-03
Method and apparatus for logic synthesis with elaboration Grant 6,519,755 - Anderson February 11, 2	2003-02-11
Method and apparatus for logic synthesis (inferring complex components) Grant 6,493,648 - Anderson December 10, 2	2002-12-10
Method for determining on-chip sheet resistivity Grant 6,403,389 - Chang , et al. June 11, 2	2002-06-11
Method and system for extraction of parasitic interconnect impedance including inductance Grant 6,381,730 - Chang , et al. April 30, 2	2002-04-30
Methods for determining on-chip interconnect process parameters Grant 6,312,963 - Chou , et al. November 6, 2	2001-11-06

Company Registrations

SEC

0001161260

SEQUENCE DESIGN INC

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