SAXENA; Vivek

Patent Applications and Registrations

Patent applications and USPTO patent grants for SAXENA; Vivek.The latest application filed is for "stiffener and socket embedded metal insert architectures for power delivery".

Company Profile

4.10.11

SAXENA; Vivek - San Ramon CA
Saxena; Vivek - Gurgaon IN
Saxena; Vivek - New York NY
Saxena; Vivek - West Hartford CT
Saxena, Vivek - Philadelphia PA
Saxena; Vivek - Orlando FL

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks

Patent Activity

Patent	Date
Stiffener And Socket Embedded Metal Insert Architectures For Power Delivery App 20220199551 - JAIN; Amit Kumar ; et al.	2022-06-23
System and method for determining automation potential of a process Grant 10,885,486 - Ghosh , et al. January 5, 2	2021-01-05
System and method for assessing client process health Grant 10,796,263 - Ghosh , et al. October 6, 2	2020-10-06
Device, method and system to mitigate a voltage overshoot event Grant 10,541,615 - Jain , et al. Ja	2020-01-21
Device, Method And System To Mitigate A Voltage Overshoot Event App 20200007039 - Jain; Amit ; et al.	2020-01-02
Bracelet Grant D866,386 - Saxena Nov	2019-11-12
System And Method For Determining Automation Potential Of A Process App 20180365617 - GHOSH; Shantanu ; et al.	2018-12-20
System And Method For Assessing Client Process Health App 20160140475 - Ghosh; Shantanu ; et al.	2016-05-19
Engineering standard work framework method and system Grant 7,496,860 - Saxena , et al. February 24, 2	2009-02-24
Engineering standard work framework method and system App 20060005157 - Saxena; Vivek ; et al.	2006-01-05
System and method for capacity allocation in HFC CATV networks App 20050278762 - Leddy, John G. ; et al.	2005-12-15
System and method for providing multiple services in HFC CATV networks App 20050246756 - Leddy, John G. ; et al.	2005-11-03
Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics Grant 6,727,588 - Abdelgadir , et al. April 27, 2	2004-04-27
Semiconductor device having an interconnect layer with a plurality of layout regions having substantially uniform densities of active interconnects and dummy fills Grant 6,683,382 - Cwynar , et al. January 27, 2	2004-01-27
Method for chemical/mechanical planarization of a semiconductor wafer having dissimilar metal pattern densities Grant 6,596,639 - Easter , et al. July 22, 2	2003-07-22
Method for making an interconnect layer and a semiconductor device including the same App 20020162082 - Cwynar, Donald Thomas ; et al.	2002-10-31
Polishing fluid, polishing method, semiconductor device and semiconductor device fabrication method Grant 6,439,972 - Misra , et al. August 27, 2	2002-08-27
Method for making an interconnect layer and a semiconductor device including the same Grant 6,436,807 - Cwynar , et al. August 20, 2	2002-08-20
Methods for deuterium sintering App 20020072187 - Chetlur, Sundar Srinivasan ; et al.	2002-06-13
Polishing fluid, polishing method, semiconductor device and semiconductor device fabrication method App 20010036796 - Misra, Sudhanshu ; et al.	2001-11-01

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