Sager; David J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Sager; David J..The latest application filed is for "systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads".

Company Profile

1.66.25

Sager; David J. - Portland OR
Sager; David J. - Acton MA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads Grant 10,725,755 - Sager , et al.	2020-07-28
Systems, Apparatuses, And Methods For A Hardware And Software System To Automatically Decompose A Program To Multiple Parallel Threads App 20180060049 - SAGER; DAVID J. ; et al.	2018-03-01
Using control flow data structures to direct and track instruction execution Grant 9,880,842 - Bobba , et al. January 30, 2	2018-01-30
Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads Grant 9,672,019 - Sager , et al. June 6, 2	2017-06-06
Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads Grant 9,189,233 - Sasanka , et al. November 17, 2	2015-11-17
Processor having execution core sections operating at different clock rates Grant RE45,487 - Sager , et al. April 21, 2	2015-04-21
Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register Grant 8,914,617 - Raikin , et al. December 16, 2	2014-12-16
Tracking Control Flow Of Instructions App 20140281424 - Bobba; Jayaram ; et al.	2014-09-18
Processor having execution core sections operating at different clock rates Grant RE44,494 - Sager , et al. September 10, 2	2013-09-10
Replay instruction morphing Grant 8,347,066 - Carmean , et al. January 1, 2	2013-01-01
Processor Having Execution Core Sections Operating At Different Clock Rates App 20120042151 - Sager; David J. ; et al.	2012-02-16
Method and Apparatus for Assigning Thread Priority in a Processor or the Like App 20110239221 - Burns; David W. ; et al.	2011-09-29
Move Elimination And Next Page Prefetcher App 20110208918 - Raikin; Shlomo ; et al.	2011-08-25
Method and apparatus for assigning thread priority in a processor or the like Grant 7,987,346 - Burns , et al. July 26, 2	2011-07-26
Systems, Apparatuses, And Methods For A Hardware And Software System To Automatically Decompose A Program To Multiple Parallel Threads App 20110167416 - Sager; David J. ; et al.	2011-07-07
Method And Apparatus For Assigning Thread Priority In A Processor Or The Like App 20110113222 - BURNS; David W. ; et al.	2011-05-12
Method and apparatus for assigning thread priority in a processor or the like Grant 7,877,583 - Burns , et al. January 25, 2	2011-01-25
Mechanisms To Handle Free Physical Register Identifiers For Smt Out-of-order Processors App 20090327661 - Sperber; Zeev ; et al.	2009-12-31
Method And Apparatus For Assigning Thread Priority In A Processor Or The Like App 20090070562 - BURNS; David W. ; et al.	2009-03-12
Method and apparatus for assigning thread priority in a processor or the like Grant 7,454,600 - Burns , et al. November 18, 2	2008-11-18
Fusing load and alu operations Grant 7,398,372 - Samra , et al. July 8, 2	2008-07-08
Multi-threading techniques for a processor utilizing a replay queue Grant 7,219,349 - Merchant , et al. May 15, 2	2007-05-15
Processor with a replay system that includes a replay queue for improved throughput Grant 7,200,737 - Merchant , et al. April 3, 2	2007-04-03
Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies Grant 7,100,012 - Sager August 29, 2	2006-08-29
Interface to a memory system for a processor having a replay system Grant 7,089,409 - Merchant , et al. August 8, 2	2006-08-08
Breaking replay dependency loops in a processor using a rescheduled replay queue Grant 6,981,129 - Boggs , et al. December 27, 2	2005-12-27
Stopping replay tornadoes Grant 6,952,764 - Sager , et al. October 4, 2	2005-10-04
Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor Grant 6,928,647 - Sager August 9, 2	2005-08-09
Replay instruction morphing App 20050172107 - Carmean, Douglas M. ; et al.	2005-08-04
Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection Grant 6,925,550 - Sprangle , et al. August 2, 2	2005-08-02
Replay instruction morphing Grant 6,880,069 - Carmean , et al. April 12, 2	2005-04-12
Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter Grant 6,877,086 - Boggs , et al. April 5, 2	2005-04-05
Storing of instructions relating to a stalled thread Grant 6,792,446 - Merchant , et al. September 14, 2	2004-09-14
Processor having a RAT state history recovery mechanism App 20040177239 - Clift, David W. ; et al.	2004-09-09
Multi-threading techniques for a processor utilizing a replay queue App 20040172523 - Merchant, Amit A. ; et al.	2004-09-02
Processor including replay queue to break livelocks Grant 6,785,803 - Merchant , et al. August 31, 2	2004-08-31
Apparatus and method for address calculation Grant 6,735,682 - Segelken , et al. May 11, 2	2004-05-11
Processor having replay architecture with fast and slow replay paths Grant 6,735,688 - Upton , et al. May 11, 2	2004-05-11
Interface to a memory system for a processor having a replay system App 20040083351 - Merchant, Amit A. ; et al.	2004-04-29
Mechanism for executing computer instructions in parallel Grant 6,704,861 - McKeen , et al. March 9, 2	2004-03-09
Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies App 20040019746 - Sager, David J.	2004-01-29
Fusing load and alu operations App 20030236966 - Samra, Nicholas G. ; et al.	2003-12-25
Interface to a memory system for a processor having a replay system Grant 6,665,792 - Merchant , et al. December 16, 2	2003-12-16
Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer Grant 6,633,970 - Clift , et al. October 14, 2	2003-10-14
Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies Grant 6,631,454 - Sager October 7, 2	2003-10-07
Apparatus and method for address calculation App 20030188125 - Segelken, Ross A. ; et al.	2003-10-02
Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor App 20030158885 - Sager, David J.	2003-08-21
Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor App 20030154235 - Sager, David J.	2003-08-14
Method and apparatus to execute instructions in a processor App 20030126417 - Sprangle, Eric ; et al.	2003-07-03
Stopping replay tornadoes App 20030126405 - Sager, David J. ; et al.	2003-07-03
Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor Grant 6,542,921 - Sager April 1, 2	2003-04-01
Method and apparatus for assigning thread priority in a processor or the like App 20020199088 - Burns, David W. ; et al.	2002-12-26
Way-predicting cache memory Grant 6,425,055 - Sager , et al. July 23, 2	2002-07-23
Multi-threading techniques for a processor utilizing a replay queue App 20020091914 - Merchant, Amit A. ; et al.	2002-07-11
System and method for partial merges for sub-register data operations App 20020083307 - Sager, David J. ; et al.	2002-06-27
Multi-threading for a processor utilizing a replay queue Grant 6,385,715 - Merchant , et al. May 7, 2	2002-05-07
Scheduling operations using a dependency matrix Grant 6,334,182 - Merchant , et al. December 25, 2	2001-12-25
Processor having execution core sections operating at different clock rates App 20010029590 - Sager, David J. ; et al.	2001-10-11
Pipelined processor for performing parallel instruction recording and register assigning Grant 6,282,629 - Sager August 28, 2	2001-08-28
Processor having execution core sections operating at different clock rates Grant 6,216,234 - Sager , et al. April 10, 2	2001-04-10
Computer processor having a checker Grant 6,212,626 - Merchant , et al. April 3, 2	2001-04-03
Trace based instruction caching Grant 6,170,038 - Krick , et al. January 2, 2	2001-01-02
Computer processor with a replay system Grant 6,163,838 - Merchant , et al. December 19, 2	2000-12-19
Computer processor with a replay system having a plurality of checkers Grant 6,094,717 - Merchant , et al. July 25, 2	2000-07-25
Trace based instruction caching Grant 6,018,786 - Krick , et al. January 25, 2	2000-01-25
Data speculatable processor having reply architecture Grant 5,966,544 - Sager October 12, 1	1999-10-12
Past-history filtered branch prediction Grant 5,828,874 - Steely, Jr. , et al. October 27, 1	1998-10-27
Processor having execution core sections operating at different clock rates Grant 5,828,868 - Sager , et al. October 27, 1	1998-10-27
Method and apparatus for parallel execution of computer programs using information providing for reconstruction of a logical sequential program Grant 5,717,883 - Sager February 10, 1	1998-02-10
Low delay means of communicating between systems on different clocks Grant 5,680,644 - Sager October 21, 1	1997-10-21
Multiple block line prediction Grant 5,581,719 - Steely, Jr. , et al. December 3, 1	1996-12-03
Past-history filtered branch prediction Grant 5,564,118 - Steely, Jr. , et al. October 8, 1	1996-10-08
Multi instruction register mapper Grant 5,519,841 - Sager , et al. May 21, 1	1996-05-21
Method and apparatus for propagating exception conditions of a computer system Grant 5,428,807 - McKeen , et al. June 27, 1	1995-06-27
Apparatus and method for speculatively executing instructions in a computer system Grant 5,421,022 - McKeen , et al. May 30, 1	1995-05-30
Mechanism for enforcing the correct order of instruction execution Grant 5,420,990 - McKeen , et al. May 30, 1	1995-05-30
Method and apparatus for realignment of synchronous data Grant 5,359,630 - Wade , et al. October 25, 1	1994-10-25
Next line prediction apparatus for a pipelined computed system Grant 5,283,873 - Steely, Jr. , et al. February 1, 1	1994-02-01
Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery Grant 5,197,132 - Steely, Jr. , et al. March 23, 1	1993-03-23
Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline Grant 5,179,673 - Steely, Jr. , et al. January 12, 1	1993-01-12
Cache memory system Grant 5,003,459 - Ramanujan , et al. March 26, 1	1991-03-26
Method of transmitting data at full bandwidth within a synchronous system when clock skew plus delay exceeds the cycle time Grant 5,003,537 - Sager March 26, 1	1991-03-26
Method and apparatus for stabilized data transmission Grant 4,979,190 - Sager , et al. * December 18, 1	1990-12-18
Method and apparatus for high speed data transmission between two systems operating under the same clock with unknown and non constant skew in the clock between the two systems Grant 4,881,165 - Sager , et al. November 14, 1	1989-11-14
Lockout registers Grant 4,825,412 - Sager , et al. April 25, 1	1989-04-25
Method and apparatus for stabilized data transmission Grant 4,811,364 - Sager , et al. March 7, 1	1989-03-07

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