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Ternary In-memory Accelerator
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Continuous authentication system and method based on BioAura
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Apparatuses, Methods, And Systems For Neural Networks
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Tomographic Reconstruction System
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Apparatuses, Methods, And Systems For Access Synchronization In A Shared Memory
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Approximate Cache Memory
App 20190220412 - Ranjan; Ashish ; et al. | 2019-07-18 |
Approximate cache memory
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Tomographic reconstruction system
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Approximate Cache Memory
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Securing medical devices through wireless monitoring and anomaly detection
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System and method for in-memory computing
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Vibration-based Secure Side Channel For Medical Devices
App 20180043168 - Kim; Younghyun ; et al. | 2018-02-15 |
Continuous Authentication System And Method Based On Bioaura
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Safety-driven Architecture For Implantable And Wearable Medical Devices
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Tomographic Reconstruction System
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Automatic pipelining framework for heterogeneous parallel computing systems
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Cross-layer system architecture design
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Automatic Pipelining Framework For Heterogeneous Parallel Computing Systems
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Securing Medical Devices Through Wireless Monitoring And Anomaly Detection
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Systems and methods for implementing best-effort parallel computing frameworks
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Methods and systems for managing computations on a hybrid computing platform including a parallel accelerator
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Cross-layer System Architecture Design
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Partitioned Iterative Convergance Programming Model
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Methods And Systems For Managing Computations On A Hybrid Computing Platform Including A Parallel Accelerator
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Systems And Methods For Implementing Best-effort Parallel Computing Frameworks
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Voice-based multimodal speaker authentication using adaptive training and applications thereof
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Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
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Voice-based Multimodal Speaker Authentication Using Adaptive Training And Applications Thereof
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System-level test architecture for delivery of compressed tests
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Power estimation employing cycle-accurate functional descriptions
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Apparatus and Method for Improving Security of a Bus Based System Through Communication Architecture Enhancements
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Flexible crossbar switching fabric
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Power Estimation Employing Cycle-accurate Functional Descriptions
App 20070022395 - Ravi; Srivaths ; et al. | 2007-01-25 |
Method and apparatus for efficient register-transfer level (RTL) power estimation
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System-level power estimation using heteregeneous power models
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Power estimation through power emulation
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Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners
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Tamper resistant secure architecture
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System-level test architecture for delivery of compressed tests
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High performance communication architecture for circuit designs using probabilistic allocation of resources
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Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
App 20040148150 - Ashar, Pranav ; et al. | 2004-07-29 |
Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
Grant 6,745,160 - Ashar , et al. June 1, 2 | 2004-06-01 |
Power mode based macro-models for power estimation of electronic circuits
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System for the design of high-performance communication architecture for system-on-chips using communication architecture tuners
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Method and apparatus for efficient register-transfer level (RTL) power estimation
App 20040019859 - Ravi, Srivaths ; et al. | 2004-01-29 |
Multi-level power macromodeling
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Techniques for efficient security processing
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Flexible crossbar switching fabric
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Multi-level power macromodeling
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Power mode based macro-models for power estimation of electronic circuits
App 20020133792 - Raghunathan, Anand ; et al. | 2002-09-19 |
High-performance communication architecture for circuit designs
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Register transfer level power optimization with emphasis on glitch analysis and reduction
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Method for synthesis of common-case optimized circuits to improve performance and power dissipation
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Constrained register sharing technique for low power VLSI design
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Method for verification of RTL generated from scheduled behavior in a high-level synthesis flow
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Controller-based power management for low-power sequential circuits
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Design tools for high-level synthesis of a low-power data path
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Process for dynamic composition and test cycles reduction
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