Paul; Bipul C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Paul; Bipul C..The latest application filed is for "non-volatile transistor embedded static random access memory (sram) cell".

Company Profile

42.55.45

Paul; Bipul C. - Mechanicville NY
Paul; Bipul C. - Malta NY
Paul; Bipul C. - Clifton Park NY
Paul; Bipul C. - Fishkill NY
- Clifton Park NY US
Paul; Bipul C. - Santa Clara CA US
Paul; Bipul C. - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
True random number generation and physically unclonable functions using voltage control of magnetic anisotropy effects in STT-MRAM Grant 11,435,982 - Dixit , et al. September 6, 2	2022-09-06
Non-volatile Transistor Embedded Static Random Access Memory (sram) Cell App 20220180923 - JAISWAL; Akhilesh R. ; et al.	2022-06-09
Structures and SRAM bit cells integrating complementary field-effect transistors Grant 11,309,319 - Mann , et al. April 19, 2	2022-04-19
Non-volatile Static Random Access Memory App 20220068340 - Paul; Bipul C. ; et al.	2022-03-03
Row-wise Tracking Of Reference Generation For Memory Devices App 20220051709 - JAISWAL; Akhilesh R. ; et al.	2022-02-17
Memory cells with vertically overlapping wordlines Grant 11,227,894 - Gupta , et al. January 18, 2	2022-01-18
Sensing Scheme For Stt-mram Using Low-barrier Nanomagnets App 20210327487 - AGRAWAL; Amogh ; et al.	2021-10-21
Low variability reference parameter generation for magnetic random access memory Grant 11,120,857 - Jaiswal , et al. September 14, 2	2021-09-14
Sensing scheme for STT-MRAM using low-barrier nanomagnets Grant 11,087,814 - Agrawal , et al. August 10, 2	2021-08-10
True Random Number Generation And Physically Unclonable Functions Using Voltage Control Of Magnetic Anisotropy Effects In Stt-mram App 20210240445 - Dixit; Hemant M. ; et al.	2021-08-05
Circuit structure and method for resistive RAM with self aligned contacts in zero-via layer Grant 11,075,247 - Gupta , et al. July 27, 2	2021-07-27
Low Variability Reference Parameter Generation For Magnetic Random Access Memory App 20210193204 - Jaiswal; Akhilesh ; et al.	2021-06-24
Circuit Structure And Method For Resistive Ram With Self Aligned Contacts In Zero-via Layer App 20210159273 - Gupta; Anuj ; et al.	2021-05-27
Circuit Structure And Memory Circuit With Resistive Memory Elements, And Related Methods App 20210142850 - Soss; Steven R. ; et al.	2021-05-13
Circuit structure and memory circuit with resistive memory elements, and related methods Grant 11,004,509 - Soss , et al. May 11, 2	2021-05-11
Twisted wordline structures Grant 11,004,491 - Gupta , et al. May 11, 2	2021-05-11
Memory Cells With Vertically Overlapping Wordlines App 20210134881 - Gupta; Anuj ; et al.	2021-05-06
Twisted Wordline Structures App 20210090627 - GUPTA; Anuj ; et al.	2021-03-25
Asymmetric gate cut isolation for SRAM Grant 10,950,610 - Paul , et al. March 16, 2	2021-03-16
Asymmetric Gate Cut Isolation For Sram App 20210020644 - Paul; Bipul C. ; et al.	2021-01-21
Sensing Scheme For Stt-mram Using Low-barrier Nanomagnets App 20210012822 - AGRAWAL; Amogh ; et al.	2021-01-14
Structures And Sram Bit Cells Integrating Complementary Field-effect Transistors App 20200365601 - Mann; Randy W. ; et al.	2020-11-19
Structures and SRAM bit cells with a buried cross-couple interconnect Grant 10,840,146 - Paul , et al. November 17, 2	2020-11-17
Structures and SRAM bit cells integrating complementary field-effect transistors Grant 10,818,674 - Mann , et al. October 27, 2	2020-10-27
Non-volatile memory elements with multiple access transistors Grant 10,811,069 - Patel , et al. October 20, 2	2020-10-20
Bitcells for a non-volatile memory device Grant 10,777,607 - Paul , et al. Sept	2020-09-15
Structures And Sram Bit Cells Integrating Complementary Field-effect Transistors App 20200286900 - Mann; Randy W. ; et al.	2020-09-10
Integrated circuit structure with complementary field effect transistor and buried metal interconnect and method Grant 10,756,096 - Paul , et al. A	2020-08-25
Method of forming a buried interconnect and the resulting devices Grant 10,720,391 - Paul , et al.	2020-07-21
Non-volatile Memory Elements With Multiple Access Transistors App 20200227107 - Patel; Harsh N. ; et al.	2020-07-16
Method Of Forming A Buried Interconnect And The Resulting Devices App 20200219813 - Paul; Bipul C. ; et al.	2020-07-09
Two port SRAM cell using complementary nano-sheet/wire transistor devices Grant 10,707,218 - Paul , et al.	2020-07-07
Gate Contact Structures And Cross-coupled Contact Structures For Transistor Devices App 20200203497 - Xie; Ruilong ; et al.	2020-06-25
Wordline strapping for non-volatile memory elements Grant 10,685,951 - Gupta , et al.	2020-06-16
Wordline Strapping For Non-volatile Memory Elements App 20200185374 - Gupta; Anuj ; et al.	2020-06-11
Resistive nonvolatile memory cells with shared access transistors Grant 10,665,281 - Jacob , et al.	2020-05-26
Methods of forming gate contact structures and cross-coupled contact structures for transistor devices Grant 10,651,284 - Xie , et al.	2020-05-12
Static random access memory cells with arranged vertical-transport field-effect transistors Grant 10,629,602 - Mann , et al.	2020-04-21
Integrated Circuit Structure With Complementary Field Effect Transistor And Buried Metal Interconnect And Method App 20200111798 - Paul; Bipul C. ; et al.	2020-04-09
Dynamic bipolar write-assist for non-volatile memory elements Grant 10,586,581 - Patel , et al.	2020-03-10
Two Port Sram Cell Using Complementary Nano-sheet/wire Transistor Devices App 20200035686 - Paul; Bipul C. ; et al.	2020-01-30
Magneto-resistive memory structures with improved sensing, and associated sensing methods Grant 10,515,679 - Jaiswal , et al. Dec	2019-12-24
Integrated circuits having memory cells with shared bit lines and shared source lines Grant 10,510,392 - Paul , et al. Dec	2019-12-17
Methods of forming conductive spacers for gate contacts and the resulting device Grant 10,504,790 - Xie , et al. Dec	2019-12-10
Gate contact structures and cross-coupled contact structures for transistor devices Grant 10,490,455 - Xie , et al. Nov	2019-11-26
Static Random Access Memory Cells With Arranged Vertical-transport Field-effect Transistors App 20190355730 - Mann; Randy W. ; et al.	2019-11-21
Dual port vertical transistor memory cell Grant 10,439,064 - Mann , et al. O	2019-10-08
Circuits based on complementary field-effect transistors Grant 10,418,449 - Paul , et al. Sept	2019-09-17
Buried local interconnect in source/drain region Grant 10,418,368 - Bentley , et al. Sept	2019-09-17
Bitcell Layout For A Two-port Sram Cell Employing Vertical-transport Field-effect Transistors App 20190279990 - Paul; Bipul C. ; et al.	2019-09-12
Six-transistor (6T) SRAM cell structure Grant 10,403,629 - Mann , et al. Sep	2019-09-03
Magneto-resistive Memory Structures With Improved Sensing, And Associated Sensing Methods App 20190244650 - Jaiswal; Akhilesh ; et al.	2019-08-08
Circuits Based On Complementary Field-effect Transistors App 20190214469 - Paul; Bipul C. ; et al.	2019-07-11
Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming Grant 10,332,803 - Xie , et al.	2019-06-25
Method of forming complementary nano-sheet/wire transistor devices with same depth contacts Grant 10,304,833 - Suvarna , et al.	2019-05-28
Gate Contact Structures And Cross-coupled Contact Structures For Transistor Devices App 20190148240 - Xie; Ruilong ; et al.	2019-05-16
Novel Six-transistor (6t) Sram Cell Structure App 20190139967 - Mann; Randy W. ; et al.	2019-05-09
Methods Of Forming Gate Contact Structures And Cross-coupled Contact Structures For Transistor Devices App 20190123162 - Xie; Ruilong ; et al.	2019-04-25
Cross-coupled contact structure on IC products and methods of making such contact structures Grant 10,236,296 - Chanemougame , et al.	2019-03-19
Methods of forming gate contact structures and cross-coupled contact structures for transistor devices Grant 10,236,215 - Xie , et al.	2019-03-19
Methods Of Forming Conductive Spacers For Gate Contacts And The Resulting Device App 20190035692 - Xie; Ruilong ; et al.	2019-01-31
Integrated circuit structure incorporating multiple gate-all-around field effect transistors having different drive currents and method Grant 10,170,484 - Sung , et al. J	2019-01-01
In-kerf Test Structure And Testing Method For A Memory Array App 20180323117 - PAUL; BIPUL C. ; et al.	2018-11-08
In-kerf test structure and testing method for a memory array Grant 10,121,713 - Paul , et al. November 6, 2	2018-11-06
Cross couple structure for vertical transistors Grant 10,109,637 - Zang , et al. October 23, 2	2018-10-23
Active contact and gate contact interconnect for mitigating adjacent gate electrode shortages Grant 10,109,636 - Woo , et al. October 23, 2	2018-10-23
Active Contact And Gate Contact Interconnect For Mitigating Adjacent Gate Electrode Shortages App 20180261604 - Woo; Youngtag ; et al.	2018-09-13
Metal layer routing level for vertical FET SRAM and logic cell scaling Grant 10,056,377 - Bentley , et al. August 21, 2	2018-08-21
Metal Layer Routing Level For Vertical Fet Sram And Logic Cell Scaling App 20180145073 - BENTLEY; Steven ; et al.	2018-05-24
Active area shapes reducing device size Grant 9,929,236 - Paul , et al. March 27, 2	2018-03-27
Metal layer routing level for vertical FET SRAM and logic cell scaling Grant 9,825,032 - Bentley , et al. November 21, 2	2017-11-21
Active area shapes reducing device size Grant 9,761,662 - Paul , et al. September 12, 2	2017-09-12
Dual port SRAM bitcell structures with improved transistor arrangement Grant 9,202,552 - Paul , et al. December 1, 2	2015-12-01
Modeling memory cell skew sensitivity Grant 9,069,922 - Paul , et al. June 30, 2	2015-06-30
Dual Port Sram Bitcell Structures With Improved Transistor Arrangement App 20150170735 - PAUL; Bipul C. ; et al.	2015-06-18
Edge and strap cell design for SRAM array Grant 8,921,179 - Paul , et al. December 30, 2	2014-12-30
Edge and strap cell design for SRAM array Grant 08921179 -	2014-12-30
Sram Cell With Reduced Voltage Droop App 20140299941 - Paul; Bipul C.	2014-10-09
Edge And Strap Cell Design For Sram Array App 20140225201 - PAUL; Bipul C. ; et al.	2014-08-14
Hierarchical layout versus schematic (LVS) comparison with extraneous device elimination Grant 8,751,985 - Puri , et al. June 10, 2	2014-06-10
Modeling Memory Cell Skew Sensitivity App 20130332136 - Paul; Bipul C. ; et al.	2013-12-12
Router design for 3D network-on-chip Grant 8,391,281 - Paul March 5, 2	2013-03-05
Memory based computation systems and methods of using the same Grant 8,238,136 - Paul August 7, 2	2012-08-07
ROM implementation for ROM based logic design Grant 8,222,922 - Paul July 17, 2	2012-07-17
Multi-valued ROM using carbon-nanotube and nanowire FET Grant 8,064,253 - Paul November 22, 2	2011-11-22
Router Design For 3d Network-on-chip App 20110243147 - Paul; Bipul C.	2011-10-06
Memory cell architecture Grant 7,995,368 - Paul August 9, 2	2011-08-09
Multi-valued Rom Using Carbon-nanotube And Nanowire Fet App 20110063905 - Paul; Bipul C.	2011-03-17
Rom Implementation For Rom Based Logic Design App 20100244892 - Paul; Bipul C.	2010-09-30
Memory Based Computation Systems And Methods Of Using The Same App 20100097837 - PAUL; Bipul C.	2010-04-22
Memory based computation systems and methods of using the same Grant 7,646,622 - Paul January 12, 2	2010-01-12
Memory Cell Architecture App 20090207644 - Paul; Bipul C.	2009-08-20
Memory based computation systems and methods for high performance and/or fast operations Grant 7,570,505 - Paul August 4, 2	2009-08-04
Carbon Nanotube Transistor Having Low Fringe Capacitance And Low Channel Resistance App 20080173864 - Fujita; Shinobu ; et al.	2008-07-24
Memory Based Computation Systems and Methods of Using the Same App 20070268042 - Paul; Bipul C.	2007-11-22
Memory Based Computation Systems And Methods For High Performance And/or Fast Operations App 20070244947 - PAUL; Bipul C.	2007-10-18

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