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name:-0.025539875030518
name:-0.017534971237183
name:-0.0018808841705322
Paruchuri; Vamsi Patent Filings

Paruchuri; Vamsi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Paruchuri; Vamsi.The latest application filed is for "selective passivation and selective deposition".

Company Profile
1.19.25
  • Paruchuri; Vamsi - Mesa AZ
  • Paruchuri; Vamsi - Clifton Park NY
  • Paruchuri; Vamsi - New York NY
  • Paruchuri; Vamsi - Albany NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Selective Passivation And Selective Deposition
App 20220208542 - Maes; Jan Willem Hub ;   et al.
2022-06-30
System And Methods For Direct Liquid Injection Of Vanadium Precursors
App 20210371978 - Shero; Eric James ;   et al.
2021-12-02
Selective Passivation And Selective Deposition
App 20210358745 - Maes; Jan Willem ;   et al.
2021-11-18
Selective passivation and selective deposition
Grant 11,145,506 - Maes , et al. October 12, 2
2021-10-12
Selective Passivation And Selective Deposition
App 20200105515 - Maes; Jan Willem Hub ;   et al.
2020-04-02
Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings
Grant 9,305,883 - Naczas , et al. April 5, 2
2016-04-05
Locally Raised Epitaxy For Improved Contact By Local Silicon Capping During Trench Silicide Processings
App 20150179576 - Naczas; Sebastian ;   et al.
2015-06-25
Cyclical physical vapor deposition of dielectric layers
Grant 9,053,926 - Jamison , et al. June 9, 2
2015-06-09
Corrosion/etching protection in integration circuit fabrications
Grant 9,054,109 - Lin , et al. June 9, 2
2015-06-09
Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings
Grant 8,999,779 - Naczas , et al. April 7, 2
2015-04-07
Locally Raised Epitaxy For Improved Contact By Local Silicon Capping During Trench Silicide Processings
App 20150069531 - Naczas; Sebastian ;   et al.
2015-03-12
Cyclical Physical Vapor Deposition Of Dielectric Layers
App 20140273425 - Jamison; Paul ;   et al.
2014-09-18
Corrosion/etching Protection In Integration Circuit Fabrications
App 20130320544 - Lin; Wei ;   et al.
2013-12-05
Threshold adjustment for high-K gate dielectric CMOS
Grant 8,187,961 - Doris , et al. May 29, 2
2012-05-29
Gate effective-workfunction modification for CMOS
Grant 8,183,642 - Park , et al. May 22, 2
2012-05-22
Self-aligned CMOS structure with dual workfunction
Grant 8,030,716 - Park , et al. October 4, 2
2011-10-04
Gate Effective-Workfunction Modification for CMOS
App 20110121401 - Park; Dae-Gyu ;   et al.
2011-05-26
Gate effective-workfunction modification for CMOS
Grant 7,947,549 - Park , et al. May 24, 2
2011-05-24
Dielectric spacer removal
Grant 7,919,379 - Cartier , et al. April 5, 2
2011-04-05
Simple low power circuit structure with metal gate and high-k dielectric
Grant 7,880,243 - Doris , et al. February 1, 2
2011-02-01
Fabrication of self-aligned CMOS structure
App 20110001195 - Park; Dae-Gyu ;   et al.
2011-01-06
Fabrication of a CMOS structure with a high-k dielectric layer oxidizing an aluminum layer in PFET region
Grant 7,863,126 - Park , et al. January 4, 2
2011-01-04
Metal gate high-K devices having a layer comprised of amorphous silicon
Grant 7,847,356 - Chen , et al. December 7, 2
2010-12-07
Low power circuit structure with metal gate and high-k dielectric
Grant 7,807,525 - Doris , et al. October 5, 2
2010-10-05
Method to fabricate metal gate high-k devices
Grant 7,790,592 - Chen , et al. September 7, 2
2010-09-07
Formation of fully silicided metal gate using dual self-aligned silicide process
Grant 7,785,999 - Cabral, Jr. , et al. August 31, 2
2010-08-31
Low power circuit structure with metal gate and high-k dielectric
Grant 7,723,798 - Doris , et al. May 25, 2
2010-05-25
Structure and Method to Fabricate Metal Gate High-K Devices
App 20090302396 - Chen; Tze-Chiang ;   et al.
2009-12-10
Threshold Adjustment for High-K Gate Dielectric CMOS
App 20090291553 - Doris; Bruce B. ;   et al.
2009-11-26
Fabrication of self-aligned CMOS structure
App 20090283838 - Park; Dae-Gyu ;   et al.
2009-11-19
Gate Effective-Workfunction Modification for CMOS
App 20090212369 - Park; Dae-Gyu ;   et al.
2009-08-27
Structure And Method To Fabricate Metal Gate High-K Devices
App 20090108366 - Chen; Tze-Chiang ;   et al.
2009-04-30
Dielectric Spacer Removal
App 20090065817 - Cartier; Eduard A. ;   et al.
2009-03-12
High Performance Metal Gate CMOS with High-K Gate Dielectric
App 20090039436 - Doris; Bruce B. ;   et al.
2009-02-12
Simple Low Power Circuit Structure with Metal Gate and High-k Dielectric
App 20090039434 - Doris; Bruce B. ;   et al.
2009-02-12
Low Power Circuit Structure with Metal Gate and High-k Dielectric
App 20090039435 - Doris; Bruce B. ;   et al.
2009-02-12
Devices with Metal Gate, High-k Dielectric, and Butted Electrodes
App 20080277726 - Doris; Bruce B. ;   et al.
2008-11-13
Threshold Adjustment for High-K Gate Dielectric CMOS
App 20080272437 - Doris; Bruce B. ;   et al.
2008-11-06
Strained Metal Gate Structure For Cmos Devices With Improved Channel Mobility And Methods Of Forming The Same
App 20080203485 - Chudzik; Michael P. ;   et al.
2008-08-28
Formation Of Fully Silicided Metal Gate Using Dual Self-aligned Silicide Process
App 20080026551 - Cabral; Cyril JR. ;   et al.
2008-01-31
Formation of fully silicided metal gate using dual self-aligned silicide process
Grant 7,271,455 - Cabral, Jr. , et al. September 18, 2
2007-09-18
Formation of fully silicided metal gate using dual self-aligned silicide process
App 20060022280 - Cabral; Cyril JR. ;   et al.
2006-02-02

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