PARIKH; Ashesh

Patent Applications and Registrations

Patent applications and USPTO patent grants for PARIKH; Ashesh.The latest application filed is for "selecting optimum primary and secondary parameters to calibrate and generate an unbiased forecasting model".

Company Profile

2.15.20

PARIKH; Ashesh - Frisco TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Selecting Optimum Primary And Secondary Parameters To Calibrate And Generate An Unbiased Forecasting Model App 20210216907 - HUSAIN; Afzal ; et al.	2021-07-15
Network Optimization App 20210065031 - PARIKH; Ashesh ; et al.	2021-03-04
Method to improve transistor matching Grant 10,339,251 - Parikh , et al.	2019-07-02
CMOS-based thermopile with reduced thermal conductance Grant 9,853,086 - Edwards , et al. December 26, 2	2017-12-26
Method To Improve Transistor Matching App 20170228488 - PARIKH; Ashesh ; et al.	2017-08-10
Method to improve transistor matching Grant 9,665,675 - Parikh , et al. May 30, 2	2017-05-30
Cmos-based Thermopile With Reduced Thermal Conductance App 20170062518 - Edwards; Henry Litzmann ; et al.	2017-03-02
CMOS-based thermopile with reduced thermal conductance Grant 9,496,313 - Edwards , et al. November 15, 2	2016-11-15
Cmos-based Thermopile With Reduced Thermal Conductance App 20150349022 - Edwards; Henry Litzmann ; et al.	2015-12-03
Method To Improve Transistor Matching App 20150187655 - PARIKH; Ashesh ; et al.	2015-07-02
Extraction of imaging parameters for computational lithography using a data weighting algorithm Grant 8,806,388 - Parikh August 12, 2	2014-08-12
Computational lithography with feature upsizing Grant 8,793,626 - Parikh , et al. July 29, 2	2014-07-29
Extraction Of Imaging Parameters For Computational Lithography Using A Data Weighting Algorithm App 20130254725 - PARIKH; ASHESH	2013-09-26
Extraction Of Imaging Parameters For Computational Lithography Using A Data Weighting Algorithm App 20130254724 - PARIKH; ASHESH	2013-09-26
Computational Lithography With Feature Upsizing App 20130254723 - PARIKH; ASHESH ; et al.	2013-09-26
Transistor layout for manufacturing process control Grant 8,394,681 - Parikh , et al. March 12, 2	2013-03-12
Method Of Transistor Matching App 20120117519 - Parikh; Ashesh	2012-05-10
Current Mirror Using Ambipolar Devices App 20120105046 - Marshall; Andrew ; et al.	2012-05-03
OPC models generated from 2D high frequency test patterns Grant 8,015,513 - Parikh , et al. September 6, 2	2011-09-06
Transistor layout for manufacturing process control Grant 7,985,990 - Parikh , et al. July 26, 2	2011-07-26
Carbon nanotube transistors on a silicon or SOI substrate Grant 7,842,955 - Parikh , et al. November 30, 2	2010-11-30
Transistor Layout for Manufacturing Process Control App 20100297815 - Parikh; Ashesh ; et al.	2010-11-25
Method for fabricating graphene transistors on a silicon or SOI substrate Grant 7,772,059 - Parikh , et al. August 10, 2	2010-08-10
Method For Fabricating Carbon Nanotube Transistors On A Silicon Or Soi Substrate App 20100133512 - Parikh; Ashesh ; et al.	2010-06-03
Method for fabricating carbon nanotube transistors on a silicon or SOI substrate Grant 7,687,308 - Parikh , et al. March 30, 2	2010-03-30
Method For Fabricating Carbon Nanotube Transistors On A Silicon Or Soi Substrate App 20100038627 - Parikh; Ashesh ; et al.	2010-02-18
Transistor layout for manufacturing process control App 20100038684 - Parikh; Ashesh ; et al.	2010-02-18
Opc Models Generated From 2d High Frequency Test Patterns App 20090300557 - Parikh; Ashesh ; et al.	2009-12-03
Method For Fabricating Graphene Transistors On A Silicon Or Soi Substrate App 20090181502 - Parikh; Ashesh ; et al.	2009-07-16
Method and process for generating an optical proximity correction model based on layout density Grant 7,562,333 - Parikh , et al. July 14, 2	2009-07-14
Verifying a process margin of a mask pattern using intermediate stage models Grant 7,458,058 - Parikh , et al. November 25, 2	2008-11-25
Verifying a process margin of a mask pattern using intermediate stage models App 20060281015 - Parikh; Ashesh ; et al.	2006-12-14
Method and system for optimization of transistor sizing based on layout density App 20060141366 - Parikh; Ashesh ; et al.	2006-06-29
Novel low defect developer rinse process for 0.15 micron cmos technology App 20020086242 - Boehm, Mark A. ; et al.	2002-07-04

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