Patent | Date |
---|
Semiconductor device with trench-like feed-throughs Grant 10,032,901 - Pattanayak , et al. July 24, 2 | 2018-07-24 |
Semiconductor Device With Trench-like Feed-throughs App 20170025527 - Pattanayak; Deva ;   et al. | 2017-01-26 |
Semiconductor device with trench-like feed-throughs Grant 9,306,056 - Pattanayak , et al. April 5, 2 | 2016-04-05 |
Complete Power Management System Implemented In A Single Surface Mount Package App 20150331438 - Owyang; King ;   et al. | 2015-11-19 |
Complete power management system implemented in a single surface mount package Grant 9,093,359 - Owyang , et al. July 28, 2 | 2015-07-28 |
Semiconductor including cup-shaped leadframe packaging techniques Grant 9,040,356 - Chang , et al. May 26, 2 | 2015-05-26 |
Complete power management system implemented in a single surface mount package Grant 8,928,138 - Owyang , et al. January 6, 2 | 2015-01-06 |
Complete power management system implemented in a single surface mount package Grant 8,471,381 - Owyang , et al. June 25, 2 | 2013-06-25 |
High current density power field effect transistor Grant 8,269,263 - Li , et al. September 18, 2 | 2012-09-18 |
Semiconductor Device With Trench-like Feed-throughs App 20110101525 - Pattanayak; Deva ;   et al. | 2011-05-05 |
Complete Power Management System Implemented In A Single Surface Mount Package App 20100219519 - Owyang; King ;   et al. | 2010-09-02 |
High Current Density Power Field Effect Transistor App 20090278176 - Li; Jian ;   et al. | 2009-11-12 |
Semiconductor Packaging Techniques App 20090256246 - Chang; Mike ;   et al. | 2009-10-15 |
Semiconductor die package including cup-shaped leadframe Grant 7,595,547 - Chang , et al. September 29, 2 | 2009-09-29 |
Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys Grant 7,394,150 - Kasem , et al. July 1, 2 | 2008-07-01 |
Trench MIS device having implanted drain-drift region and thick bottom oxide Grant 7,326,995 - Darwish , et al. February 5, 2 | 2008-02-05 |
Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys Grant 7,238,551 - Kasem , et al. July 3, 2 | 2007-07-03 |
Complete power management system implemented in a single surface mount package App 20070063341 - Owyang; King ;   et al. | 2007-03-22 |
Complete power management system implemented in a single surface mount package App 20070063340 - Owyang; King ;   et al. | 2007-03-22 |
Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys App 20060108671 - Kasem; Mohammed ;   et al. | 2006-05-25 |
Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys App 20060110856 - Kasem; Mohammed ;   et al. | 2006-05-25 |
Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same Grant 7,033,876 - Darwish , et al. April 25, 2 | 2006-04-25 |
Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same App 20050236665 - Darwish, Mohamed N. ;   et al. | 2005-10-27 |
Semiconductor assembly with package using cup-shaped lead-frame Grant 6,909,170 - Chang , et al. June 21, 2 | 2005-06-21 |
Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same App 20040121572 - Darwish, Mohamed N. ;   et al. | 2004-06-24 |
Semiconductor die package including cup-shaped leadframe Grant 6,744,124 - Chang , et al. June 1, 2 | 2004-06-01 |
Semiconductor assembly with package using cup-shaped lead frame App 20030057532 - Chang, Mike ;   et al. | 2003-03-27 |
Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof Grant 5,910,669 - Chang , et al. June 8, 1 | 1999-06-08 |
Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation Grant 5,767,578 - Chang , et al. June 16, 1 | 1998-06-16 |
Surface mount and flip chip technology for total integrated circuit isolation Grant 5,757,081 - Chang , et al. May 26, 1 | 1998-05-26 |
Surface mount and flip chip technology for total integrated circuit isolation Grant 5,753,529 - Chang , et al. May 19, 1 | 1998-05-19 |
Trenched DMOS transistor fabrication having thick termination region oxide Grant 5,639,676 - Hshieh , et al. June 17, 1 | 1997-06-17 |
Trenched DMOS transistor having thick field oxide in termination region Grant 5,578,851 - Hshieh , et al. November 26, 1 | 1996-11-26 |
Method of making a field effect trench transistor having lightly doped epitaxial region on the surface portion thereof Grant 5,532,179 - Chang , et al. July 2, 1 | 1996-07-02 |
Structure of power mosfets, including termination structures Grant 5,521,409 - Hshieh , et al. May 28, 1 | 1996-05-28 |
Reverse battery protection device containing power MOSFET Grant 5,517,379 - Williams , et al. May 14, 1 | 1996-05-14 |
Trenched DMOS transistor with channel block at cell trench corners Grant 5,468,982 - Hshieh , et al. November 21, 1 | 1995-11-21 |
Low on-resistance power MOS technology Grant 5,429,964 - Yilmaz , et al. July 4, 1 | 1995-07-04 |
Metal crossover in high voltage IC with graduated doping control Grant 5,426,325 - Chang , et al. June 20, 1 | 1995-06-20 |
Structure and fabrication of power MOSFETs, including termination structures Grant 5,404,040 - Hshieh , et al. April 4, 1 | 1995-04-04 |
Trenched DMOS transistor fabrication using six masks Grant 5,316,959 - Kwan , et al. May 31, 1 | 1994-05-31 |
Low on-resistance power MOS technology Grant 5,304,831 - Yilmaz , et al. April 19, 1 | 1994-04-19 |
Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs Grant 5,132,753 - Chang , et al. July 21, 1 | 1992-07-21 |
IGT and MOSFET devices having reduced channel width Grant 4,803,533 - Chang , et al. February 7, 1 | 1989-02-07 |
Mosfet structure with substrate coupled source Grant 4,794,432 - Yilmaz , et al. December 27, 1 | 1988-12-27 |
Semiconductor device with built-up low resistance contact Grant 4,505,029 - Owyang , et al. March 19, 1 | 1985-03-19 |
Method of making an integrated circuit incorporating low voltage and high voltage semiconductor devices Grant 4,475,280 - Ragonese , et al. October 9, 1 | 1984-10-09 |
Integrated circuit incorporating low voltage and high voltage semiconductor devices Grant 4,412,142 - Ragonese , et al. October 25, 1 | 1983-10-25 |