Onsongo; David M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Onsongo; David M..The latest application filed is for "heat source integration for electromigration analysis".

Company Profile

0.16.11

Onsongo; David M. - Manor TX
Onsongo; David M. - Newburgh NY US
Onsongo; David M. - Austin TX US
Onsongo; David M. - Byron MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Heat source integration for electromigration analysis Grant 9,710,577 - Baumgartner , et al. July 18, 2	2017-07-18
Heat Source Integration For Electromigration Analysis App 20170103146 - Baumgartner; Steven J. ; et al.	2017-04-13
Bias-temperature induced damage mitigation circuit Grant 9,405,311 - Onsongo , et al. August 2, 2	2016-08-02
Bias-temperature induced damage mitigation circuit Grant 9,401,643 - Onsongo , et al. July 26, 2	2016-07-26
Calibrating on-chip resistors via a daisy chain scheme Grant 8,451,021 - Fox , et al. May 28, 2	2013-05-28
Field effect transistor having multiple conduction states Grant 8,405,165 - Chidambarrao , et al. March 26, 2	2013-03-26
Structure And Method For Forming A Light Detecting Diode And A Light Emitting Diode On A Silicon-on-insulator Wafer Backside App 20130015502 - Fox; Benjamin A. ; et al.	2013-01-17
Structure and method for forming a light detecting diode and a light emitting diode on a silicon-on-insulator wafer backside Grant 8,354,678 - Fox , et al. January 15, 2	2013-01-15
CMOS diodes with dual gate conductors, and methods for forming the same Grant 8,222,702 - Onsongo , et al. July 17, 2	2012-07-17
Cmos Diodes With Dual Gate Conductors, And Methods For Forming The Same App 20100252881 - Onsongo; David M. ; et al.	2010-10-07
Multiple conduction state devices having differently stressed liners Grant 7,768,041 - Chidambarrao , et al. August 3, 2	2010-08-03
CMOS diodes with dual gate conductors, and methods for forming the same Grant 7,737,500 - Onsongo , et al. June 15, 2	2010-06-15
Silicon/silcion germaninum/silicon body device with embedded carbon dopant Grant 7,560,326 - Mocuta , et al. July 14, 2	2009-07-14
N-fets With Tensilely Strained Semiconductor Channels, And Method For Fabricating Same Using Buried Pseudomorphic Layers App 20080179636 - Chidambarrao; Dureseti ; et al.	2008-07-31
Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models Grant 7,337,420 - Chidambarrao , et al. February 26, 2	2008-02-26
Multiple Conduction State Devices Having Differently Stressed Liners App 20070296001 - Chidambarrao; Dureseti ; et al.	2007-12-27
Silicon/silcion Germaninum/silicon Body Device With Embedded Carbon Dopant App 20070257249 - Mocuta; Anda C. ; et al.	2007-11-08
Improved Cmos Diodes With Dual Gate Conductors, And Methods For Forming The Same App 20070252212 - Onsongo; David M. ; et al.	2007-11-01
Programming and determining state of electrical fuse using field effect transistor having multiple conduction states Grant 7,242,239 - Hanson , et al. July 10, 2	2007-07-10
Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models App 20070028195 - Chidambarrao; Dureseti ; et al.	2007-02-01
Structure And Method Of Making Field Effect Transistor Having Multiple Conduction States App 20060273393 - Chidambarrao; Dureseti ; et al.	2006-12-07
Programming And Determining State Of Electrical Fuse Using Field Effect Transistor Having Multiple Conduction States App 20060273841 - Hanson; David R. ; et al.	2006-12-07
Sense amplifier including multiple conduction state field effect transistor Grant 7,123,529 - Hanson , et al. October 17, 2	2006-10-17

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