NETSPEED SYSTEMS, INC.

Patent Applications and Registrations

Patent applications and USPTO patent grants for NETSPEED SYSTEMS, INC..The latest application filed is for "application mapping on hardened network-on-chip (noc) of field-programmable gate array (fpga)".

Company Profile

31.47.65

NETSPEED SYSTEMS, INC. - San Jose CA US
NetSpeed Systems, Inc. - Santa Jose CA
NetSpeed Systems, Inc. -

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Application Mapping On Hardened Network-on-chip (noc) Of Field-programmable Gate Array (fpga) App 20220012177 - KUMAR; Sailesh	2022-01-13
System on chip (SoC) builder Grant 11,176,302 - Rao , et al. November 16, 2	2021-11-16
Enhanced page locality in network-on-chip (NoC) architectures Grant 11,144,457 - Rowlands , et al. October 12, 2	2021-10-12
Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA) Grant 11,023,377 - Kumar June 1, 2	2021-06-01
Bandwidth weighting mechanism based network-on-chip (NoC) configuration Grant 10,983,910 - Rowlands , et al. April 20, 2	2021-04-20
Repository of integration description of hardware intellectual property for NoC construction and SoC integration Grant 10,896,476 - Rao , et al. January 19, 2	2021-01-19
Interface virtualization and fast path for Network on Chip Grant 10,749,811 - Rowlands , et al. A	2020-08-18
Interface virtualization and fast path for network on chip Grant 10,735,335 - Rowlands , et al.	2020-08-04
Systems and methods for facilitating low power on a network-on-chip Grant 10,613,616 - Bauman , et al.	2020-04-07
Systems and methods for facilitating low power on a network-on-chip Grant 10,564,704 - Bauman , et al. Feb	2020-02-18
Systems and methods for facilitating low power on a network-on-chip Grant 10,564,703 - Bauman , et al. Feb	2020-02-18
Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation Grant 10,547,514 - Rao , et al. Ja	2020-01-28
Buffer sizing of a NoC through machine learning Grant 10,523,599 - Norige , et al. Dec	2019-12-31
Cost management against requirements for the generation of a NoC Grant 10,469,338 - Bainbridge , et al. No	2019-11-05
Cost management against requirements for the generation of a NoC Grant 10,469,337 - Bainbridge , et al. No	2019-11-05
Systems and methods for facilitating low power on a network-on-chip Grant 10,452,124 - Bauman , et al. Oc	2019-10-22
Cost management against requirements for the generation of a NoC Grant 10,419,300 - Bainbridge , et al. Sept	2019-09-17
Application Mapping On Hardened Network-on-chip (noc) Of Field-programmable Gate Array (fpga) App 20190266089 - KUMAR; Sailesh	2019-08-29
System On Chip (soc) Builder App 20190266307 - RAO; Nishant ; et al.	2019-08-29
Backbone Network-on-chip (noc) For Field-programmable Gate Array (fpga) App 20190266088 - KUMAR; Sailesh	2019-08-29
Systems And Methods For Maintaining Network-on-chip (noc) Safety And Reliability App 20190260504 - Philip; Joji ; et al.	2019-08-22
Enhanced Page Locality In Network-on-chip (noc) Architectures App 20190258572 - ROWLANDS; Joseph ; et al.	2019-08-22
Repository Of Integration Description Of Hardware Intellectual Property For Noc Construction And Soc Integration App 20190259113 - RAO; Nishant ; et al.	2019-08-22
Bandwidth Weighting Mechanism Based Network-on-chip (noc) Configuration App 20190258573 - ROWLANDS; Joseph ; et al.	2019-08-22
Automatic Crossbar Generation And Router Connections For Network-on-chip (noc) Topology Generation App 20190260644 - RAO; Nishant ; et al.	2019-08-22
System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology Grant 10,348,563 - Rao , et al. July 9, 2	2019-07-09
System and method for network on chip construction through machine learning Grant 10,313,269 - Raponi	2019-06-04
Systems and methods for NoC construction Grant 10,298,485 - Raponi , et al.	2019-05-21
Buffer Sizing of a NoC Through Machine Learning App 20180324113 - NORIGE; Eric ; et al.	2018-11-08
Generation Of Network-on-chip Layout Based On User Specified Topological Constraints App 20180302293 - RAPONI; Pier Giorgio ; et al.	2018-10-18
Extracting features from a NoC for machine learning construction Grant 10,084,725 - Raponi , et al. September 25, 2	2018-09-25
Streaming bridge design with host interfaces and network on chip (NoC) layers Grant 10,084,692 - Chopra , et al. September 25, 2	2018-09-25
Buffer sizing of a NoC through machine learning Grant 10,063,496 - Norige , et al. August 28, 2	2018-08-28
System-on-chip (soc) Optimization Through Transformation And Generation Of A Network-on-chip (noc) Topology App 20180227180 - RAO; Nishant ; et al.	2018-08-09
Systems and Methods for NoC Construction App 20180227215 - RAPONI; Pier Giorgio ; et al.	2018-08-09
Cost Management Against Requirements for the Generation of a NoC App 20180219738 - BAINBRIDGE; William John ; et al.	2018-08-02
Cost Management Against Requirements for the Generation of a NoC App 20180219747 - BAINBRIDGE; William John ; et al.	2018-08-02
Cost Management Against Requirements for the Generation of a NoC App 20180219746 - BAINBRIDGE; William John ; et al.	2018-08-02
Strategies for NoC Construction Using Machine Learning App 20180198682 - RAO; Nishant ; et al.	2018-07-12
EXTRACTING FEATURES FROM A NoC FOR MACHINE LEARNING CONSTRUCTION App 20180198734 - RAPONI; Pier Giorgio ; et al.	2018-07-12
Metrics to Train Machine Learning Predictor for NoC Construction App 20180197110 - RAO; Nishant ; et al.	2018-07-12
Buffer Sizing of a NoC Through Machine Learning App 20180198738 - NORIGE; Eric ; et al.	2018-07-12
Infrastructure to Apply Machine Learning for NoC Construction App 20180198687 - RAO; Nishant ; et al.	2018-07-12
Interface Virtualization And Fast Path For Network On Chip App 20180191626 - ROWLANDS; Joseph ; et al.	2018-07-05
Traffic Mapping Of A Network On Chip Through Machine Learning App 20180183726 - KUMAR; Sailesh ; et al.	2018-06-28
System And Method For Network On Chip Construction Through Machine Learning App 20180183715 - Raponi; Pier Giorgio	2018-06-28
Traffic Mapping Of A Network On Chip Through Machine Learning App 20180183728 - KUMAR; Sailesh ; et al.	2018-06-28
System And Method For Grouping Of Network On Chip (noc) Elements App 20180183672 - NORIGE; Eric ; et al.	2018-06-28
Interface Virtualization And Fast Path For Network On Chip App 20180183721 - ROWLANDS; Joseph ; et al.	2018-06-28
Systems And Methods For Facilitating Low Power On A Network-on-chip App 20180181190 - BAUMAN; James A. ; et al.	2018-06-28
Automatic Generation Of Power Management Sequence In A Soc Or Noc App 20180181174 - GANGWAR; Anup ; et al.	2018-06-28
Automatic Generation Of Power Management Sequence In A Soc Or Noc App 20180181173 - GANGWAR; Anup ; et al.	2018-06-28
Interface Virtualization And Fast Path For Network On Chip App 20180183722 - ROWLANDS; Joseph ; et al.	2018-06-28
Traffic Mapping Of A Network On Chip Through Machine Learning App 20180183727 - KUMAR; Sailesh ; et al.	2018-06-28
Systems And Methods For Facilitating Low Power On A Network-on-chip App 20180181192 - BAUMAN; James A. ; et al.	2018-06-28
Systems And Methods For Facilitating Low Power On A Network-on-chip App 20180181191 - BAUMAN; James A. ; et al.	2018-06-28
Interface Virtualization And Fast Path For Network On Chip App 20180159786 - Rowlands; Joseph ; et al.	2018-06-07
Transaction expansion for NoC simulation and NoC design Grant 9,928,204 - Norige , et al. March 27, 2	2018-03-27
Systems And Methods For Facilitating Low Power On A Network-on-chip App 20180074572 - BAUMAN; James A. ; et al.	2018-03-15
Automatic generation of physically aware aggregation/distribution networks Grant 9,864,728 - Norige , et al. January 9, 2	2018-01-09
Automatic buffer sizing for optimal network-on-chip design Grant 9,860,197 - Kumar January 2, 2	2018-01-02
Hardware and software enabled implementation of power profile management instructions in system on chip Grant 9,829,962 - Kaushal , et al. November 28, 2	2017-11-28
Reuse of directory entries for holding state information through use of multiple formats Grant 9,830,265 - Rowlands , et al. November 28, 2	2017-11-28
Automatic buffer sizing for optimal network-on-chip design Grant 9,825,887 - Kumar November 21, 2	2017-11-21
Verification low power collateral generation Grant 9,785,732 - Pusuluri , et al. October 10, 2	2017-10-10
STREAMING BRIDGE DESIGN WITH HOST INTERFACES AND NETWORK ON CHIP (NoC) LAYERS App 20170264533 - Chopra; Rajesh ; et al.	2017-09-14
Automatic Buffer Sizing For Optimal Network-on-chip Design App 20170171115 - KUMAR; Sailesh	2017-06-15
Automatic Buffer Sizing For Optimal Network-on-chip Design App 20170163574 - KUMAR; Sailesh	2017-06-08
CONGESTION CONTROL AND QoS IN NoC BY REGULATING THE INJECTION TRAFFIC App 20170111283 - Kumar; Sailesh ; et al.	2017-04-20
Hardware And Software Enabled Implementation Of Power Profile Management Instructions In System On Chip App 20170097672 - Kaushal; Rimu ; et al.	2017-04-06
Hardware and software enabled implementation of power profile management instructions in system on chip Grant 9,568,970 - Kaushal , et al. February 14, 2	2017-02-14

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.