Murray; Conal E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Murray; Conal E..The latest application filed is for "semiconductor device with reduced via resistance".

Company Profile

14.78.76

Murray; Conal E. - Yorktown Heights NY
Murray; Conal E - Yorktown Heights NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device with reduced via resistance Grant 11,222,815 - Murray , et al. January 11, 2	2022-01-11
Semiconductor Device With Reduced Via Resistance App 20210183699 - Murray; Conal E. ; et al.	2021-06-17
Semiconductor device with reduced via resistance Grant 10,804,147 - Murray , et al. October 13, 2	2020-10-13
Reducing contact resistance in vias for copper interconnects Grant 10,714,379 - Murray , et al.	2020-07-14
Semiconductor Device With Reduced Via Resistance App 20200090993 - Murray; Conal E. ; et al.	2020-03-19
Semiconductor Device With Reduced Via Resistance App 20200090994 - Murray; Conal E. ; et al.	2020-03-19
Reducing Contact Resistance In Vias For Copper Interconnects App 20200066576 - Murray; Conal E. ; et al.	2020-02-27
Semiconductor device with reduced via resistance Grant 10,553,483 - Murray , et al. Fe	2020-02-04
Reducing contact resistance in vias for copper interconnects Grant 10,468,296 - Murray , et al. No	2019-11-05
Hybrid interconnects and method of forming the same Grant 10,446,491 - Murray , et al. Oc	2019-10-15
Method for forming improved liner layer and semiconductor device including the same Grant 10,424,504 - Murray , et al. Sept	2019-09-24
Activating reactions in integrated circuits through electrical discharge Grant 10,388,615 - Cabral, Jr. , et al. A	2019-08-20
Reducing contact resistance in vias for copper interconnects Grant 10,361,115 - Murray , et al.	2019-07-23
Activating reactions in integrated circuits through electrical discharge Grant 10,262,955 - Cabral, Jr. , et al.	2019-04-16
Forming a stacked capacitor Grant 10,242,943 - Murray , et al.	2019-03-26
Reducing contact resistance in vias for copper interconnects Grant 10,170,358 - Murray , et al. J	2019-01-01
Semiconductor device interconnect structures formed by metal reflow process Grant 10,109,586 - Murray , et al. October 23, 2	2018-10-23
Capacitance monitoring using x-ray diffraction Grant 10,008,421 - Kang , et al. June 26, 2	2018-06-26
Semiconductor Device With Reduced Via Resistance App 20180174903 - Murray; Conal E. ; et al.	2018-06-21
Columnar interconnects and method of making them Grant 9,997,406 - Murray , et al. June 12, 2	2018-06-12
Activating reactions in integrated circuits through electrical discharge Grant 9,991,214 - Cabral, Jr. , et al. June 5, 2	2018-06-05
Forming a Stacked Capacitor App 20180122740 - Murray; Conal E. ; et al.	2018-05-03
Semiconductor device with reduced via resistance Grant 9,953,869 - Murray , et al. April 24, 2	2018-04-24
Capacitance Monitoring Using X-ray Diffraction App 20180096904 - Kang; Donghun ; et al.	2018-04-05
Treating copper interconnects Grant 9,929,092 - Murray , et al. March 27, 2	2018-03-27
Activating Reactions In Integrated Circuits Through Electrical Discharge App 20180061782 - Cabral, JR.; Cyril ; et al.	2018-03-01
Forming a stacked capacitor Grant 9,875,959 - Murray , et al. January 23, 2	2018-01-23
Method For Forming Improved Liner Layer And Semiconductor Device Including The Same App 20180019163 - Murray; Conal E. ; et al.	2018-01-18
Method For Forming Improved Liner Layer And Semiconductor Device Including The Same App 20180019164 - Murray; Conal E. ; et al.	2018-01-18
Capacitance monitoring using X-ray diffraction Grant 9,870,960 - Kang , et al. January 16, 2	2018-01-16
Hybrid Interconnects And Method Of Forming The Same App 20180012841 - Murray; Conal E. ; et al.	2018-01-11
Semiconductor device with reduced via resistance Grant 9,859,160 - Murray , et al. January 2, 2	2018-01-02
Method for forming improved liner layer and semiconductor device including the same Grant 9,859,157 - Murray , et al. January 2, 2	2018-01-02
Forming A Stacked Capacitor App 20170358529 - Murray; Conal E. ; et al.	2017-12-14
Treating Copper Interconnects App 20170287830 - Murray; Conal E. ; et al.	2017-10-05
Treating copper interconnects Grant 9,748,169 - Murray , et al. August 29, 2	2017-08-29
Hybrid interconnects and method of forming the same Grant 9,748,173 - Murray , et al. August 29, 2	2017-08-29
Semiconductor Device Interconnect Structures Formed By Metal Reflow Process App 20170243830 - Murray; Conal E. ; et al.	2017-08-24
Semiconductor device interconnect structures formed by metal reflow process Grant 9,735,051 - Murray , et al. August 15, 2	2017-08-15
Columnar Interconnects And Method Of Making Them App 20170229344 - MURRAY; Conal E. ; et al.	2017-08-10
Semiconductor Device Interconnect Structures Formed By Metal Reflow Process App 20170170062 - Murray; Conal E. ; et al.	2017-06-15
Reducing Contact Resistance In Vias For Copper Interconnects App 20160358859 - Murray; Conal E. ; et al.	2016-12-08
Reducing Contact Resistance In Vias For Copper Interconnects App 20160358812 - Murray; Conal E. ; et al.	2016-12-08
Structure and method to determine through silicon via build integrity Grant 9,476,927 - Graves-Abe , et al. October 25, 2	2016-10-25
Activating Reactions In Integrated Circuits Through Electrical Discharge App 20160300802 - Cabral, JR.; Cyril ; et al.	2016-10-13
Method and structure for determining thermal cycle reliability Grant 9,443,776 - Filippi , et al. September 13, 2	2016-09-13
Activating reactions in integrated circuits through electrical discharge Grant 9,431,354 - Cabral, Jr. , et al. August 30, 2	2016-08-30
Semiconductor Device With Reduced Via Resistance App 20160204069 - Murray; Conal E. ; et al.	2016-07-14
Semiconductor Device With Reduced Via Resistance App 20160197010 - Murray; Conal E. ; et al.	2016-07-07
Capacitance Monitoring Using X-ray Diffraction App 20160178679 - Kang; Donghun ; et al.	2016-06-23
Activating Reactions In Integrated Circuits Through Electrical Discharge App 20160163658 - Cabral, JR.; Cyril ; et al.	2016-06-09
Semiconductor device with reduced via resistance Grant 9,349,691 - Murray , et al. May 24, 2	2016-05-24
Activating Reactions In Integrated Circuits Through Electrical Discharge App 20160133581 - Cabral, Jr.; Cyril ; et al.	2016-05-12
Semiconductor Device With Reduced Via Resistance App 20160027738 - Murray; Conal E. ; et al.	2016-01-28
Method And Structure For Determining Thermal Cycle Reliability App 20150262899 - FILIPPI; RONALD G. ; et al.	2015-09-17
Structure And Method To Determine Through Silicon Via Build Integrity App 20150204932 - Graves-Abe; Troy L. ; et al.	2015-07-23
Reprogrammable electrical fuse Grant 9,058,887 - Hsu , et al. June 16, 2	2015-06-16
Surface repair structure and process for interconnect applications Grant 8,802,563 - Yang , et al. August 12, 2	2014-08-12
Annealing copper interconnects Grant 8,772,161 - Cabral, Jr. , et al. July 8, 2	2014-07-08
Measurement Of Cmos Device Channel Strain By X-ray Diffraction App 20140159161 - Adam; Thomas N. ; et al.	2014-06-12
Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process Grant 8,716,695 - Cohen , et al. May 6, 2	2014-05-06
Measurement of CMOS device channel strain by X-ray diffraction Grant 8,716,037 - Adam , et al. May 6, 2	2014-05-06
Redundancy design with electro-migration immunity and method of manufacture Grant 8,624,395 - Hsu , et al. January 7, 2	2014-01-07
Compressive (PFET) and Tensile (NFET) Channel Strain in Nanowire FETs Fabricated With a Replacement Gate Process App 20130285020 - Cohen; Guy ; et al.	2013-10-31
Nanowire FET having induced radial strain Grant 8,564,025 - Bangsaruntip , et al. October 22, 2	2013-10-22
Redundancy design with electro-migration immunity and method of manufacture Grant 8,450,205 - Hsu , et al. May 28, 2	2013-05-28
p-FET with a strained nanowire channel and embedded SiGe source and drain stressors Grant 8,445,892 - Cohen , et al. May 21, 2	2013-05-21
Interconnect structure and method for Cu/ultra low k integration Grant 8,405,215 - Yang , et al. March 26, 2	2013-03-26
p-FET with a strained nanowire channel and embedded SiGe source and drain stressors Grant 8,399,314 - Cohen , et al. March 19, 2	2013-03-19
Silicidation Of Device Contacts Using Pre-amorphization Implant Of Semiconductor Substrate App 20130049200 - Besser; Paul R. ; et al.	2013-02-28
Silicidation Of Device Contacts Using Pre-amorphization Implant Of Semiconductor Substrate App 20130049199 - Besser; Paul R. ; et al.	2013-02-28
Annealing Copper Interconnects App 20130040454 - Cabral, JR.; Cyril ; et al.	2013-02-14
Surface Repair Structure And Process For Interconnect Applications App 20120329270 - Yang; Chih-Chao ; et al.	2012-12-27
Nanowire Fet Having Induced Radial Strain App 20120298948 - Bangsaruntip; Sarunya ; et al.	2012-11-29
Nanowire FET having induced radial strain Grant 8,313,990 - Bangsaruntip , et al. November 20, 2	2012-11-20
Nanoelectromechanical Structures Exhibiting Tensile Stress And Techniques For Fabrication Thereof App 20120286377 - Chang; Josephine B. ; et al.	2012-11-15
Nanowire FET having induced radial strain Grant 8,309,991 - Bangsaruntip , et al. November 13, 2	2012-11-13
A p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors App 20120280211 - Cohen; Guy ; et al.	2012-11-08
Redundancy Design With Electro-migration Immunity And Method Of Manufacture App 20120225549 - HSU; Louis L. ; et al.	2012-09-06
Dosimeter powered by passive RF absorption Grant 8,212,218 - Cabral, Jr. , et al. July 3, 2	2012-07-03
Redundancy Design With Electro-migration Immunity And Method Of Manufacture App 20120161334 - HSU; Louis L. ; et al.	2012-06-28
Measurement Of Cmos Device Channel Strain By X-ray Diffraction App 20120146050 - ADAM; THOMAS N. ; et al.	2012-06-14
Air channel interconnects for 3-D integration Grant 8,198,174 - Hsu , et al. June 12, 2	2012-06-12
Redundancy design with electro-migration immunity Grant 8,138,603 - Hsu , et al. March 20, 2	2012-03-20
p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors App 20110233522 - Cohen; Guy ; et al.	2011-09-29
Nanowire Fet Having Induced Radial Strain App 20110133166 - Bangsaruntip; Sarunya ; et al.	2011-06-09
Nanowire Fet Having Induced Radial Strain App 20110133163 - Bangsaruntip; Sarunya ; et al.	2011-06-09
Dosimeter Powered by Passive RF Absorption App 20110127438 - Cabral, JR.; Cyril ; et al.	2011-06-02
Electronics structures using a sacrificial multi-layer hardmask scheme Grant 7,947,907 - Colburn , et al. May 24, 2	2011-05-24
Varying capacitance voltage contrast structures to determine defect resistance Grant 7,927,895 - Lavoie , et al. April 19, 2	2011-04-19
Method and structure for reducing contact resistance between silicide contact and overlying metallization Grant 7,923,838 - Lavoie , et al. April 12, 2	2011-04-12
Varying Capacitance Voltage Contrast Structures To Determine Defect Resistance App 20110080180 - Lavoie; Christian ; et al.	2011-04-07
Air Channel Interconnects For 3-d Integration App 20110031633 - Hsu; Louis L. ; et al.	2011-02-10
INTERCONNECT STRUCTURE AND METHOD FOR Cu/ULTRA LOW k INTEGRATION App 20110031623 - Yang; Chih-Chao ; et al.	2011-02-10
Computer program products for determining stopping powers of design structures with respect to a traveling particle Grant 7,877,716 - Fiorenza , et al. January 25, 2	2011-01-25
Non-plasma capping layer for interconnect applications Grant 7,871,935 - Yang , et al. January 18, 2	2011-01-18
Interconnect structure and method for Cu/ultra low k integration Grant 7,846,834 - Yang , et al. December 7, 2	2010-12-07
Carbon-on-insulator substrates by in-place bonding Grant 7,811,906 - Bol , et al. October 12, 2	2010-10-12
Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure Grant 7,786,578 - Detavenier , et al. August 31, 2	2010-08-31
Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure Grant 7,732,870 - Detavenier , et al. June 8, 2	2010-06-08
Surface Repair Structure And Process For Interconnect Applications App 20100084766 - Yang; Chih-Chao ; et al.	2010-04-08
Redundancy Design With Electro-migration Immunity And Method Of Manufacture App 20090278260 - Hsu; Louis L. ; et al.	2009-11-12
Non-plasma Capping Layer For Interconnect Applications App 20090269929 - Yang; Chih-Chao ; et al.	2009-10-29
INTERCONNECT STRUCTURE AND METHOD FOR Cu/ULTRA LOW k INTEGRATION App 20090194876 - Yang; Chih-Chao ; et al.	2009-08-06
Method of room temperature growth of SiO.sub.x on silicide as an etch stop layer for metal contact open of semiconductor devices Grant 7,538,029 - Wang , et al. May 26, 2	2009-05-26
Reprogrammable Electrical Fuse App 20090109722 - Hsu; Louis C. ; et al.	2009-04-30
Method and structure for reducing contact resistance between silicide contact and overlying metallization Grant 7,491,643 - Lavoie , et al. February 17, 2	2009-02-17
Deflection analysis system and method for circuit design Grant 7,475,368 - Angyal , et al. January 6, 2	2009-01-06
Building metal pillars in a chip for structure support Grant 7,456,098 - Hichri , et al. November 25, 2	2008-11-25
Structure For Optimizing Fill In Semiconductor Features Deposited By Electroplating App 20080284036 - Murray; Conal E. ; et al.	2008-11-20
Structure for optimizing fill in semiconductor features deposited by electroplating Grant 7,446,040 - Murray , et al. November 4, 2	2008-11-04
Electronics Structures Using a Sacrificial Multi-Layer Hardmask Scheme App 20080251284 - Colburn; Matthew Earl ; et al.	2008-10-16
ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS Ni ALLOY SILICIDE STRUCTURE App 20080217781 - Detavernier; Christophe ; et al.	2008-09-11
ELIMINATING METAL-RICH SILICIDES USING AN AMORPHOUS Ni ALLOY SILICIDE STRUCTURE App 20080217780 - Detavernier; Christophe ; et al.	2008-09-11
Method And Structure For Reducing Contact Resistance Between Silicide Contact And Overlying Metallization App 20080211100 - Lavoie; Christian ; et al.	2008-09-04
Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure Grant 7,419,907 - Detavernier , et al. September 2, 2	2008-09-02
Computer Program Products For Determining Stopping Powers Of Design Structures With Respect To A Traveling Particle App 20080201681 - Fiorenza; Giovanni ; et al.	2008-08-21
Method Of Determining Stopping Powers Of Design Structures With Respect To A Traveling Particle App 20080163137 - Fiorenza; Giovanni ; et al.	2008-07-03
Method of determining stopping powers of design structures with respect to a traveling particle Grant 7,386,817 - Fiorenza , et al. June 10, 2	2008-06-10
Process for preparing electronics structures using a sacrificial multilayer hardmask scheme Grant 7,371,684 - Colburn , et al. May 13, 2	2008-05-13
Reprogrammable Electrical Fuse App 20080023789 - Hsu; Louis C. ; et al.	2008-01-31
Method and structure for reducing contact resistance between silicide contact and overlying metallization App 20070275548 - Lavoie; Christian ; et al.	2007-11-29
Reprogrammable electrical fuse Grant 7,298,639 - Hsu , et al. November 20, 2	2007-11-20
Deflection analysis system and method for circuit design App 20070174796 - Angyal; Matthew S. ; et al.	2007-07-26
Structure for optimizing fill in semiconductor features deposited by electroplating App 20070161239 - Murray; Conal E. ; et al.	2007-07-12
Apparatus and method for flattening a warped substrate Grant 7,214,548 - Fayaz , et al. May 8, 2	2007-05-08
Heat dissipation for heat generating element of semiconductor device and related method Grant 7,166,913 - Chinthakindi , et al. January 23, 2	2007-01-23
METHOD OF ROOM TEMPERATURE GROWTH OF SIOx ON SILICIDE AS AN ETCH STOP LAYER FOR METAL CONTACT OPEN OF SEMICONDUCTOR DEVICES App 20070010093 - Wang; Yun-Yu ; et al.	2007-01-11
Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure App 20070004205 - Detavernier; Christophe ; et al.	2007-01-04
Process for preparing electronics structures using a sacrificial multilayer hardmask scheme App 20060258159 - Colburn; Matthew Earl ; et al.	2006-11-16
Reprogrammable Electrical Fuse App 20060249808 - Hsu; Louis C. ; et al.	2006-11-09
Heat Dissipation For Heat Generating Element Of Semiconductor Device And Related Method App 20060231945 - Chinthakindi; Anil K. ; et al.	2006-10-19
Building metal pillars in a chip for structure support App 20060190846 - Hichri; Habib ; et al.	2006-08-24
Method Of Forming Images In A Scanning Electron Microscope App 20060169894 - Gignac; Lynne M. ; et al.	2006-08-03
Building metal pillars in a chip for structure support Grant 7,067,902 - Hichri , et al. June 27, 2	2006-06-27
Apparatus and method for flattening a warped substrate App 20060055073 - Fayaz; Mohammed F. ; et al.	2006-03-16
Stacked via-stud with improved reliability in copper metallurgy App 20060014376 - Agarwala; Birendra N. ; et al.	2006-01-19
Stacked via-stud with improved reliability in copper metallurgy Grant 6,972,209 - Agarwala , et al. December 6, 2	2005-12-06
Building metal pillars in a chip for structure support App 20050118803 - Hichri, Habib ; et al.	2005-06-02
Method for SEM measurement of topological features Grant 6,768,111 - Wells , et al. July 27, 2	2004-07-27
Stacked via-stud with improved reliability in copper metallurgy App 20040101663 - Agarwala, Birendra N. ; et al.	2004-05-27

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