loadpatents
name:-0.015913009643555
name:-0.018566846847534
name:-0.00039482116699219
Murarka; Shyam P. Patent Filings

Murarka; Shyam P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Murarka; Shyam P..The latest application filed is for "chemical treatment of material surfaces".

Company Profile
0.16.8
  • Murarka; Shyam P. - Clifton Park NY
  • Murarka, Shyam P. - US
  • Murarka; Shyam P. - New Providence NJ
  • Murarka; Shyam P. - New Providenc NJ
  • Murarka; Shyam P. - Murray Hill NJ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Siloxane epoxy polymers as metal diffusion barriers to reduce electromigration
Grant 7,285,842 - Wang , et al. October 23, 2
2007-10-23
Diffusion barriers comprising a self-assembled monolayer
Grant 7,202,159 - Ganapathiraman , et al. April 10, 2
2007-04-10
Siloxane epoxy polymers for low-k dielectric applications
Grant 7,019,386 - Ghoshal , et al. March 28, 2
2006-03-28
Siloxane epoxy polymers as metal diffusion barriers to reduce electromigration
App 20050236711 - Wang, Pei-I ;   et al.
2005-10-27
Siloxane epoxy polymers for low-k dielectric applications
App 20050236695 - Ghoshal, Ramkrishna ;   et al.
2005-10-27
Chemical treatment of material surfaces
App 20050239295 - Wang, Pei-l ;   et al.
2005-10-27
Diffusion barriers comprising a self-assembled monolayer
App 20040180506 - Ramanath, G. ;   et al.
2004-09-16
Surface modification for barrier to ionic penetration
App 20030087534 - Mallikarjunan, Anupama ;   et al.
2003-05-08
Metallization structures for microelectronic applications and process for forming the structures
Grant 6,486,533 - Krishnamoorthy , et al. November 26, 2
2002-11-26
Self-assembled near-zero-thickness molecular layers as diffusion barriers for Cu metallization
App 20020105081 - Ramanath, G. ;   et al.
2002-08-08
Diffusion barriers comprising a self-assembled monolayer
App 20020079487 - Ramanath, G. ;   et al.
2002-06-27
Metallization structures for microelectronic applications and process for forming the structures
App 20020050628 - Krishnamoorthy, Ahila ;   et al.
2002-05-02
Metallization structures for microelectronic applications and process for forming the structures
Grant 6,368,966 - Krishnamoorthy , et al. April 9, 2
2002-04-09
Copper alloy electroplating bath for microelectronic applications
Grant 6,319,387 - Krishnamoorthy , et al. November 20, 2
2001-11-20
Systems for performing chemical mechanical planarization and process for conducting same
Grant 5,637,185 - Murarka , et al. June 10, 1
1997-06-10
Method for making integrated semiconductor circuit structure with formation of Ti or Ta silicide
Grant RE32,207 - Levinstein , et al. July 15, 1
1986-07-15
Boron nitride X-ray masks with controlled stress
Grant 4,522,842 - Levinstein , et al. June 11, 1
1985-06-11
Cobalt silicide metallization for semiconductor integrated circuits
Grant 4,378,628 - Levinstein , et al. April 5, 1
1983-04-05
Silicon rich refractory silicides as gate metal
Grant 4,337,476 - Fraser , et al. June 29, 1
1982-06-29
Method for making integrated semiconductor circuit structure with formation of Ti or Ta silicide
Grant 4,332,839 - Levinstein , et al. June 1, 1
1982-06-01
Method of fabricating MOS field effect transistors
Grant 4,324,038 - Chang , et al. April 13, 1
1982-04-13
Integrated semiconductor circuit structure and method for making it
Grant 4,276,557 - Levinstein , et al. June 30, 1
1981-06-30
Method of limiting stacking faults in oxidized silicon wafers
Grant 4,149,905 - Levinstein , et al. April 17, 1
1979-04-17
Passivation of metallized semiconductor substrates
Grant 4,134,125 - Adams , et al. January 9, 1
1979-01-09

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