May; Charles E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for May; Charles E..The latest application filed is for "method for redirecting void diffusion away from vias in an integrated circuit design".

Company Profile

0.59.12

May; Charles E. - Gresham OR
May; Charles E. - Fairview OR
May; Charles E. - Austin TX
May, Charles E. - Greshman OR
May; Charles E - Austin TX
May; Charles E. - Rocky River OH

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Arrangement and method for fabricating a semiconductor wafer Grant 7,601,643 - May October 13, 2	2009-10-13
Method for redirecting void diffusion away from vias in an integrated circuit design Grant 7,582,566 - Allman , et al. September 1, 2	2009-09-01
Method and apparatus for diverting void diffusion in integrated circuit conductors Grant 7,436,040 - Allman , et al. October 14, 2	2008-10-14
Method For Redirecting Void Diffusion Away From Vias In An Integrated Circuit Design App 20080132065 - Allman; Derryl D. J. ; et al.	2008-06-05
Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design Grant 7,361,965 - Allman , et al. April 22, 2	2008-04-22
Method and apparatus for diverting void diffusion in integrated circuit conductors App 20070259518 - Allman; Derryl D.J. ; et al.	2007-11-08
Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design App 20070155160 - Allman; Derryl D. J. ; et al.	2007-07-05
Bond pad design Grant 7,023,067 - Allman , et al. April 4, 2	2006-04-04
Extreme low-K interconnect structure and method App 20060006538 - Allman; Derryl D. J. ; et al.	2006-01-12
Temperature control system App 20050279284 - May, Charles E. ; et al.	2005-12-22
Temperature control system Grant 6,967,177 - May , et al. November 22, 2	2005-11-22
Via and metal line interface capable of reducing the incidence of electro-migration induced voids Grant 6,875,693 - May , et al. April 5, 2	2005-04-05
Via and metal line interface capable of reducing the incidence of electro-migration induced voids App 20050064708 - May, Charles E. ; et al.	2005-03-24
Ion implantation phase shift mask App 20040241554 - Rissman, Paul ; et al.	2004-12-02
Bond pad design App 20040135223 - Allman, Derryl D.J. ; et al.	2004-07-15
High performance MOSFET with modulated channel gate thickness Grant 6,743,688 - Gardner , et al. June 1, 2	2004-06-01
Semiconductor wafer arrangement of a semiconductor wafer Grant 6,707,114 - May , et al. March 16, 2	2004-03-16
Thermal low k dielectrics Grant 6,654,226 - May , et al. November 25, 2	2003-11-25
Ion beam dual damascene process App 20030203620 - May, Charles E.	2003-10-30
Thermal characterization compensation Grant 6,638,776 - May October 28, 2	2003-10-28
Ion beam dual damascene process Grant 6,620,729 - May September 16, 2	2003-09-16
Thermal low k dielectrics App 20030170973 - May, Charles E. ; et al.	2003-09-11
Thermal characterization compensation App 20030157735 - May, Charles E.	2003-08-21
Use of contamination-free manufacturing data in fault detection and classification as well as in run-to-run control Grant 6,560,504 - Goodwin , et al. May 6, 2	2003-05-06
Coupling capacitance reduction App 20030013298 - May, Charles E.	2003-01-16
Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography Grant 6,452,412 - Jarvis , et al. September 17, 2	2002-09-17
Method of coupling capacitance reduction Grant 6,432,812 - May August 13, 2	2002-08-13
Transistor having enhanced metal silicide and a self-aligned gate electrode Grant 6,410,967 - Hause , et al. June 25, 2	2002-06-25
Semiconductor topography having improved active device isolation and reduced dopant migration Grant 6,362,510 - Gardner , et al. March 26, 2	2002-03-26
Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process Grant 6,323,519 - Gardner , et al. November 27, 2	2001-11-27
Spacer formation for precise salicide formation Grant 6,323,561 - Gardner , et al. November 27, 2	2001-11-27
Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures Grant 6,303,962 - Gardner , et al. October 16, 2	2001-10-16
Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment Grant 6,294,397 - Jarvis , et al. September 25, 2	2001-09-25
Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication Grant 6,268,637 - Gardner , et al. July 31, 2	2001-07-31
Buried local interconnect Grant 6,261,908 - Hause , et al. July 17, 2	2001-07-17
Semiconductor device having ultra shallow junctions and a reduced channel length and method for making same Grant 6,261,909 - Gardner , et al. July 17, 2	2001-07-17
Ultrathin deposited gate dielectric formation using low-power, low-pressure PECVD for improved semiconductor device performance Grant 6,251,800 - Sun , et al. June 26, 2	2001-06-26
Fractal filter applied to a contamination-free manufacturing signal to improve signal-to-noise ratios Grant 6,242,273 - Goodwin , et al. June 5, 2	2001-06-05
Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof Grant 6,225,168 - Gardner , et al. May 1, 2	2001-05-01
Integration of high K spacers for dual gate oxide channel fabrication technique Grant 6,207,485 - Gardner , et al. March 27, 2	2001-03-27
Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device Grant 6,204,153 - Gardner , et al. March 20, 2	2001-03-20
Multi-layer gate conductor having a diffusion barrier in the bottom layer Grant 6,160,300 - Gardner , et al. December 12, 2	2000-12-12
Apparatus and method for determining depth profile characteristics of a dopant material in a semiconductor device Grant 6,151,119 - Campion , et al. November 21, 2	2000-11-21
Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions Grant 6,150,222 - Gardner , et al. November 21, 2	2000-11-21
Semiconductor device having self-aligned asymmetric source/drain regions and method of fabrication thereof Grant 6,146,952 - Nariman , et al. November 14, 2	2000-11-14
Ultrathin silicon nitride containing sidewall spacers for improved transistor performance Grant 6,144,071 - Gardner , et al. November 7, 2	2000-11-07
Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate Grant 6,140,691 - Gardner , et al. October 31, 2	2000-10-31
Ion beam milling to generate custom reticles Grant 6,130,012 - May , et al. October 10, 2	2000-10-10
Ultra shallow extension formation using disposable spacers Grant 6,127,234 - Gardner , et al. October 3, 2	2000-10-03
Semiconductor device with layered doped regions and methods of manufacture Grant 6,117,739 - Gardner , et al. September 12, 2	2000-09-12
Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process Grant 6,100,173 - Gardner , et al. August 8, 2	2000-08-08
Process for making high performance MOSFET with scaled gate electrode thickness Grant 6,090,676 - Gardner , et al. July 18, 2	2000-07-18
Trench isolation structure partially bound between a pair of low K dielectric structures Grant 6,087,705 - Gardner , et al. July 11, 2	2000-07-11
Transistor having a metal silicide self-aligned to the gate Grant 6,084,280 - Gardner , et al. July 4, 2	2000-07-04
V-gate transistor Grant 6,078,078 - Gardner , et al. June 20, 2	2000-06-20
Method and apparatus for the molecular identification of defects in semiconductor manufacturing using a radiation scattering technique such as raman spectroscopy Grant 6,067,154 - Hossain , et al. May 23, 2	2000-05-23
Transistor gate conductor having sidewall surfaces upon which a spacer having a profile that substantially prevents silicide bridging is formed Grant 6,051,863 - Hause , et al. April 18, 2	2000-04-18
Selectively sized spacers Grant 6,046,089 - Gardner , et al. April 4, 2	2000-04-04
Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques Grant 6,037,607 - Hause , et al. March 14, 2	2000-03-14
Method for making semiconductor device having nitrogen-rich active region-channel interface Grant 6,030,875 - May , et al. February 29, 2	2000-02-29
Process for formation of isolation trenches with high-K gate dielectrics Grant 6,008,095 - Gardner , et al. December 28, 1	1999-12-28
Trench isolation structure having a low K dielectric encapsulated by oxide Grant 6,008,109 - Fulford, Jr. , et al. December 28, 1	1999-12-28
Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device Grant 6,005,285 - Gardner , et al. December 21, 1	1999-12-21
Method and apparatus for high performance transistor devices Grant 5,981,363 - Gardner , et al. November 9, 1	1999-11-09
Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths Grant 5,963,803 - Dawson , et al. October 5, 1	1999-10-05
Method of patterning a metal substrate using spin-on glass as a hard mask Grant 5,950,106 - May , et al. September 7, 1	1999-09-07
Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen Grant 5,943,585 - May , et al. August 24, 1	1999-08-24
Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure Grant 5,915,195 - Fulford, Jr. , et al. June 22, 1	1999-06-22
Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties Grant 5,904,539 - Hause , et al. May 18, 1	1999-05-18
Semiconductor device having a vertical active region and method of manufacture thereof Grant 5,846,862 - May , et al. December 8, 1	1998-12-08
Method of cross-linking polyvinyl alcohol and other water soluble resins Grant 4,218,280 - Philipp , et al. August 19, 1	1980-08-19

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