Maszara; Witold P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Maszara; Witold P..The latest application filed is for "finfet semiconductor devices with stressed channel regions".

Company Profile

0.44.28

Maszara; Witold P. - Morgan Hill CA
Maszara; Witold P. - Sunnyvale CA
Maszara; Witold P. - Columbia MD

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods of forming low defect replacement fins for a FinFET semiconductor device and the resulting devices Grant 9,614,058 - Fronheiser , et al. April 4, 2	2017-04-04
Methods of forming different FinFET devices with different threshold voltages and integrated circuit products containing such devices Grant 9,564,367 - Jacob , et al. February 7, 2	2017-02-07
Channel cladding last process flow for forming a channel region on a FinFET device having a reduced size fin in the channel region Grant 9,508,853 - Jacob , et al. November 29, 2	2016-11-29
Finfet Semiconductor Devices With Stressed Channel Regions App 20160293706 - Cai; Xiuyu ; et al.	2016-10-06
Semiconductor device having structure with fractional dimension of the minimum dimension of a lithography system Grant 9,460,924 - Maszara , et al. October 4, 2	2016-10-04
Channel Cladding Last Process Flow For Forming A Channel Region On A Finfet Device Having A Reduced Size Fin In The Channel Region App 20160204261 - Jacob; Ajey Poovannummoottil ; et al.	2016-07-14
Channel Cladding Last Process Flow For Forming A Channel Region On A Finfet Device App 20160163863 - Jacob; Ajey Poovannummoottil ; et al.	2016-06-09
Channel cladding last process flow for forming a channel region on a FinFET device Grant 9,362,405 - Jacob , et al. June 7, 2	2016-06-07
Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device Grant 9,349,840 - Cai , et al. May 24, 2	2016-05-24
Methods Of Forming Metastable Replacement Fins For A Finfet Semiconductor Device By Performing A Replacement Growth Process App 20160064250 - Jacob; Ajey P. ; et al.	2016-03-03
Methods Of Forming Stressed Channel Regions For A Finfet Semiconductor Device And The Resulting Device App 20160035863 - Cai; Xiuyu ; et al.	2016-02-04
Methods of forming replacement fins for a FinFET semiconductor device by performing a replacement growth process Grant 9,240,342 - Jacob , et al. January 19, 2	2016-01-19
Methods Of Forming Low Defect Replacement Fins For A Finfet Semiconductor Device And The Resulting Devices App 20160013296 - Fronheiser; Jody ; et al.	2016-01-14
Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device Grant 9,214,553 - Cai , et al. December 15, 2	2015-12-15
Methods Of Forming Stressed Channel Regions For A Finfet Semiconductor Device And The Resulting Device App 20150255608 - Cai; Xiuyu ; et al.	2015-09-10
Methods Of Forming Stressed Channel Regions For A Finfet Semiconductor Device And The Resulting Device App 20150255542 - Cai; Xiuyu ; et al.	2015-09-10
Methods Of Forming Replacement Fins For A Finfet Semiconductor Device By Performing A Replacement Growth Process App 20150024573 - Jacob; Ajey P. ; et al.	2015-01-22
Methods Of Forming Low Defect Replacement Fins For A Finfet Semiconductor Device And The Resulting Devices App 20140264488 - Fronheiser; Jody ; et al.	2014-09-18
Methods of forming FinFET devices with alternative channel materials Grant 8,673,718 - Maszara , et al. March 18, 2	2014-03-18
Methods Of Forming Different Finfet Devices With Different Threshold Voltages And Integrated Circuit Products Containing Such Devices App 20140070322 - Jacob; Ajey P. ; et al.	2014-03-13
Methods Of Forming Finfet Devices With Alternative Channel Materials App 20140011341 - Maszara; Witold P. ; et al.	2014-01-09
Methods Of Forming Finfet Devices With Alternative Channel Materials App 20130309847 - Maszara; Witold P. ; et al.	2013-11-21
Methods of forming FinFET devices with alternative channel materials Grant 8,580,642 - Maszara , et al. November 12, 2	2013-11-12
Strained fully depleted silicon on insulator semiconductor device Grant 8,502,283 - Xiang , et al. August 6, 2	2013-08-06
Fully silicided gate structure for FinFET devices Grant 8,008,136 - Lin , et al. August 30, 2	2011-08-30
Semiconductor Device Having Structure With Fractional Dimension Of The Minimum Dimension Of A Lithography System App 20080237803 - Maszara; Witold P. ; et al.	2008-10-02
Semiconductor Device Having Structure With Sub-lithography Dimensions App 20080241574 - Maszara; Witold P.	2008-10-02
Strained Fully Depleted Silicon On Insulator Semiconductor Device App 20080054316 - Xiang; Qi ; et al.	2008-03-06
Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor Grant 7,306,997 - Xiang , et al. December 11, 2	2007-12-11
Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect Grant 7,306,998 - Maszara December 11, 2	2007-12-11
Shallow junction semiconductor Grant 7,298,012 - Pelella , et al. November 20, 2	2007-11-20
Formation Of Abrupt Junctions In Devices By Using Silicide Growth Dopant Snowplow Effect App 20060211245 - Maszara; Witold P.	2006-09-21
Shallow Junction Semiconductor App 20060180873 - Pelella; Mario M. ; et al.	2006-08-17
Fully Silicided Gate Structure For Finfet Devices App 20060177998 - Lin; Ming-Ren ; et al.	2006-08-10
Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect Grant 7,081,655 - Maszara July 25, 2	2006-07-25
Formation of finFET using a sidewall epitaxial layer Grant 7,078,299 - Maszara , et al. July 18, 2	2006-07-18
Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor App 20060099752 - Xiang; Qi ; et al.	2006-05-11
Shallow junction semiconductor and method for the fabrication thereof Grant 7,033,916 - Pelella , et al. April 25, 2	2006-04-25
Method of growing as a channel region to reduce source/drain junction capacitance Grant 6,955,969 - Djomehri , et al. October 18, 2	2005-10-18
Semiconductor solid phase epitaxy damage control method and integrated circuit produced thereby Grant 6,933,579 - En , et al. August 23, 2	2005-08-23
Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect App 20050121731 - Maszara, Witold P.	2005-06-09
Semiconductor device with non-compounded contacts, and method of making Grant 6,872,644 - Buynoski , et al. March 29, 2	2005-03-29
Formation Of Finfet Using A Sidewall Epitaxial Layer App 20050048727 - Maszara, Witold P. ; et al.	2005-03-03
Method of growing as a channel region to reduce source/drain junction capicitance App 20050048743 - Djomehri, Ihsan J. ; et al.	2005-03-03
Semiconductor device with a silicon-on-void structure and method of making the same Grant 6,830,987 - Pelella , et al. December 14, 2	2004-12-14
Ultra-thin fully depleted SOI device and method of fabrication Grant 6,815,297 - Krivokapic , et al. November 9, 2	2004-11-09
Wafer pattern variation of integrated circuit fabrication Grant 6,812,550 - En , et al. November 2, 2	2004-11-02
Method of making a hybrid SOI device that suppresses floating body effects Grant 6,727,149 - Krishnan , et al. April 27, 2	2004-04-27
Silicon-on-insulator Device With Strained Device Film And Method For Making The Same With Partial Replacement Of Isolation Oxide App 20040018668 - Maszara, Witold P.	2004-01-29
Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide Grant 6,680,240 - Maszara January 20, 2	2004-01-20
Asymmetric semiconductor device having dual work function gate and method of fabrication Grant 6,630,720 - Maszara , et al. October 7, 2	2003-10-07
Asymmetric Semiconductor Device Having Dual Work Function Gate And Method Of Fabrication App 20030178689 - Maszara, Witold P. ; et al.	2003-09-25
Semiconductor device having multi-work function gate electrode and multi-segment gate dielectric Grant 6,586,808 - Xiang , et al. July 1, 2	2003-07-01
Argon implantation after silicidation for improved floating-body effects Grant 6,495,887 - Krishnan , et al. December 17, 2	2002-12-17
Semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions Grant 6,465,847 - Krishnan , et al. October 15, 2	2002-10-15
SOI semiconductor device opening implantation gettering method Grant 6,444,534 - Maszara September 3, 2	2002-09-03
Method of fabricating semiconductor-on-insulator (SOI) device with hyperabrupt source/drain junctions Grant 6,429,054 - Krishnan , et al. August 6, 2	2002-08-06
Formation of low thermal budget shallow abrupt junctions for semiconductor devices Grant 6,362,063 - Maszara , et al. March 26, 2	2002-03-26
Method of formation of pseudo-SOI structures with direct contact of transistor body to the substrate Grant 6,245,636 - Maszara June 12, 2	2001-06-12
Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects Grant 6,204,138 - Krishnan , et al. March 20, 2	2001-03-20
Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile Grant 6,184,112 - Maszara , et al. February 6, 2	2001-02-06
Fast Mosfet with low-doped source/drain Grant 6,060,364 - Maszara , et al. May 9, 2	2000-05-09
Method for forming thickened source/drain contact regions for field effect transistors Grant 5,250,454 - Maszara October 5, 1	1993-10-05
Method for making a self-aligned lateral bipolar SOI transistor Grant 5,073,506 - Maszara , et al. December 17, 1	1991-12-17

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