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name:-0.013646125793457
name:-0.026082038879395
name:-0.011203050613403
Mai; Quang X. Patent Filings

Mai; Quang X.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Mai; Quang X..The latest application filed is for "method for fabricating low resistance, low inductance interconnections in high current semiconductor devices".

Company Profile
0.10.3
  • Mai; Quang X. - Sugar Land TX
  • Mai; Quang X. - Sugarland TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
Grant RE48,420 - Lange , et al. February 2, 2
2021-02-02
Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
Grant RE46,618 - Lange , et al. November 28, 2
2017-11-28
Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
Grant RE46,466 - Lange , et al. July 4, 2
2017-07-04
Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
Grant 7,335,536 - Lange , et al. February 26, 2
2008-02-26
Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices
App 20070048996 - Lange; Bernhard P. ;   et al.
2007-03-01
Wafer-level assembly method for chip-size devices having flipped chips
App 20050151268 - Boyd, William D. ;   et al.
2005-07-14
Integrated circuit with bonding layer over active circuitry
Grant 6,683,380 - Efland , et al. January 27, 2
2004-01-27
Integrated circuit with bonding layer over active circuitry
App 20030036256 - Efland, Taylor R. ;   et al.
2003-02-20
Plastic encapsulation for integrated circuits having plated copper top surface level interconnect
Grant 6,140,702 - Efland , et al. October 31, 2
2000-10-31
Plastic encapsulation for integrated circuits having plated copper top surface level interconnect
Grant 6,140,150 - Efland , et al. October 31, 2
2000-10-31
Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect
Grant 6,025,275 - Efland , et al. February 15, 2
2000-02-15
Thick plated interconnect and associated auxillary interconnect
Grant 6,020,640 - Efland , et al. February 1, 2
2000-02-01

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