Liang; Mong-Song

Patent Applications and Registrations

Patent applications and USPTO patent grants for Liang; Mong-Song.The latest application filed is for "integrated circuit metal gate structure having tapered profile".

Company Profile

0.166.98

Liang; Mong-Song - Taipei TW
Liang; Mong-Song - Hsin-Chu TW
LIANG; Mong-Song - Taipei City TW
Liang; Mong-Song - Hsinchu TW
LIANG; Mong-Song - Hsinchu City TW
Liang; Mong-Song - Cupertino CA
Liang; Mong-Song - Milpitas CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Strained isolation regions Grant 9,564,488 - Liang , et al. February 7, 2	2017-02-07
Integrated circuit metal gate structure having tapered profile Grant 9,455,344 - Chuang , et al. September 27, 2	2016-09-27
SRAM devices utilizing strained-channel transistors and methods of manufacture Grant 9,059,310 - Chuang , et al. June 16, 2	2015-06-16
Dishing-free gap-filling with multiple CMPs Grant 8,932,951 - Wu , et al. January 13, 2	2015-01-13
Integrated Circuit Metal Gate Structure Having Tapered Profile App 20140246712 - CHUANG; Harry-Hak-Lay ; et al.	2014-09-04
Strained Isolation Regions App 20140242776 - Liang; Mong-Song ; et al.	2014-08-28
Layout methods of integrated circuits having unit MOS devices Grant 8,803,202 - Chuang , et al. August 12, 2	2014-08-12
Process to make high-K transistor dielectrics Grant 8,785,272 - Yao , et al. July 22, 2	2014-07-22
Integrated circuit metal gate structure and method of fabrication Grant 8,735,235 - Chuang , et al. May 27, 2	2014-05-27
Strained isolation regions Grant 8,736,016 - Liang , et al. May 27, 2	2014-05-27
Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors Grant 8,728,900 - Chuang , et al. May 20, 2	2014-05-20
Semiconductor device and method of fabricating same Grant 8,716,103 - Cheng , et al. May 6, 2	2014-05-06
SRAM Devices Utilizing Strained-Channel Transistors and Methods of Manufacture App 20140099758 - Chuang; Harry-Hak-Lay ; et al.	2014-04-10
Integrating a first contact structure in a gate last process Grant 8,669,153 - Yeh , et al. March 11, 2	2014-03-11
Dishing-Free Gap-Filling with Multiple CMPs App 20140030888 - Wu; Ming-Yuan ; et al.	2014-01-30
SRAM devices utilizing strained-channel transistors and methods of manufacture Grant 8,624,295 - Chuang , et al. January 7, 2	2014-01-07
Semiconductor Device and Method of Fabricating Same App 20130316504 - Cheng; Chung Long ; et al.	2013-11-28
Relaxed silicon germanium substrate with low defect density Grant 8,564,018 - Lin , et al. October 22, 2	2013-10-22
Strained transistor with optimized drive current and method of forming Grant 8,558,278 - Chuang , et al. October 15, 2	2013-10-15
Dishing-free gap-filling with multiple CMPs Grant 8,552,522 - Wu , et al. October 8, 2	2013-10-08
Hybrid process for forming metal gates of MOS devices Grant 8,536,660 - Hsu , et al. September 17, 2	2013-09-17
Integrating a First Contact Structure in a Gate Last Process App 20130196496 - Yeh; Chiung-Han ; et al.	2013-08-01
Semiconductor device and method of fabricating same Grant 8,461,629 - Cheng , et al. June 11, 2	2013-06-11
Spacer shape engineering for void-free gap-filling process Grant 8,461,654 - Wu , et al. June 11, 2	2013-06-11
Integrating a first contact structure in a gate last process Grant 8,394,692 - Yeh , et al. March 12, 2	2013-03-12
Integrating the Formation of I/O and Core MOS Devices with MOS Capacitors and Resistors App 20130034946 - Chuang; Harry ; et al.	2013-02-07
Reducing device performance drift caused by large spacings between active regions Grant 8,368,170 - Chuang , et al. February 5, 2	2013-02-05
Integrating a capacitor in a metal gate last process Grant 8,368,136 - Chuang , et al. February 5, 2	2013-02-05
Implanted metal silicide for semiconductor device Grant 8,349,732 - Chuang , et al. January 8, 2	2013-01-08
Layout Methods of Integrated Circuits Having Unit MOS Devices App 20120286368 - Chuang; Harry ; et al.	2012-11-15
Integrating the formation of I/O and core MOS devices with MOS capacitors and resistors Grant 8,294,216 - Chuang , et al. October 23, 2	2012-10-23
3-dimensional device design layout Grant 8,286,114 - Chuang , et al. October 9, 2	2012-10-09
MOS devices with partial stressor channel Grant 8,274,071 - Yu , et al. September 25, 2	2012-09-25
Layout methods of integrated circuits having unit MOS devices Grant 8,237,201 - Chuang , et al. August 7, 2	2012-08-07
Reducing Device Performance Drift Caused by Large Spacings Between Active Regions App 20120132987 - Chuang; Harry ; et al.	2012-05-31
Low K dielectric surface damage control Grant 8,148,270 - Tao , et al. April 3, 2	2012-04-03
Semiconductor device with local interconnects Grant 8,138,554 - Chuang , et al. March 20, 2	2012-03-20
Device layout for gate last process Grant 8,125,051 - Chuang , et al. February 28, 2	2012-02-28
Integrating A First Contact Structure In A Gate Last Process App 20120045889 - Yeh; Chiung-Han ; et al.	2012-02-23
Reducing device performance drift caused by large spacings between active regions Grant 8,115,271 - Chuang , et al. February 14, 2	2012-02-14
Spacer Shape Engineering for Void-Free Gap-Filling Process App 20120025329 - Wu; Ming-Yuah ; et al.	2012-02-02
Integrating a first contact structure in a gate last process Grant 8,093,120 - Yeh , et al. January 10, 2	2012-01-10
Process To Make High-k Transistor Dielectrics App 20110318915 - Yao; Liang-Gi ; et al.	2011-12-29
Spacer shape engineering for void-free gap-filling process Grant 8,048,752 - Wu , et al. November 1, 2	2011-11-01
Semiconductor Device and Method of Fabricating Same App 20110260251 - Cheng; Chung Long ; et al.	2011-10-27
Integrating a first contact structure in a gate last process Grant 8,035,165 - Yeh , et al. October 11, 2	2011-10-11
Method for forming composite barrier layer Grant 8,034,709 - Huang , et al. October 11, 2	2011-10-11
Reducing Device Performance Drift Caused by Large Spacings Between Active Regions App 20110233682 - Chuang; Harry ; et al.	2011-09-29
Dishing-Free Gap-Filling with Multiple CMPs App 20110227189 - Wu; Ming-Yuan ; et al.	2011-09-22
Process to make high-K transistor dielectrics Grant 8,012,824 - Yao , et al. September 6, 2	2011-09-06
Semiconductor device with both I/O and core components and method of fabricating same Grant 7,998,830 - Cheng , et al. August 16, 2	2011-08-16
Reducing device performance drift caused by large spacings between active regions Grant 7,977,202 - Chuang , et al. July 12, 2	2011-07-12
Dishing-free gap-filling with multiple CMPs Grant 7,955,964 - Wu , et al. June 7, 2	2011-06-07
MOS Devices with Partial Stressor Channel App 20110101305 - Yu; Ming-Hua ; et al.	2011-05-05
Semiconductor Device with both I/O and Core Components and Method of Fabricating Same App 20110076813 - Cheng; Chung Long ; et al.	2011-03-31
Contact scheme for MOSFETs Grant 7,898,037 - Chuang , et al. March 1, 2	2011-03-01
Semiconductor device with both I/O and core components and method of fabricating same Grant 7,868,361 - Cheng , et al. January 11, 2	2011-01-11
MOS devices with partial stressor channel Grant 7,868,317 - Yu , et al. January 11, 2	2011-01-11
STI stress modulation with additional implantation and natural pad sin mask Grant 7,851,328 - Liao , et al. December 14, 2	2010-12-14
Integrating A First Contact Structure In A Gate Last Process App 20100285658 - Yeh; Chiung-Han ; et al.	2010-11-11
Integrated circuit having improved interconnect structure Grant 7,772,701 - Yao , et al. August 10, 2	2010-08-10
Low K Dielectric Surface Damage Control App 20100173499 - Tao; Hun-Jan ; et al.	2010-07-08
Fuse Structure For Intergrated Circuit Devices App 20100117190 - CHUANG; Harry ; et al.	2010-05-13
Gate dielectric layers and methods of fabricating gate dielectric layers Grant 7,713,854 - Chen , et al. May 11, 2	2010-05-11
Low K dielectric surface damage control Grant 7,709,392 - Tao , et al. May 4, 2	2010-05-04
Sti Stress Modulation With Additional Implantation And Natural Pad Sin Mask App 20100075480 - Liao; Ming-Han ; et al.	2010-03-25
Semiconductor Device With Local Interconnects App 20100065921 - CHUANG; Harry ; et al.	2010-03-18
Selective formation of stress memorization layer Grant 7,678,636 - Chuang , et al. March 16, 2	2010-03-16
Integrating A First Contact Structure In A Gate Last Process App 20100052075 - Yeh; Chiung-Han ; et al.	2010-03-04
Integrated Circuit Metal Gate Structure And Method Of Fabrication App 20100044783 - Chuang; Harry ; et al.	2010-02-25
Integrating the Formation of I/O and Core MOS Devices with MOS Capacitors and Resistors App 20100038692 - Chuang; Harry ; et al.	2010-02-18
Spacer Shape Engineering for Void-Free Gap-Filling Process App 20100022061 - Wu; Ming-Yuan ; et al.	2010-01-28
Structure and a Method of Manufacture for Low Resistance NiSix App 20100013029 - Chuang; Harry ; et al.	2010-01-21
Integrating A Capacitor In A Metal Gate Last Process App 20100001332 - Chuang; Harry ; et al.	2010-01-07
Device Layout For Gate Last Process App 20100001369 - Chuang; Harry ; et al.	2010-01-07
Method for semiconductor device performance enhancement Grant 7,632,729 - Chuang , et al. December 15, 2	2009-12-15
Dishing-free gap-filling with multiple CMPs App 20090286384 - Wu; Ming-Yuan ; et al.	2009-11-19
Reducing Device Performance Drift Caused by Large Spacings Between Action Regions App 20090273052 - Chuang; Harry ; et al.	2009-11-05
SRAM Devices Utilizing Strained-Channel Transistors and Methods of Manufacture App 20090236633 - Chuang; Harry ; et al.	2009-09-24
Hybrid Process for Forming Metal Gates of MOS Devices App 20090230479 - Hsu; Peng-Fu ; et al.	2009-09-17
MOS Devices with Partial Stressor Channel App 20090224337 - Yu; Ming-Hua ; et al.	2009-09-10
MOS devices with partial stressor channel Grant 7,554,110 - Yu , et al. June 30, 2	2009-06-30
Super anneal for process induced strain modulation Grant 7,528,028 - Liang , et al. May 5, 2	2009-05-05
Method for fabricating dual-gate semiconductor device Grant 7,510,940 - Yeh , et al. March 31, 2	2009-03-31
Method for forming composite barrier layer App 20090047780 - Huang; Cheng-Lin ; et al.	2009-02-19
Semiconductor Device with both I/O and Core Components and Method of Fabricating Same App 20080315320 - Cheng; Chung Long ; et al.	2008-12-25
Strained Isolation Regions App 20080303102 - Liang; Mong-Song ; et al.	2008-12-11
Layout methods of integrated circuits having unit MOS devices App 20080296691 - Chuang; Harry ; et al.	2008-12-04
Composite barrier layer Grant 7,453,149 - Huang , et al. November 18, 2	2008-11-18
Adhesion of copper and etch stop layer for copper alloy Grant 7,443,029 - Lin , et al. October 28, 2	2008-10-28
3-Dimensional Device Design Layout App 20080263492 - Chuang; Harry ; et al.	2008-10-23
Contact Scheme for MOSFETs App 20080258228 - Chuang; Harry ; et al.	2008-10-23
Methods For Forming Transistors With High-k Dielectric Layers And Transistors Formed Therefrom App 20080254588 - Chuang; Harry ; et al.	2008-10-16
Method for fabricating semiconductor device App 20080242108 - Chang; Weng ; et al.	2008-10-02
Method for fabricating dual-gate semiconductor device App 20080197420 - Yeh; Chen-Nan ; et al.	2008-08-21
Method of making FUSI gate and resulting structure Grant 7,410,854 - Yao , et al. August 12, 2	2008-08-12
Backside contacts for MOS devices Grant 7,402,866 - Liang , et al. July 22, 2	2008-07-22
Strained Transistor with Optimized Drive Current and Method of Forming App 20080169484 - Chuang; Harry ; et al.	2008-07-17
Relaxed Silicon Germanium Substrate With Low Defect Density App 20080142842 - LIN; Chun Chich ; et al.	2008-06-19
Novel Method To Adjust Work Function By Plasma Assisted Metal Incorporated Dielectric App 20080146012 - Lin; Wenli ; et al.	2008-06-19
Etch stop layer Grant 7,375,040 - Lin , et al. May 20, 2	2008-05-20
Polysilicon levels for silicided structures including MOSFET gate electrodes and 3D devices App 20080093682 - Yao; Liang-Gi ; et al.	2008-04-24
Gate Dielectric Layers And Methods Of Fabricating Gate Dielectric Layers App 20080096394 - Chen; Chi-Chun ; et al.	2008-04-24
Relaxed silicon germanium substrate with low defect density Grant 7,357,838 - Lin , et al. April 15, 2	2008-04-15
Method of making FUSI gate and resulting structure App 20080085590 - Yao; Liang-Gi ; et al.	2008-04-10
Noble high-k device Grant 7,351,994 - Yao , et al. April 1, 2	2008-04-01
Method for semiconductor device performance enhancement App 20080076215 - Chuang; Harry ; et al.	2008-03-27
MOS devices with partial stressor channel App 20080067557 - Yu; Ming-Hua ; et al.	2008-03-20
Selective formation of stress memorization layer App 20080003734 - Chuang; Harry ; et al.	2008-01-03
Backside contacts for MOS devices App 20070296002 - Liang; Mong Song ; et al.	2007-12-27
Integrated Circuit Having Improved Interconnect Structure App 20070284747 - Yao; Chih-Hsiang ; et al.	2007-12-13
Copper interconnects Grant 7,253,524 - Wu , et al. August 7, 2	2007-08-07
Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology Grant 7,247,915 - Chang , et al. July 24, 2	2007-07-24
Semiconductor device and fabrication method thereof App 20070152306 - Shih; Chien-Hsueh ; et al.	2007-07-05
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement Grant 7,238,989 - Yeo , et al. July 3, 2	2007-07-03
Barrier-less integration with copper alloy Grant 7,215,024 - Lin , et al. May 8, 2	2007-05-08
Atomic layer deposition tantalum nitride layer to improve adhesion between a copper structure and overlying materials Grant 7,202,162 - Lin , et al. April 10, 2	2007-04-10
Method for producing low defect density strained -Si channel MOSFETS Grant 7,202,142 - Lee , et al. April 10, 2	2007-04-10
Low K Dielectric Surface Damage Control App 20070026668 - Tao; Hun-Jan ; et al.	2007-02-01
Semiconductor devices and methods of manufacture thereof App 20070013070 - Liang; Mong Song ; et al.	2007-01-18
Method of forming a MOS device having a strained channel region App 20070010073 - Chen; Chien-Hao ; et al.	2007-01-11
Super anneal for process induced strain modulation App 20060286758 - Liang; Mong Song ; et al.	2006-12-21
Multiple etch-stop layer deposition scheme and materials Grant 7,151,052 - Huang , et al. December 19, 2	2006-12-19
Laser spike annealing for gate dielectric materials App 20060270166 - Yao; Liang-Gi ; et al.	2006-11-30
Integrated dual damascene clean apparatus and process App 20060246727 - Hsieh; Ching-Hua ; et al.	2006-11-02
Multiple Etch-stop Layer Deposition Scheme And Materials App 20060246686 - Huang; Tai-Chun ; et al.	2006-11-02
Process to make high-K transistor dielectrics App 20060246698 - Yao; Liang-Gi ; et al.	2006-11-02
Silicon oxycarbide and silicon carbonitride based materials for MOS devices Grant 7,115,974 - Wu , et al. October 3, 2	2006-10-03
Strained silicon layer fabrication with reduced dislocation defect density Grant 7,105,393 - Yao , et al. September 12, 2	2006-09-12
Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology App 20060157800 - Chang; Chih-Wei ; et al.	2006-07-20
Geometrically optimized spacer to improve device performance App 20060148157 - Tao; Hun-Jan ; et al.	2006-07-06
Integrated treatment method for obtaining robust low dielectric constant materials Grant 7,071,093 - Liang , et al. July 4, 2	2006-07-04
Methods for enhancing die saw and packaging reliability App 20060055002 - Yao; Chih-Hsiang ; et al.	2006-03-16
Method for improving the electrical continuity for a silicon-germanium film across a silicon/oxide/polysilicon surface using a novel two-temperature process Grant 7,012,009 - Lee , et al. March 14, 2	2006-03-14
Composite barrier layer App 20060027925 - Huang; Cheng-Lin ; et al.	2006-02-09
Self-passivated copper interconnect structure Grant 6,995,471 - Shue , et al. February 7, 2	2006-02-07
Method for producing high throughput strained-Si channel MOSFETS Grant 6,982,208 - Lee , et al. January 3, 2	2006-01-03
Adhesion of copper and etch stop layer for copper alloy App 20050277298 - Lin, Jing Cheng ; et al.	2005-12-15
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement App 20050272188 - Yeo, Yee-Chia ; et al.	2005-12-08
Barrier free copper interconnect by multi-layer copper seed App 20050263902 - Lin, Jing-Cheng ; et al.	2005-12-01
Adhesion of copper and etch stop layer for copper alloy Grant 6,967,155 - Lin , et al. November 22, 2	2005-11-22
Method for producing low defect density strained -Si channel MOSFETS App 20050245035 - Lee, Kuen-Chyr ; et al.	2005-11-03
Method For Producing High Throughput Strained-si Channel Mosfets App 20050245058 - Lee, Kuen-Chyr ; et al.	2005-11-03
Silicon oxycarbide and silicon carbonitride based materials for MOS devices App 20050236694 - Wu, Zhen-Cheng ; et al.	2005-10-27
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement Grant 6,955,952 - Yeo , et al. October 18, 2	2005-10-18
Integrated treatment method for obtaining robust low dielectric constant materials App 20050215052 - Liang, Mong-Song ; et al.	2005-09-29
Barrier free copper interconnect by multi-layer copper seed Grant 6,943,111 - Lin , et al. September 13, 2	2005-09-13
Deposition method for Si-Ge epi layer on different intermediate substrates Grant 6,936,530 - Yao , et al. August 30, 2	2005-08-30
Method for improving the electrical continuity for a silicon-germanium film across a silicon/oxide/polysilicon surface using a novel two-temperature process App 20050186750 - Lee, Kuen-Chyr ; et al.	2005-08-25
Novel Deposition Method For Si-ge Epi Layer On Different Intermediate Substrates App 20050176229 - Yao, Liang-Gi ; et al.	2005-08-11
Strained silicon layer fabrication with reduced dislocation defect density App 20050170577 - Yao, Liang-Gi ; et al.	2005-08-04
Noble high-k device App 20050156255 - Yao, Liang-Gi ; et al.	2005-07-21
Relaxed silicon germanium substrate with low defect density App 20050158971 - Lin, Chun Chich ; et al.	2005-07-21
Discontinuity prevention for SiGe deposition Grant 6,911,369 - Lee , et al. June 28, 2	2005-06-28
Copper interconnects App 20050110153 - Wu, Zhen-Cheng ; et al.	2005-05-26
Low K dielectric surface damage control App 20050095869 - Tao, Hun-Jan ; et al.	2005-05-05
Relaxed silicon germanium substrate with low defect density Grant 6,878,610 - Lin , et al. April 12, 2	2005-04-12
Embedded fastener apparatus and method for preventing particle contamination App 20050050708 - Huang, Yu-Lien ; et al.	2005-03-10
Barrier-less integration with copper alloy App 20050029665 - Lin, Jing-Cheng ; et al.	2005-02-10
Adhesion of copper and etch stop layer for copper alloy App 20050006776 - Lin, Jing Cheng ; et al.	2005-01-13
Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology App 20040262649 - Chang, Chih-Wei ; et al.	2004-12-30
Hybrid copper/low k dielectric interconnect integration method and device App 20040251549 - Huang, Tai-Chun ; et al.	2004-12-16
Atomic layer deposited tantalum nitride layer to improve adhesion between a copper structure and overlying materials App 20040214425 - Lin, Jing-Cheng ; et al.	2004-10-28
Method of barrier-less integration with copper alloy Grant 6,806,192 - Lin , et al. October 19, 2	2004-10-19
Method for integrating an electrodeposition and electro-mechanical polishing process Grant 6,793,797 - Chou , et al. September 21, 2	2004-09-21
Method for forming a self-passivated copper interconnect structure App 20040180532 - Shue, Shau-Lin ; et al.	2004-09-16
Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement App 20040175872 - Yeo, Yee-Chia ; et al.	2004-09-09
Barrier free copper interconnect by multi-layer copper seed App 20040157431 - Lin, Jing-Cheng ; et al.	2004-08-12
Discontinuity prevention for SiGe deposition App 20040157399 - Lee, Kuen-Chyr ; et al.	2004-08-12
Method of barrier-less integration with copper alloy App 20040147104 - Lin, Jing-Cheng ; et al.	2004-07-29
Method of forming a silicon nitride-silicon dioxide gate stack Grant 6,767,847 - Hu , et al. July 27, 2	2004-07-27
Method of improving the bondability between Au wires and Cu bonding pads Grant 6,753,259 - Jang , et al. June 22, 2	2004-06-22
Method for manufacturing a silicon germanium based device with crystal defect prevention App 20040115878 - Lee, Kuen-Chyr ; et al.	2004-06-17
Laminating method for forming integrated circuit microelectronic fabrication Grant 6,740,567 - Liang , et al. May 25, 2	2004-05-25
Method for forming a self-passivated copper interconnect structure Grant 6,716,753 - Shue , et al. April 6, 2	2004-04-06
Barrier-free copper interconnect Grant 6,706,629 - Lin , et al. March 16, 2	2004-03-16
Copper back-end-of-line by electropolish Grant 6,649,513 - Tsai , et al. November 18, 2	2003-11-18
Scanning type etcher design for precision process control App 20030209321 - Tao, Hun-Jan ; et al.	2003-11-13
Method for integrating an electrodeposition and electro-mechanical polishing process App 20030183530 - Chou, Shih-Wei ; et al.	2003-10-02
Process technology architecture of embedded DRAM Grant 6,600,186 - Lee , et al. July 29, 2	2003-07-29
Selectively controllable gas feed zones for a plasma reactor Grant 6,590,344 - Tao , et al. July 8, 2	2003-07-08
Selectively Controllable Gas Feed Zones For A Plasma Reactor App 20030094903 - Tao, Jhun-jan ; et al.	2003-05-22
Vertical stacked gate flash memory device Grant 6,548,856 - Lin , et al. April 15, 2	2003-04-15
Laminating method for forming integrated circuit microelectronic fabrication App 20020197775 - Liang, Mong-Song ; et al.	2002-12-26
Methods to create high-k dielectric gate electrodes with backside cleaning Grant 6,455,330 - Yao , et al. September 24, 2	2002-09-24
Method of protecting a copper pad structure during a fuse opening procedure Grant 6,440,833 - Lee , et al. August 27, 2	2002-08-27
Method of improving the bondability between Au wires and Cu bonding pads Grant 6,423,625 - Jang , et al. July 23, 2	2002-07-23
Method of improving the bondability between Au wires and Cu bonding pads App 20020086533 - Jang, Syun-Ming ; et al.	2002-07-04
Fabrication of MIM capacitor in copper damascene process Grant 6,387,775 - Jang , et al. May 14, 2	2002-05-14
Pseudo silicon on insulator MOSFET device Grant 6,346,729 - Liang , et al. February 12, 2	2002-02-12
OTP (open trigger path) latchup scheme using triple and buried well for sub-quarter micron transistors Grant 6,258,641 - Wong , et al. July 10, 2	2001-07-10
3D reservoir to improve electromigration resistance of tungsten plug Grant 6,245,675 - Liang , et al. June 12, 2	2001-06-12
Isolation dielectric deposition in multi-polysilicon chemical-mechanical polishing process Grant 6,218,286 - Su , et al. April 17, 2	2001-04-17
Method for forming a ultra-thin gate insulator layer Grant 6,184,155 - Yu , et al. February 6, 2	2001-02-06
Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors Grant 6,174,754 - Lee , et al. January 16, 2	2001-01-16
Dynamic threshold MOSFET using accumulated base BJT level shifter for low voltage sub-quarter micron transistor Grant 6,124,618 - Wong , et al. September 26, 2	2000-09-26
Method for forming a polysilicon-interconnect contact in a TFT-SRAM Grant 6,110,822 - Huang , et al. August 29, 2	2000-08-29
Method of manufacture of vertical stacked gate flash memory device Grant 6,093,606 - Lin , et al. July 25, 2	2000-07-25
Method to improve the adhesion of a molding compound to a semiconductor chip comprised with copper damascene structures Grant 6,090,696 - Jang , et al. July 18, 2	2000-07-18
Large angle channel threshold implant for improving reverse narrow width effect Grant 6,083,795 - Liang , et al. July 4, 2	2000-07-04
Pseudo silicon on insulator MOSFET device Grant 6,071,783 - Liang , et al. June 6, 2	2000-06-06
OTP (open trigger path) latchup scheme using buried-diode for sub-quarter micron transistors Grant 6,054,344 - Liang , et al. April 25, 2	2000-04-25
Drain and source engineering for ESD-protection transistors Grant 6,051,458 - Liang , et al. April 18, 2	2000-04-18
Method for manufacturing a TFT SRAM memory device with improved performance Grant 5,953,606 - Huang , et al. September 14, 1	1999-09-14
Method of manufacture of memory device with high coupling ratio Grant 5,923,974 - Liang , et al. July 13, 1	1999-07-13
Method for making low-topography buried capacitor by a two stage etching process and device made Grant 5,885,865 - Liang , et al. March 23, 1	1999-03-23
Multi-level split- gate flash memory cell Grant 5,877,523 - Liang , et al. March 2, 1	1999-03-02
Method of making a semiconductor device having 4t sram and mixed-mode capacitor in logic Grant 5,866,451 - Yoo , et al. February 2, 1	1999-02-02
Method of making dual isolation regions for logic and embedded memory devices Grant 5,858,830 - Yoo , et al. January 12, 1	1999-01-12
Method of making monos flash memory for multi-level logic Grant 5,851,881 - Lin , et al. December 22, 1	1998-12-22
Method of making buried contact in DRAM technology Grant 5,846,860 - Shih , et al. December 8, 1	1998-12-08
Process for integrating stacked capacitor DRAM devices with MOSFET devices used for high performance logic circuits Grant 5,843,817 - Lee , et al. December 1, 1	1998-12-01
Body contact for a MOSFET device fabricated in an SOI layer Grant 5,818,085 - Hsu , et al. October 6, 1	1998-10-06
Non-volatile-memory cell for electrically programmable read only memory having a trench-like coupling capacitors Grant 5,801,415 - Lee , et al. September 1, 1	1998-09-01
High-performance and reliable thin film transistor (TFT) using plasma hydrogenation with a metal shield on the TFT channel Grant 5,796,150 - Wuu , et al. August 18, 1	1998-08-18
Process for fabricating MOS memory devices, with a self-aligned contact structure, and MOS logic devices with salicide, both on a single semiconductor chip Grant 5,792,684 - Lee , et al. August 11, 1	1998-08-11
Method for fabricating a DRAM cell with a Y shaped storage capacitor Grant 5,759,888 - Wang , et al. June 2, 1	1998-06-02
Process to fabricate stacked capacitor DRAM and low power thin film transistor SRAM devices on a single semiconductor chip Grant 5,716,881 - Liang , et al. February 10, 1	1998-02-10
Multi-level, split-gate, flash memory cell and method of manufacture thereof Grant 5,714,412 - Liang , et al. February 3, 1	1998-02-03
Fabrication method for integrating logic and single level polysilicon DRAM devices on the same semiconductor chip Grant 5,712,201 - Lee , et al. January 27, 1	1998-01-27
Gate spacer to control the base width of a lateral bipolar junction transistor using SOI technology Grant 5,705,839 - Hsu , et al. January 6, 1	1998-01-06
Blending integrated circuit technology Grant 5,702,988 - Liang December 30, 1	1997-12-30
Method for fabricating a tub structured stacked capacitor for a DRAM cell having a central column Grant 5,702,989 - Wang , et al. December 30, 1	1997-12-30
Elevated source/drain with solid phase diffused source/drain extension for deep sub-micron MOSFETS Grant 5,693,974 - Hsu , et al. December 2, 1	1997-12-02
Method of making high-performance and reliable thin film transistor (TFT) using plasma hydrogenation with a metal shield on the TFT channel Grant 5,686,335 - Wuu , et al. November 11, 1	1997-11-11
Method of making raised-bitline contactless trenched flash memory cell Grant 5,679,591 - Lin , et al. October 21, 1	1997-10-21
Method of forming an ultra thin dielectric film for a capacitor Grant 5,670,431 - Huanga , et al. September 23, 1	1997-09-23
Method for fabricating a dual-gate dielectric module for memory with embedded logic technology Grant 5,668,035 - Fang , et al. September 16, 1	1997-09-16
One step smooth cylinder surface formation process in stacked cylindrical DRAM products Grant 5,668,038 - Huang , et al. September 16, 1	1997-09-16
Self-aligned tin formation by N.sub.2.sup.+ implantation during two-step annealing Ti-salicidation Grant 5,656,546 - Chen , et al. August 12, 1	1997-08-12
Method for fabricating CMOS field effect transistors having sub-quarter micrometer channel lengths with improved short channel effect characteristics Grant 5,646,435 - Hsu , et al. July 8, 1	1997-07-08
Sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains Grant 5,623,153 - Liang , et al. April 22, 1	1997-04-22
Method for fabricating an accumulated-base bipolar junction transistor Grant 5,614,424 - Wong , et al. March 25, 1	1997-03-25
Anti-punchthrough ion implantation for sub-half micron channel length MOSFET devices Grant 5,614,430 - Liang , et al. March 25, 1	1997-03-25
Method for fabricating a DRAM cell with a T shaped storage capacitor Grant 5,607,874 - Wang , et al. March 4, 1	1997-03-04
Method for forming buried plug contacts on semiconductor integrated circuits Grant 5,607,879 - Wuu , et al. March 4, 1	1997-03-04
Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells Grant 5,605,853 - Yoo , et al. February 25, 1	1997-02-25
Method of making ESD protection circuit with three stages Grant 5,593,911 - Lee , et al. January 14, 1	1997-01-14
Method of making a body contacted SOI MOSFET Grant 5,591,650 - Hsu , et al. January 7, 1	1997-01-07
High resistance polysilicon resistor for integrated circuits and method of fabrication thereof Grant 5,587,696 - Su , et al. December 24, 1	1996-12-24
Method of making a body contact for a MOSFET device fabricated in an SOI layer Grant 5,573,961 - Hsu , et al. November 12, 1	1996-11-12
Process for forming stacked contacts and metal contacts on static random access memory having thin film transistors Grant 5,547,892 - Wuu , et al. August 20, 1	1996-08-20
Method of fabricating a sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains Grant 5,545,579 - Liang , et al. August 13, 1	1996-08-13
Elevated source/drain with solid phase diffused source/drain extension for deep sub-micron mosfets Grant 5,504,031 - Hsu , et al. April 2, 1	1996-04-02
Process of making a polysilicon barrier layer in a self-aligned contact module Grant 5,480,814 - Wuu , et al. January 2, 1	1996-01-02
Method of making buried contact module with multiple poly si layers Grant 5,393,687 - Liang February 28, 1	1995-02-28
Multiple tilted angle ion implantation MOSFET method Grant 5,372,957 - Liang , et al. December 13, 1	1994-12-13
Integrated circuit structure having gate electrode and underlying oxide and method of making same Grant 4,789,883 - Cox , et al. December 6, 1	1988-12-06
Method of improving silicon dioxide Grant 4,774,197 - Haddad , et al. September 27, 1	1988-09-27
Memory cell having hot-hole injection erase mode Grant 4,742,491 - Liang , et al. May 3, 1	1988-05-03