| Patent | Date |
|---|
Techniques For Firmware Updates With Accessories
App 20220229653 - Le; Hung Q. ; et al. | 2022-07-21 |
Instruction streaming using state migration
Grant 11,301,254 - Battle , et al. April 12, 2 | 2022-04-12 |
Techniques for firmware updates with accessories
Grant 11,275,576 - Le , et al. March 15, 2 | 2022-03-15 |
Dynamic update of the number of architected registers assigned to software threads using spill counts
Grant 11,275,614 - Cain, III , et al. March 15, 2 | 2022-03-15 |
Thread transition management
Grant 11,256,507 - Abernathy , et al. February 22, 2 | 2022-02-22 |
Instruction Handling For Accumulation Of Register Results In A Microprocessor
App 20220050682 - Thompto; Brian W. ; et al. | 2022-02-17 |
Techniques For Firmware Updates With Accessories
App 20210397432 - Le; Hung Q. ; et al. | 2021-12-23 |
Techniques For Firmware Updates With Accessories
App 20210397436 - Le; Hung Q. ; et al. | 2021-12-23 |
Techniques For Firmware Updates With Accessories
App 20210397435 - Le; Hung Q. ; et al. | 2021-12-23 |
Multiple streams execution for hard-to-predict branches in a microprocessor
Grant 11,188,340 - Thompto , et al. November 30, 2 | 2021-11-30 |
Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entry
Grant 11,157,276 - Battle , et al. October 26, 2 | 2021-10-26 |
Independent mapping of threads
Grant 11,144,323 - Chu , et al. October 12, 2 | 2021-10-12 |
Instruction handling for accumulation of register results in a microprocessor
Grant 11,132,198 - Thompto , et al. September 28, 2 | 2021-09-28 |
Extended prefix including routing bit for extended instruction format
Grant 11,119,777 - Frazier , et al. September 14, 2 | 2021-09-14 |
Check pointing of accumulator register results in a microprocessor
Grant 11,119,772 - Battle , et al. September 14, 2 | 2021-09-14 |
Slice-target register file for microprocessor
Grant 11,119,774 - Thompto , et al. September 14, 2 | 2021-09-14 |
Decoupling of conditional branches
Grant 11,106,466 - Orzol , et al. August 31, 2 | 2021-08-31 |
Banked slice-target register file for wide dataflow execution in a microprocessor
Grant 11,093,246 - Boersma , et al. August 17, 2 | 2021-08-17 |
Register file write using pointers
Grant 11,093,282 - Barrick , et al. August 17, 2 | 2021-08-17 |
Instruction streaming using copy select vector
Grant 11,061,681 - Battle , et al. July 13, 2 | 2021-07-13 |
Check Pointing Of Accumulator Register Results In A Microprocessor
App 20210173649 - Battle; Steven J ; et al. | 2021-06-10 |
Saving and restoring a transaction memory state
Grant 10,996,995 - Battle , et al. May 4, 2 | 2021-05-04 |
Program instruction scheduling
Grant 10,983,797 - Zoellin , et al. April 20, 2 | 2021-04-20 |
Slice-target Register File For Microprocessor
App 20210072992 - Thompto; Brian W. ; et al. | 2021-03-11 |
Banked Slice-target Register File For Wide Dataflow Execution In A Microprocessor
App 20210072991 - Boersma; Maarten J. ; et al. | 2021-03-11 |
Thread-based Organization Of Slice Target Register File Entry In A Microprocessor
App 20210072993 - Battle; Steven J. ; et al. | 2021-03-11 |
Instruction Handling For Accumulation Of Register Results In A Microprocessor
App 20210064365 - Thompto; Brian W. ; et al. | 2021-03-04 |
Speculatively releasing store data before store instruction completion in a processor
Grant 10,929,144 - Ward , et al. February 23, 2 | 2021-02-23 |
Instruction Streaming Using State Migration
App 20210026642 - Battle; Steven J. ; et al. | 2021-01-28 |
Instruction Streaming Using Copy Select Vector
App 20210026643 - Battle; Steven J. ; et al. | 2021-01-28 |
Handling unaligned load operations in a multi-slice computer processor
Grant 10,884,742 - Chadha , et al. January 5, 2 | 2021-01-05 |
Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor
Grant 10,877,763 - Lloyd , et al. December 29, 2 | 2020-12-29 |
Program Instruction Scheduling
App 20200379766 - Zoellin; Christian ; et al. | 2020-12-03 |
Managing an issue queue for fused instructions and paired instructions in a microprocessor
Grant 10,831,498 - Genden , et al. November 10, 2 | 2020-11-10 |
Handling unaligned load operations in a multi-slice computer processor
Grant 10,831,481 - Chadha , et al. November 10, 2 | 2020-11-10 |
Dynamic update of the number of architected registers assigned to software threads using spill counts
Grant 10,831,537 - Cain, III , et al. November 10, 2 | 2020-11-10 |
Managing an issue queue for fused instructions and paired instructions in a microprocessor
Grant 10,831,501 - Genden , et al. November 10, 2 | 2020-11-10 |
Register File Write Using Pointers
App 20200326978 - Barrick; Brian D. ; et al. | 2020-10-15 |
Saving And Restoring A Transaction Memory State
App 20200301758 - BATTLE; Steven J. ; et al. | 2020-09-24 |
Network Access Tokens For Accessories
App 20200267552 - Lee; Wayne A. ; et al. | 2020-08-20 |
Dual compare of least-significant-bit for dependency wake up from a fused instruction tag in a microprocessor
Grant 10,747,545 - Genden , et al. A | 2020-08-18 |
Speculatively Releasing Stores in a Processor
App 20200249946 - Kind Code | 2020-08-06 |
Multiple Streams Execution For Branch Predication In A Microprocessor
App 20200201646 - THOMPTO; Brian W. ; et al. | 2020-06-25 |
Converting multiple instructions into a single combined instruction with an extension opcode
Grant 10,691,459 - Frazier , et al. | 2020-06-23 |
Converting multiple instructions into a single combined instruction with an extension opcode
Grant 10,684,856 - Frazier , et al. | 2020-06-16 |
Dual Compare Of Least-significant-bit For Dependency Wake Up From A Fused Instruction Tag In A Microprocessor
App 20200167166 - Genden; Michael J. ; et al. | 2020-05-28 |
Speeding up younger store instruction execution after a sync instruction
Grant 10,664,275 - Eisen , et al. | 2020-05-26 |
Shared compare lanes for dependency wake up in a pair-based issue queue
Grant 10,635,444 - Genden , et al. | 2020-04-28 |
Independent Mapping Of Threads
App 20200073668 - Chu; Sam G. ; et al. | 2020-03-05 |
Operation of a multi-slice processor with an expanded merge fetching queue
Grant 10,564,978 - Fernsler , et al. Feb | 2020-02-18 |
Low Power Back-to-back Wake Up And Issue For Paired Issue Queue In A Microprocessor
App 20200042321 - Genden; Michael J. ; et al. | 2020-02-06 |
Dispatching, Allocating, and Deallocating Instructions in a Queue in a Processor
App 20200042319 - Lloyd; Bryan ; et al. | 2020-02-06 |
Multi-level history buffer for transaction memory in a microprocessor
Grant 10,545,765 - Barrick , et al. Ja | 2020-01-28 |
Independent mapping of threads
Grant 10,545,762 - Chu , et al. Ja | 2020-01-28 |
Dynamic Update Of The Number Of Architected Registers Assigned To Software Threads Using Spill Counts
App 20200026559 - CAIN, III; HAROLD W. ; et al. | 2020-01-23 |
Multiple Level History Buffer for Transaction Memory Support
App 20200019405 - Battle; Steven J. ; et al. | 2020-01-16 |
Shared Compare Lanes For Dependency Wake Up In A Pair-based Issue Queue
App 20200004546 - GENDEN; MICHAEL J. ; et al. | 2020-01-02 |
Handling Unaligned Load Operations In A Multi-slice Computer Processor
App 20190384602 - CHADHA; SUNDEEP ; et al. | 2019-12-19 |
Decoupling Of Conditional Branches
App 20190384607 - Orzol; Nicholas R. ; et al. | 2019-12-19 |
Handling unaligned load operations in a multi-slice computer processor
Grant 10,496,406 - Chadha , et al. De | 2019-12-03 |
Handling Unaligned Load Operations In A Multi-slice Computer Processor
App 20190286446 - CHADHA; SUNDEEP ; et al. | 2019-09-19 |
Handling unaligned load operations in a multi-slice computer processor
Grant 10,409,598 - Chadha , et al. Sept | 2019-09-10 |
Managing An Issue Queue For Fused Instructions And Paired Instructions In A Microprocessor
App 20190265979 - GENDEN; MICHAEL J. ; et al. | 2019-08-29 |
Managing An Issue Queue For Fused Instructions And Paired Instructions In A Microprocessor
App 20190265978 - GENDEN; MICHAEL J. ; et al. | 2019-08-29 |
Managing an issue queue for fused instructions and paired instructions in a microprocessor
Grant 10,394,565 - Genden , et al. A | 2019-08-27 |
Managing an issue queue for fused instructions and paired instructions in a microprocessor
Grant 10,387,147 - Genden , et al. A | 2019-08-20 |
Thread Transition Management
App 20190250918 - Abernathy; Christopher M. ; et al. | 2019-08-15 |
Thread transition management
Grant 10,296,339 - Abernathy , et al. | 2019-05-21 |
Method and apparatus for execution of threads on processing slices using a history buffer for recording architected register data
Grant 10,289,415 - Eisen , et al. | 2019-05-14 |
Method and apparatus for execution of threads on processing slices using a history buffer for restoring architected register data via issued instructions
Grant 10,282,205 - Eisen , et al. | 2019-05-07 |
Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
Grant 10,268,518 - Chadha , et al. | 2019-04-23 |
Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
Grant 10,255,107 - Chadha , et al. | 2019-04-09 |
Split-level history buffer in a computer processing unit
Grant 10,241,800 - Le , et al. | 2019-03-26 |
Extended store forwarding for store misses without cache allocate
Grant 10,223,266 - Cordes , et al. | 2019-03-05 |
Managing An Issue Queue For Fused Instructions And Paired Instructions In A Microprocessor
App 20190042239 - GENDEN; MICHAEL J. ; et al. | 2019-02-07 |
Managing An Issue Queue For Fused Instructions And Paired Instructions In A Microprocessor
App 20190042238 - GENDEN; MICHAEL J. ; et al. | 2019-02-07 |
Converting Program Instructions For Two-stage Processors
App 20190018677 - FRAZIER; GILES R. ; et al. | 2019-01-17 |
Converting Program Instructions For Two-stage Processors
App 20190018679 - FRAZIER; GILES R. ; et al. | 2019-01-17 |
Speeding Up Younger Store Instruction Execution After a Sync Instruction
App 20190012175 - Eisen; Susan E. ; et al. | 2019-01-10 |
Thread Transition Management
App 20180349141 - Abernathy; Christopher M. ; et al. | 2018-12-06 |
Multi-level History Buffer For Transaction Memory In A Microprocessor
App 20180336037 - BARRICK; Brian D. ; et al. | 2018-11-22 |
Handling Unaligned Load Operations In A Multi-slice Computer Processor
App 20180300135 - CHADHA; SUNDEEP ; et al. | 2018-10-18 |
Handling Unaligned Load Operations In A Multi-slice Computer Processor
App 20180300136 - CHADHA; SUNDEEP ; et al. | 2018-10-18 |
Operation Of A Multi-slice Processor With An Expanded Merge Fetching Queue
App 20180293077 - FERNSLER; KIMBERLY M. ; et al. | 2018-10-11 |
Operation Of A Multi-slice Processor Implementing A Load/store Unit Maintaining Rejected Instructions
App 20180285161 - CHADHA; SUNDEEP ; et al. | 2018-10-04 |
Operation Of A Multi-slice Processor Implementing A Load/store Unit Maintaining Rejected Instructions
App 20180276132 - CHADHA; SUNDEEP ; et al. | 2018-09-27 |
Processing instructions in parallel with waw hazards and via a distributed history buffer in a microprocessor having a multi-execution slice architecture
Grant 10,073,699 - Eisen , et al. September 11, 2 | 2018-09-11 |
Handling unaligned load operations in a multi-slice computer processor
Grant 10,073,697 - Chadha , et al. September 11, 2 | 2018-09-11 |
Handling unaligned load operations in a multi-slice computer processor
Grant 10,067,763 - Chadha , et al. September 4, 2 | 2018-09-04 |
Speeding up younger store instruction execution after a sync instruction
Grant 10,067,765 - Eisen , et al. September 4, 2 | 2018-09-04 |
Dynamic Physical Register Allocation Across Multiple Threads
App 20180239604 - CAIN, III; HAROLD W. ; et al. | 2018-08-23 |
Thread transition management
Grant 10,055,226 - Abernathy , et al. August 21, 2 | 2018-08-21 |
Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
Grant 10,042,770 - Chadha , et al. August 7, 2 | 2018-08-07 |
Operation of a multi-slice processor with an expanded merge fetching queue
Grant 10,037,211 - Fernsler , et al. July 31, 2 | 2018-07-31 |
Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
Grant 10,037,229 - Chadha , et al. July 31, 2 | 2018-07-31 |
Universal history buffer to support multiple register types
Grant 9,996,353 - Genden , et al. June 12, 2 | 2018-06-12 |
Extended Store Forwarding For Store Misses Without Cache Allocate
App 20180150395 - CORDES; ROBERT A. ; et al. | 2018-05-31 |
Split-level history buffer in a computer processing unit
Grant 9,940,139 - Le , et al. April 10, 2 | 2018-04-10 |
Independent Mapping Of Threads
App 20180067746 - Chu; Sam G. ; et al. | 2018-03-08 |
Independent mapping of threads
Grant 9,870,229 - Chu , et al. January 16, 2 | 2018-01-16 |
Initializing a memory subsystem of a management controller
Grant 9,870,233 - Heinrich , et al. January 16, 2 | 2018-01-16 |
Administering Instruction Tags In A Computer Processor
App 20180004516 - FEISTE; KURT A. ; et al. | 2018-01-04 |
Split-level history buffer in a computer processing unit
Grant 9,851,979 - Le , et al. December 26, 2 | 2017-12-26 |
Operation Of A Multi-slice Processor Implementing A Load/store Unit Maintaining Rejected Instructions
App 20170329641 - CHADHA; SUNDEEP ; et al. | 2017-11-16 |
Operation Of A Multi-slice Processor Implementing A Load/store Unit Maintaining Rejected Instructions
App 20170329713 - CHADHA; SUNDEEP ; et al. | 2017-11-16 |
Transactional storage accesses supporting differing priority levels
Grant 9,798,577 - Guthrie , et al. October 24, 2 | 2017-10-24 |
Thread Transition Management
App 20170300331 - Abernathy; Christopher M. ; et al. | 2017-10-19 |
Transactional storage accesses supporting differing priority levels
Grant 9,792,147 - Guthrie , et al. October 17, 2 | 2017-10-17 |
Techniques For Restoring Previous Values To Registers Of A Processor Register File
App 20170277535 - LE; HUNG Q. ; et al. | 2017-09-28 |
Operation Of A Multi-slice Processor With An Expanded Merge Fetching Queue
App 20170277542 - FERNSLER; KIMBERLY M. ; et al. | 2017-09-28 |
Independent mapping of threads
Grant 9,720,696 - Chu , et al. August 1, 2 | 2017-08-01 |
Thread transition management
Grant 9,703,561 - Abernathy , et al. July 11, 2 | 2017-07-11 |
Handling Unaligned Load Operations In A Multi-slice Computer Processor
App 20170168823 - CHADHA; SUNDEEP ; et al. | 2017-06-15 |
Handling Unaligned Load Operations In A Multi-slice Computer Processor
App 20170168945 - CHADHA; SUNDEEP ; et al. | 2017-06-15 |
Method And Apparatus For Restoring Data To A Register File Of A Processing Unit
App 20170109167 - EISEN; Susan E. ; et al. | 2017-04-20 |
Method And Apparatus For Processing Instructions In A Microprocessor Having A Multi-execution Slice Architecture
App 20170109171 - EISEN; Susan E. ; et al. | 2017-04-20 |
Method And Apparatus For Recovery In A Microprocessor Having A Multi-execution Slice Architecture
App 20170109166 - EISEN; Susan E. ; et al. | 2017-04-20 |
Transactional memory system supporting unbroken suspended execution
Grant 9,626,187 - Cain, III , et al. April 18, 2 | 2017-04-18 |
Determining failure context in hardware transactional memories
Grant 9,626,256 - Cain , et al. April 18, 2 | 2017-04-18 |
Transactional Storage Accesses Supporting Differing Priority Levels
App 20170004004 - GUTHRIE; GUY L. ; et al. | 2017-01-05 |
Transactional Storage Accesses Supporting Differing Priority Levels
App 20170004085 - GUTHRIE; GUY L. ; et al. | 2017-01-05 |
Split-level History Buffer In A Computer Processing Unit
App 20160378500 - Le; Hung Q. ; et al. | 2016-12-29 |
Split-level History Buffer In A Computer Processing Unit
App 20160378501 - Le; Hung Q. ; et al. | 2016-12-29 |
Split-level History Buffer In A Computer Processing Unit
App 20160371088 - Le; Hung Q. ; et al. | 2016-12-22 |
Split-level History Buffer In A Computer Processing Unit
App 20160371087 - Le; Hung Q. ; et al. | 2016-12-22 |
Split-level history buffer in a computer processing unit
Grant 9,524,171 - Le , et al. December 20, 2 | 2016-12-20 |
Techniques for increasing vector processing utilization and efficiency through vector lane predication prediction
Grant 9,519,479 - Le , et al. December 13, 2 | 2016-12-13 |
Universal History Buffer to Support Multiple Register Types
App 20160253177 - Genden; Michael J. ; et al. | 2016-09-01 |
Independent Mapping Of Threads
App 20160092276 - Chu; Sam G. ; et al. | 2016-03-31 |
Independent Mapping Of Threads
App 20160092231 - Chu; Sam G. ; et al. | 2016-03-31 |
Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories
Grant 9,268,598 - Blainey , et al. February 23, 2 | 2016-02-23 |
Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories
Grant 9,268,599 - Blainey , et al. February 23, 2 | 2016-02-23 |
Storing data in any of a plurality of buffers in a memory controller
Grant 9,213,545 - Le , et al. December 15, 2 | 2015-12-15 |
Detection of conflicts between transactions and page shootdowns
Grant 9,086,986 - Cain, III , et al. July 21, 2 | 2015-07-21 |
Detection of conflicts between transactions and page shootdowns
Grant 9,086,987 - Cain, III , et al. July 21, 2 | 2015-07-21 |
Conditional transaction abort and precise abort handling
Grant 9,081,607 - Blainey , et al. July 14, 2 | 2015-07-14 |
Techniques for Increasing Vector Processing Utilization and Efficiency Through Vector Lane Predication Prediction
App 20150143083 - Le; Hung Q. ; et al. | 2015-05-21 |
Hardware assist thread for increasing code parallelism
Grant 9,037,837 - Hall , et al. May 19, 2 | 2015-05-19 |
Instruction tracking system for processors
Grant 8,874,880 - Abernathy , et al. October 28, 2 | 2014-10-28 |
Thread Transition Management
App 20140258691 - Abernathy; Christopher M. ; et al. | 2014-09-11 |
Memory subsystem having a first portion to store data with error correction code information and a second portion to store data without error correction code information
Grant 8,738,995 - Emerson , et al. May 27, 2 | 2014-05-27 |
Thread transition management
Grant 8,725,993 - Abernathy , et al. May 13, 2 | 2014-05-13 |
Detection Of Conflicts Between Transactions And Page Shootdowns
App 20140115297 - Cain, III; Harold W. ; et al. | 2014-04-24 |
Method And Apparatus For Conditional Transaction Abort And Precise Abort Handling
App 20140115590 - Blainey; Robert J ; et al. | 2014-04-24 |
Seamless interface for multi-threaded core accelerators
Grant 8,683,175 - Ekanadham , et al. March 25, 2 | 2014-03-25 |
Method And Apparatus For Recording And Profiling Transaction Failure Source Addresses In Hardware Transactional Memories
App 20140081936 - Blainey; Robert J. ; et al. | 2014-03-20 |
Method And Apparatus For Determining Failure Context In Hardware Transactional Memories
App 20140075131 - Cain; Harold W. ; et al. | 2014-03-13 |
Detection Of Conflicts Between Transactions And Page Shootdowns
App 20140075151 - Cain, III; Harold W. ; et al. | 2014-03-13 |
Method And Apparatus For Recording And Profiling Transaction Failure Source Addresses In Hardware Transactional Memories
App 20140075441 - Blainey; Robert J. ; et al. | 2014-03-13 |
Method And Apparatus For Determining Failure Context In Hardware Transactional Memories
App 20140075132 - Cain; Harold W. ; et al. | 2014-03-13 |
Multi-level register file supporting multiple threads
Grant 8,661,227 - Abernathy , et al. February 25, 2 | 2014-02-25 |
Multi-level register file supporting multiple threads
Grant 8,661,228 - Abernathy , et al. February 25, 2 | 2014-02-25 |
Register file supporting transactional processing
Grant 8,631,223 - Abernathy , et al. January 14, 2 | 2014-01-14 |
Instruction Tracking System For Processors
App 20130346731 - Abernathy; Christopher M. ; et al. | 2013-12-26 |
Speeding Up Younger Store Instruction Execution after a Sync Instruction
App 20130305022 - Eisen; Susan E. ; et al. | 2013-11-14 |
Hardware assist thread for increasing code parallelism
Grant 8,423,750 - Hall , et al. April 16, 2 | 2013-04-16 |
Initializing A Memory Subsystem Of A Management Controller
App 20130067189 - Heinrich; David F. ; et al. | 2013-03-14 |
Storing Data In Any Of A Plurality Of Buffers In A Memory Controller
App 20130046933 - Le; Hung Q. ; et al. | 2013-02-21 |
Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions
App 20130013899 - Barton; Christopher M. ; et al. | 2013-01-10 |
Hardware Assisted Scheduling In Computer System
App 20120284720 - Cain, III; Harold W. ; et al. | 2012-11-08 |
Hardware Assist Thread for Increasing Code Parallelism
App 20120254594 - Hall; Ronald P. ; et al. | 2012-10-04 |
Seamless Interface For Multi-threaded Core Accelerators
App 20120239904 - Ekanadham; Kattamuri ; et al. | 2012-09-20 |
Thread Transition Management
App 20120216004 - Abernathy; Christopher M. ; et al. | 2012-08-23 |
Multi-level Register File Supporting Multiple Threads
App 20120204009 - ABERNATHY; CHRISTOPHER M. ; et al. | 2012-08-09 |
Memory Subsystem Having A First Portion To Store Data With Error Correction Code Information And A Second Portion To Store Data Without Error Correction Code Information
App 20120124448 - Emerson; Ted ; et al. | 2012-05-17 |
Enhanced load lookahead prefetch in single threaded mode for a simultaneous multithreaded microprocessor
Grant 8,145,887 - Le , et al. March 27, 2 | 2012-03-27 |
Multi-level Register File Supporting Multiple Threads
App 20120072700 - ABERNATHY; CHRISTOPHER M. ; et al. | 2012-03-22 |
Electronic curtain for vehicle protection
Grant 8,098,191 - Pergande , et al. January 17, 2 | 2012-01-17 |
Instruction Tracking System For Processors
App 20110302392 - Abernathy; Christopher M. ; et al. | 2011-12-08 |
Transactional Memory System Supporting Unbroken Suspended Execution
App 20110296148 - Cain, III; Harold W. ; et al. | 2011-12-01 |
Register File Supporting Transactional Processing
App 20110283096 - ABERNATHY; CHRISTOPHER M. ; et al. | 2011-11-17 |
Hardware Assist Thread for Increasing Code Parallelism
App 20110283095 - Hall; Ronald P. ; et al. | 2011-11-17 |
Enhanced single threaded execution in a simultaneous multithreaded microprocessor
Grant 7,827,389 - Le , et al. November 2, 2 | 2010-11-02 |
Universal register rename mechanism for instructions with multiple targets in a microprocessor
Grant 7,809,929 - Le , et al. October 5, 2 | 2010-10-05 |
System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor
Grant 7,779,234 - Bishop , et al. August 17, 2 | 2010-08-17 |
System and method for implementing a software-supported thread assist mechanism for a microprocessor
Grant 7,779,233 - Le , et al. August 17, 2 | 2010-08-17 |
Universal register rename mechanism for targets of different instruction types in a microprocessor
Grant 7,765,384 - Le , et al. July 27, 2 | 2010-07-27 |
System and Method for Implementing a Hardware-Supported Thread Assist Under Load Lookahead Mechanism for a Microprocessor
App 20090106538 - Bishop; James W. ; et al. | 2009-04-23 |
System and Method for Implementing a Software-Supported Thread Assist Mechanism for a Microprocessor
App 20090106534 - Le; Hung Q. ; et al. | 2009-04-23 |
System for managing data dependency using bit field instruction destination vector identifying destination for execution results
Grant 7,475,226 - Le , et al. January 6, 2 | 2009-01-06 |
Dynamically shared group completion table between multiple threads
Grant 7,472,258 - Burky , et al. December 30, 2 | 2008-12-30 |
Enhanced Single Threaded Execution in a Simultaneous Multithreaded Microprocessor
App 20080313422 - Le; Hung Q. ; et al. | 2008-12-18 |
Enhanced Load Lookahead Prefetch in Single Threaded Mode for a Simultaneous Multithreaded Microprocessor
App 20080313425 - Le; Hung Q. ; et al. | 2008-12-18 |
Universal Register Rename Mechanism for Targets of Different Instruction Types in a Microprocessor
App 20080263321 - Le; Hung Q. ; et al. | 2008-10-23 |
Universal Register Rename Mechanism for Instructions with Multiple Targets in a Microprocessor
App 20080263331 - Le; Hung Q. ; et al. | 2008-10-23 |
Adaptive Fetch Gating In Multithreaded Processors, Fetch Control And Method Of Controlling Fetches
App 20080229068 - BOSE; PRADIP ; et al. | 2008-09-18 |
Dynamic recalculation of resource vector at issue queue for steering of dependent instructions
Grant 7,395,414 - Le , et al. July 1, 2 | 2008-07-01 |
Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches
Grant 7,392,366 - Bose , et al. June 24, 2 | 2008-06-24 |
Dynamic Recalculation Of Resource Vector At Issue Queue For Steering Of Dependent Instructions
App 20080133890 - Le; Hung Q. ; et al. | 2008-06-05 |
Adaptive Fetch Gating In Multithreaded Processors, Fetch Control And Method Of Controlling Fetches
App 20080133886 - BOSE; PRADIP ; et al. | 2008-06-05 |
Data Processing System, Processor And Method Of Data Processing Employing An Improved Instruction Destination Tag
App 20080072018 - Le; Hung Q. ; et al. | 2008-03-20 |
Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table
Grant 7,278,011 - Eisen , et al. October 2, 2 | 2007-10-02 |
SMT flush arbitration
Grant 7,194,603 - Burky , et al. March 20, 2 | 2007-03-20 |
Method of implementing precise, localized hardware-error workarounds under centralized control
App 20060184770 - Bishop; James W. ; et al. | 2006-08-17 |
Dynamic recalculation of resource vector at issue queue for steering of dependent instructions
App 20060184767 - Le; Hung Q. ; et al. | 2006-08-17 |
Method and apparatus for dynamic modification of microprocessor instruction group at dispatch
App 20060184768 - Bishop; James W. ; et al. | 2006-08-17 |
Localized generation of global flush requests while guaranteeing forward progress of a processor
App 20060184769 - Floyd; Michael S. ; et al. | 2006-08-17 |
Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches
App 20060101238 - Bose; Pradip ; et al. | 2006-05-11 |
Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to access a free entry
Grant 6,988,186 - Eickemeyer , et al. January 17, 2 | 2006-01-17 |
Completion table configured to track a larger number of outstanding instructions
App 20050228972 - Eisen, Susan E. ; et al. | 2005-10-13 |
Dynamically adaptive buffer mechanism
Grant 6,938,143 - Le August 30, 2 | 2005-08-30 |
Dynamically share interrupt handling logic among multiple threads
App 20040215937 - Burky, William E. ; et al. | 2004-10-28 |
SMT flush arbitration
App 20040215938 - Burky, William E. ; et al. | 2004-10-28 |
Dynamically shared group completion table between multiple threads
App 20040210743 - Burky, William E. ; et al. | 2004-10-21 |
Dynamically adaptive buffer mechanism
App 20040052135 - Le, Hung Q. | 2004-03-18 |
Dynamically adaptive buffer mechanism
Grant 6,678,813 - Le January 13, 2 | 2004-01-13 |
Mechanism to assign more logical load/store tags than available physical registers in a microprocessor system
App 20030182537 - Le, Hung Q. ; et al. | 2003-09-25 |
Apparatus and method for providing access security to a device coupled upon a two-wire bidirectional bus
Grant 6,510,522 - Heinrich , et al. January 21, 2 | 2003-01-21 |
Shared resource queue for simultaneous multithreaded processing
App 20030005263 - Eickemeyer, Richard James ; et al. | 2003-01-02 |
Apparatus And Method For Maintaining Secured Access To Relocated Plug And Play Peripheral Devices
App 20020194486 - HEINRICH, DAVID F. ; et al. | 2002-12-19 |
Apparatus and method for programmably and flexibly assigning passwords to unlock devices of a computer system intended to remain secure
Grant 6,460,139 - Heinrich , et al. October 1, 2 | 2002-10-01 |
Computer access via a single-use password
Grant 6,370,649 - Angelo , et al. April 9, 2 | 2002-04-09 |
Circuit and method employing feedback for driving a clocking signal to compensate for load-induced skew
Grant 6,182,236 - Culley , et al. January 30, 2 | 2001-01-30 |
Flash ROM sharing between processor and microcontroller during booting and handling warm-booting events
Grant 6,154,838 - Le , et al. November 28, 2 | 2000-11-28 |
Serial bus system for shadowing registers
Grant 6,108,729 - Maguire , et al. August 22, 2 | 2000-08-22 |
Flash ROM sharing between processor and microcontroller during booting and handling warm-booting events
Grant 5,819,087 - Le , et al. October 6, 1 | 1998-10-06 |
Computer system and method for replacing obsolete or corrupt boot code contained within reprogrammable memory with new boot code supplied from an external source through a data port
Grant 5,805,882 - Cooper , et al. September 8, 1 | 1998-09-08 |
Flash ROM sharing between a processor and a controller
Grant 5,794,054 - Le , et al. August 11, 1 | 1998-08-11 |
Serial bus system for shadowing registers
Grant 5,748,911 - Maguire , et al. May 5, 1 | 1998-05-05 |
Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system
Grant 5,465,336 - Imai , et al. November 7, 1 | 1995-11-07 |
Buffering digitizer data in a first-in first-out memory
Grant 5,455,907 - Hess , et al. October 3, 1 | 1995-10-03 |
Battery charger
Grant 5,304,916 - Le , et al. April 19, 1 | 1994-04-19 |
Multiple frequency phase-locked loop clock generator with stable transitions between frequencies
Grant 5,142,247 - Lada, Jr. , et al. August 25, 1 | 1992-08-25 |
| 