King; Tsu-Jae

Patent Applications and Registrations

Patent applications and USPTO patent grants for King; Tsu-Jae.The latest application filed is for "damascene process for use in fabricating semiconductor structures having micro/nano gaps".

Company Profile

0.71.55

King; Tsu-Jae - Fremont CA US
King, Tsu-Jae - US
King, Tsu-Jae - Fremount CA
King; Tsu-Jae - Cupertino CA
King; Tsu-Jae - Santa Clara County CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit on corrugated substrate Grant 8,786,057 - King , et al. July 22, 2	2014-07-22
Damascene process for use in fabricating semiconductor structures having micro/nano gaps Grant 8,329,559 - Takeuchi , et al. December 11, 2	2012-12-11
Damascene Process For Use In Fabricating Semiconductor Structures Having Micro/nano Gaps App 20120171798 - Takeuchi; Hideki ; et al.	2012-07-05
Metal-insulator-metal (MIM) switching devices Grant 8,044,442 - Kam , et al. October 25, 2	2011-10-25
Methods of designing an integrated circuit on corrugated substrate Grant 7,960,232 - King , et al. June 14, 2	2011-06-14
Nano-electro-mechanical memory cells and devices Grant 7,839,710 - Kam , et al. November 23, 2	2010-11-23
Complementary field-effect transistors having enhanced performance with a single capping layer Grant 7,649,230 - Shin , et al. January 19, 2	2010-01-19
Two bit/four bit SONOS flash memory cell Grant 7,629,640 - She , et al. December 8, 2	2009-12-08
Integrated Circuit On Corrugated Substrate App 20090181477 - King; Tsu-Jae ; et al.	2009-07-16
Process for controlling performance characteristics of a negative differential resistance (NDR) device Grant 7,557,009 - King July 7, 2	2009-07-07
Metal-insulator-metal (mim) Switching Devices App 20090128221 - Kam; Hei ; et al.	2009-05-21
Nano-electro-mechanical Memory Cells And Devices App 20090129139 - Kam; Hei ; et al.	2009-05-21
Low-voltage memory having flexible gate charging element App 20090121273 - King; Tsu-Jae ; et al.	2009-05-14
Integrated circuit on corrugated substrate Grant 7,528,465 - King , et al. May 5, 2	2009-05-05
Integrated Circuit On Corrugated Substrate App 20080290470 - King; Tsu-Jae ; et al.	2008-11-27
Negative differential resistance field effect transistor for implementing a pull up element in a memory cell Grant 7,453,083 - King November 18, 2	2008-11-18
Process For Controlling Performance Characteristics Of A Negative Differential Resistance (NDR) Device App 20080020524 - King; Tsu-Jae	2008-01-24
Method of IC production using corrugated substrate Grant 7,265,008 - King , et al. September 4, 2	2007-09-04
Compact static memory cell with non-volatile storage capability Grant 7,266,010 - King September 4, 2	2007-09-04
Damascene process for use in fabricating semiconductor structures having micro/nano gaps Grant 7,256,107 - Takeuchi , et al. August 14, 2	2007-08-14
Finfet-based Sram With Feedback App 20070183185 - Guo; Zheng ; et al.	2007-08-09
Method of making adaptive negative differential resistance device Grant 7,254,050 - King August 7, 2	2007-08-07
Segmented channel MOS transistor Grant 7,247,887 - King , et al. July 24, 2	2007-07-24
Multi-bit-per-cell Nvm Structures And Architecture App 20070164352 - Padilla; Alvaro ; et al.	2007-07-19
Integrated Circuit On Corrugated Substrate App 20070132053 - King; Tsu-Jae ; et al.	2007-06-14
Compact static memory cell with non-volatile storage capability App 20070121371 - King; Tsu-Jae	2007-05-31
Process for controlling performance characteristics of a negative differential resistance (NDR) device Grant 7,220,636 - King May 22, 2	2007-05-22
Integrated circuit on corrugated substrate Grant 7,190,050 - King , et al. March 13, 2	2007-03-13
Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET Grant 7,186,619 - King March 6, 2	2007-03-06
Method of forming a negative differential resistance device Grant 7,186,621 - King March 6, 2	2007-03-06
Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects Grant 7,187,028 - King March 6, 2	2007-03-06
Method of IC production using corrugated substrate App 20070004113 - King; Tsu-Jae ; et al.	2007-01-04
Integrated circuit on corrugated substrate App 20070001232 - King; Tsu-Jae ; et al.	2007-01-04
Segmented channel MOS transistor App 20070001237 - King; Tsu-Jae ; et al.	2007-01-04
Complementary field-effect transistors having enhanced performance with a single capping layer App 20060284255 - Shin; Kyoungsub ; et al.	2006-12-21
Dual work function CMOS gate technology based on metal interdiffusion Grant 7,141,858 - Polishchuk , et al. November 28, 2	2006-11-28
Method of forming a negative differential resistance device Grant 7,113,423 - King September 26, 2	2006-09-26
CMOS compatible process for making a charge trapping device Grant 7,109,078 - King , et al. September 19, 2	2006-09-19
Charge Trapping Device App 20060197122 - King; Tsu-Jae ; et al.	2006-09-07
Negative differential resistance (NDR) elements and memory device using the same Grant 7,098,472 - King August 29, 2	2006-08-29
Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device Grant 7,095,659 - King August 22, 2	2006-08-22
Ion beam extractor with counterbore Grant 7,084,407 - Ji , et al. August 1, 2	2006-08-01
Charge trapping device Grant 7,067,873 - King , et al. June 27, 2	2006-06-27
Methods of testing/stressing a charge trapping device Grant 7,060,524 - King June 13, 2	2006-06-13
Charge trapping device and method of forming the same Grant 7,015,536 - King March 21, 2	2006-03-21
Two terminal silicon based negative differential resistance device Grant 7,016,224 - King March 21, 2	2006-03-21
Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs) Grant 7,012,833 - King March 14, 2	2006-03-14
Enhanced read and write methods for negative differential resistance (NDR) based memory device Grant 7,012,842 - King March 14, 2	2006-03-14
N-channel pull-up element and logic circuit Grant 7,005,711 - King February 28, 2	2006-02-28
Variable voltage supply bias and methods for negative differential resistance (NDR) based memory device App 20060028881 - King; Tsu-Jae	2006-02-09
Method of making memory cell utilizing negative differential resistance devices Grant 6,990,016 - King January 24, 2	2006-01-24
Negative differential resistance (NDR) elements and memory device using the same App 20060007773 - King; Tsu-Jae	2006-01-12
Method of forming a negative differential resistance device Grant 6,980,467 - King December 27, 2	2005-12-27
Process for controlling performance characteristics of a negative differential resistance (NDR) device Grant 6,979,580 - King December 27, 2	2005-12-27
Negative differential resistance pull up element for DRAM App 20050269628 - King, Tsu-Jae	2005-12-08
CMOS process compatible, tunable negative differential resistance (NDR) device and method of operating same Grant 6,972,465 - King , et al. December 6, 2	2005-12-06
Variable threshold semiconductor device and method of operating same Grant 6,969,894 - King , et al. November 29, 2	2005-11-29
Method of forming a negative differential resistance device App 20050260798 - King, Tsu-Jae	2005-11-24
Method of forming a negative differential resistance device App 20050253133 - King, Tsu-Jae	2005-11-17
Damascene process for use in fabricating semiconductor structures having micro/nano gaps App 20050250236 - Takeuchi, Hideki ; et al.	2005-11-10
Two bit/four bit SONOS flash memory cell App 20050242391 - She, Min ; et al.	2005-11-03
Negative differential resistance load element Grant 6,933,548 - King August 23, 2	2005-08-23
Flash memory devices using large electron affinity material for charge trapping App 20050167734 - She, Min ; et al.	2005-08-04
Charge trapping device and method of forming the same App 20050156158 - King, Tsu-Jae	2005-07-21
Process for controlling performance characteristics of a negative differential resistance (NDR) device App 20050153461 - King, Tsu-Jae	2005-07-14
Negative differential resistance (NDR) memory device with reduced soft error rate App 20050145955 - King, Tsu-Jae	2005-07-07
Negative differential resistance (NDR) based memory device with reduced body effects Grant 6,912,151 - King June 28, 2	2005-06-28
Enhanced read and write methods for negative differential resistance (NDR) based memory device App 20050128797 - King, Tsu-Jae	2005-06-16
Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects App 20050121664 - King, Tsu-Jae	2005-06-09
Methods of testing/stressing a charge trapping device App 20050106765 - King, Tsu-Jae	2005-05-19
Method of making adaptive negative differential resistance device App 20050064645 - King, Tsu-Jae	2005-03-24
Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects Grant 6,864,104 - King March 8, 2	2005-03-08
Negative differential resistance (NDR) memory cell with reduced soft error rate Grant 6,861,707 - King March 1, 2	2005-03-01
Multiple-thickness gate oxide formed by oxygen implantation Grant 6,855,994 - King , et al. February 15, 2	2005-02-15
Negative differential resistance (NDR) memory device with reduced soft error rate Grant 6,853,035 - King February 8, 2	2005-02-08
Charge trapping device and method of forming the same Grant 6,849,483 - King February 1, 2	2005-02-01
Enhanced read and write methods for negative differential resistance (NDR) based memory device Grant 6,847,562 - King January 25, 2	2005-01-25
Two terminal silicon based negative differential resistance device App 20040246778 - King, Tsu-Jae	2004-12-09
Method of making memory cell utilizing negative differential resistance devices App 20040246764 - King, Tsu-Jae	2004-12-09
Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) fet App 20040238855 - King, Tsu-Jae	2004-12-02
Dual work function CMOS gate technology based on metal interdiffusion App 20040238859 - Polishchuk, Igor ; et al.	2004-12-02
Adaptive negative differential resistance device Grant 6,812,084 - King November 2, 2	2004-11-02
Methods of testing/stressing a charge trapping device Grant 6,806,117 - King October 19, 2	2004-10-19
Dual work function CMOS gate technology based on metal interdiffusion Grant 6,794,234 - Polishchuk , et al. September 21, 2	2004-09-21
Negative differential resistance (NDR) elements and memory device using the same Grant 6,795,337 - King September 21, 2	2004-09-21
CMOS process compatible, tunable negative differential resistance (NDR) device and method of operating same App 20040150011 - King, Tsu-Jae ; et al.	2004-08-05
Charge trapping device App 20040145010 - King, Tsu-Jae ; et al.	2004-07-29
Variable threshold semiconductor device and method of operating same App 20040145023 - King, Tsu-Jae ; et al.	2004-07-29
CMOS compatible process for making a charge trapping device App 20040142533 - King, Tsu-Jae ; et al.	2004-07-22
N-channel pull-up element & logic circuit App 20040119114 - King, Tsu-Jae	2004-06-24
Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET Grant 6,754,104 - King June 22, 2	2004-06-22
Multiple-thickness gate oxide formed by oxygen implantation Grant 6,753,229 - King , et al. June 22, 2	2004-06-22
Process for controlling performance characteristics of a negative differential resistance (NDR) device App 20040110338 - King, Tsu-Jae	2004-06-10
Charge trapping device & method of forming the same App 20040110336 - King, Tsu-Jae	2004-06-10
Methods of testing/stressing a charge trapping device App 20040110349 - King, Tsu-Jae	2004-06-10
Method of forming a negative differential resistance device App 20040110324 - King, Tsu-Jae	2004-06-10
Adaptive negative differential resistance device App 20040110337 - King, Tsu-Jae	2004-06-10
Integrated circuit having negative differential resistance (NDR) devices with varied peak-to-valley ratios (PVRs) App 20040110332 - King, Tsu-Jae	2004-06-10
Negative differential resistance (NDR) element and memory with reduced soft error rate Grant 6,727,548 - King April 27, 2	2004-04-27
Memory cell using negative differential resistance field effect transistors Grant 6,724,655 - King April 20, 2	2004-04-20
Charge trapping device and method for implementing a transistor having a configurable threshold Grant 6,700,155 - King , et al. March 2, 2	2004-03-02
Negative differential resistance (NDR) based memory device with reduced body effects App 20040032770 - King, Tsu-Jae	2004-02-19
Method for configuring a device to include a negative differential resistance (NDR) characteristic Grant 6,693,027 - King , et al. February 17, 2	2004-02-17
Method for fabricating a dual mode FET and logic circuit having negative differential resistance mode Grant 6,686,267 - King February 3, 2	2004-02-03
Negative differential resistance (NDR) device and method of operating same Grant 6,686,631 - King , et al. February 3, 2	2004-02-03
Method for making both a negative differential resistance (NDR) device and a non-NDR device using a common MOS process Grant 6,680,245 - King , et al. January 20, 2	2004-01-20
Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects App 20040008535 - King, Tsu-Jae	2004-01-15
Enhanced Read & Write Methods For Negative Differential Resistance (ndr)based Memory Device App 20040001363 - King, Tsu-Jae	2004-01-01
Negative differential resistance (NDR) elements & memory device using the same App 20040001354 - King, Tsu-Jae	2004-01-01
Method of orperating a dual mode FET & logic circuit having negative differential resistance mode Grant 6,664,601 - King December 16, 2	2003-12-16
Dual work function CMOS gate technology based on metal interdiffusion App 20030180994 - Polishchuk, Igor ; et al.	2003-09-25
Ion beam extractor with counterbore App 20030168608 - Ji, Qing ; et al.	2003-09-11
CMOS compatible process for making a tunable negative differential resistance (NDR) device Grant 6,596,617 - King , et al. July 22, 2	2003-07-22
CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same Grant 6,512,274 - King , et al. January 28, 2	2003-01-28
Charge trapping device and method for implementing a transistor having a negative differential resistance mode Grant 6,479,862 - King , et al. November 12, 2	2002-11-12
Polycrystalline silicon-germanium films for micro-electromechanical systems application Grant 6,448,622 - Franke , et al. September 10, 2	2002-09-10
Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture Grant 6,413,802 - Hu , et al. July 2, 2	2002-07-02
Dual mode fet & logic circuit having negative differential resistance mode App 20020057123 - King, Tsu-Jae	2002-05-16
Memory cell using negative differential resistance field effect transistors App 20020054502 - King, Tsu-JAe	2002-05-09
Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET App 20020048190 - King, Tsu-Jae	2002-04-25
Polycrystalline silicon germanium films for forming micro-electromechanical systems Grant 6,210,988 - Howe , et al. April 3, 2	2001-04-03
Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates Grant 5,893,949 - King , et al. April 13, 1	1999-04-13
Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates Grant 5,707,744 - King , et al. January 13, 1	1998-01-13
Reducing leakage current in a thin-film transistor with charge carrier densities that vary in two dimensions Grant 5,401,982 - King , et al. March 28, 1	1995-03-28
Low temperature germanium-silicon on insulator thin-film transistor Grant 5,250,818 - Saraswat , et al. October 5, 1	1993-10-05