Kang; Inkuk

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kang; Inkuk.The latest application filed is for "method of forming high-voltage transistor with thin gate poly".

Company Profile

6.24.16

Kang; Inkuk - San Jose CA
Kang; Inkuk - Sunnyvale CA
KANG; Inkuk - San Jos CA
Kang; Inkuk - Saratoga CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of Forming High-Voltage Transistor with Thin Gate Poly App 20210296343 - Chen; Chun ; et al.	2021-09-23
Embedded Non-volatile Memory Device And Fabrication Method Of The Same App 20210134811 - Chen; Chun ; et al.	2021-05-06
Embedded non-volatile memory device and fabrication method of the same Grant 10,872,898 - Chen , et al. December 22, 2	2020-12-22
Split-gate flash cell formed on recessed substrate Grant 10,497,710 - Kang , et al. De	2019-12-03
Method of Forming High-Voltage Transistor with Thin Gate Poly App 20190304990 - Chen; Chun ; et al.	2019-10-03
Method of forming high-voltage transistor with thin gate poly Grant 10,242,996 - Chen , et al.	2019-03-26
Method of Forming High-Voltage Transistor with Thin Gate Poly App 20190027487 - Chen; Chun ; et al.	2019-01-24
Embedded Non-volatile Memory Device And Fabrication Method Of The Same App 20190027484 - Chen; Chun ; et al.	2019-01-24
Split-Gate Flash Cell formed on Recessed Substrate App 20180166458 - Kang; Sung-Taeg ; et al.	2018-06-14
Split-gate flash cell formed on recessed substrate Grant 9,853,039 - Kang , et al. December 26, 2	2017-12-26
Method to Improve Charge Trap Flash Memory Top Oxide Quality App 20150255480 - CHEN; Tung-Sheng ; et al.	2015-09-10
Methods for fabricating memory cells having fin structures with semicircular top surfaces and rounded top corners and edges Grant 8,987,092 - Kang , et al. March 24, 2	2015-03-24
Sonos memory cells having non-uniform tunnel oxide and methods for fabricating same Grant 8,742,496 - Fang , et al. June 3, 2	2014-06-03
Method and device employing polysilicon scaling Grant 8,637,918 - Fang , et al. January 28, 2	2014-01-28
Self-aligned Si Rich Nitride Charge Trap Layer Isolation For Charge Trap Flash Memory App 20140001537 - FANG; Shenqing ; et al.	2014-01-02
Sonos Memory Cells Having Non-uniform Tunnel Oxide And Methods For Fabricating Same App 20130277732 - FANG; Shenqing ; et al.	2013-10-24
Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory Grant 8,551,858 - Fang , et al. October 8, 2	2013-10-08
SONOS memory cells having non-uniform tunnel oxide and methods for fabricating same Grant 8,487,373 - Fang , et al. July 16, 2	2013-07-16
Method And Device Employing Polysilicon Scaling App 20120056260 - Fang; Shenqing ; et al.	2012-03-08
Method and device employing polysilicon scaling Grant 8,076,199 - Fang , et al. December 13, 2	2011-12-13
Cu annealing for improved data retention in flash memory devices Grant 8,026,169 - You , et al. September 27, 2	2011-09-27
Sonos Memory Cells Having Non-uniform Tunnel Oxide And Methods For Fabricating Same App 20100276746 - FANG; Shenqing ; et al.	2010-11-04
Method And Device Employing Polysilicon Scaling App 20100207191 - FANG; Shenqing ; et al.	2010-08-19
Self-aligned Si Rich Nitride Charge Trap Layer Isolation For Charge Trap Flash Memory App 20100133646 - FANG; Shenqing ; et al.	2010-06-03
Methods For Fabricating Memory Cells Having Fin Structures With Semicircular Top Surfaces And Rounded Top Corners And Edges App 20090269916 - KANG; Inkuk ; et al.	2009-10-29
Cu annealing for improved data retention in flash memory devices App 20080108193 - You; Lu ; et al.	2008-05-08
Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure Grant 7,288,487 - Kang , et al. October 30, 2	2007-10-30
Bond pad structure for copper metallization having increased reliability and method for fabricating same Grant 7,242,102 - Kang , et al. July 10, 2	2007-07-10
Method for achieving increased control over interconnect line thickness across a wafer and between wafers Grant 7,122,465 - Ang , et al. October 17, 2	2006-10-17
Memory device and method of simultaneous fabrication of core and periphery of same Grant 7,060,564 - Kang , et al. June 13, 2	2006-06-13
ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices Grant 7,033,957 - Shiraiwa , et al. April 25, 2	2006-04-25
Bond pad structure for copper metallization having increased reliability and method for fabricating same App 20060006552 - Kang; Inkuk ; et al.	2006-01-12
Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing Grant 6,974,989 - Chen , et al. December 13, 2	2005-12-13
ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices Grant 6,969,886 - Park , et al. November 29, 2	2005-11-29
Recessed channel Grant 6,963,108 - Kang , et al. November 8, 2	2005-11-08
ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices Grant 6,803,275 - Park , et al. October 12, 2	2004-10-12

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