Jong; Kiun Kiet

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jong; Kiun Kiet.The latest application filed is for "methods and apparatus for reducing microbumps for inter-die double-data rate (ddr) transfer".

Company Profile

2.13.7

Jong; Kiun Kiet - Penang MY
Jong; Kiun Kiet - George Town MY
Jong; Kiun Kiet - Pulau Pinang MY
Jong; Kiun Kiet - Bayan Lepas MY
Jong; Kiun Kiet - Serian MY
Jong; Kiun Kiet - Gelugor N/A MY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Scalable micro bumps indexing and redundancy scheme for homogeneous configurable integrated circuit dies Grant 11,336,286 - Tang , et al. May 17, 2	2022-05-17
Methods And Apparatus For Reducing Microbumps For Inter-die Double-data Rate (ddr) Transfer App 20200097362 - Law; Hwa Chaw ; et al.	2020-03-26
Criticality-based error detection Grant 10,528,413 - Tan , et al. J	2020-01-07
Scalable Micro Bumps Indexing and Redundancy Scheme for Homogeneous Configurable Integrated Circuit Dies App 20190158096 - Tang; Lai Guan ; et al.	2019-05-23
High Speed Fpga Boot-up Through Concurrent Multi-frame Configuration Scheme App 20190156873 - Tan; Jun Pin ; et al.	2019-05-23
High speed FPGA boot-up through concurrent multi-frame configuration scheme Grant 10,186,305 - Tan , et al. Ja	2019-01-22
Criticality-based Error Detection App 20180285190 - Tan; Jun Pin ; et al.	2018-10-04
High Speed Fpga Boot-up Through Concurrent Multi-frame Configuration Scheme App 20170221537 - Tan; Jun Pin ; et al.	2017-08-03
High speed FPGA boot-up through concurrent multi-frame configuration scheme Grant 9,627,019 - Tan , et al. April 18, 2	2017-04-18
High Speed Fpga Boot-up Through Concurrent Multi-frame Configuration Scheme App 20160307612 - Tan; Jun Pin ; et al.	2016-10-20
High speed FPGA boot-up through concurrent multi-frame configuration scheme Grant 9,401,190 - Tan , et al. July 26, 2	2016-07-26
Integrated circuit with state and data retention Grant 9,383,802 - Tan , et al. July 5, 2	2016-07-05
Configuring data registers to program a programmable device with a configuration bit stream without phantom bits Grant 8,941,408 - Tan , et al. January 27, 2	2015-01-27
Configuring Data Registers To Program A Programmable Device With A Configuration Bit Stream Without Phantom Bits App 20140240000 - Tan; Jun Pin ; et al.	2014-08-28
Integrated circuit with improved interconnect routing and associated methods Grant 8,629,689 - Tan , et al. January 14, 2	2014-01-14
Memory error detection circuitry Grant 8,612,814 - Tan , et al. December 17, 2	2013-12-17
Zeroization verification of integrated circuit Grant 8,437,200 - Tan , et al. May 7, 2	2013-05-07

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.