| Patent | Date |
|---|
Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device
Grant 11,393,725 - Bao , et al. July 19, 2 | 2022-07-19 |
Nanosheet field effect transistors with partial inside spacers
Grant 11,342,446 - Guillorn , et al. May 24, 2 | 2022-05-24 |
Long Channel And Short Channel Vertical Fet Co-integration For Vertical Fet Vtfet
App 20220139909 - Hook; Terence B. ; et al. | 2022-05-05 |
Long channel and short channel vertical FET co-integration for vertical FET VTFET
Grant 11,251,179 - Hook , et al. February 15, 2 | 2022-02-15 |
Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device
Grant 11,195,762 - Bao , et al. December 7, 2 | 2021-12-07 |
Checking wafer-level integrated designs for rule compliance
Grant 11,170,151 - Hook , et al. November 9, 2 | 2021-11-09 |
Vertical field-effect transistor with a bottom contact that exhibits low electrical resistance
Grant 11,152,507 - Zhang , et al. October 19, 2 | 2021-10-19 |
Performance-screen ring oscillator with switchable features
Grant 11,146,251 - DeForge , et al. October 12, 2 | 2021-10-12 |
Fully-depleted CMOS transistors with u-shaped channel
Grant 11,145,758 - Cheng , et al. October 12, 2 | 2021-10-12 |
Performance-screen Ring Oscillator With Switchable Features
App 20210281248 - DeForge; John B. ; et al. | 2021-09-09 |
Method and structures for personalizing lithography
Grant 11,067,895 - Deforge , et al. July 20, 2 | 2021-07-20 |
Fully Depleted Soi Transistor With A Buried Ferroelectric Layer In Back-gate
App 20210151577 - Cheng; Kangguo ; et al. | 2021-05-20 |
Integrating a junction field effect transistor into a vertical field effect transistor
Grant 11,011,513 - Anderson , et al. May 18, 2 | 2021-05-18 |
Semiconductor device and method of forming the semiconductor device
Grant 10,978,454 - Anderson , et al. April 13, 2 | 2021-04-13 |
Stack viabar structures
Grant 10,971,356 - Fan , et al. April 6, 2 | 2021-04-06 |
Integration of input/output device in vertical field-effect transistor technology
Grant 10,964,812 - Liu , et al. March 30, 2 | 2021-03-30 |
Vertical transistor contact for cross-coupling in a memory cell
Grant 10,957,794 - Anderson , et al. March 23, 2 | 2021-03-23 |
Vertical transistor contact for a memory cell with increased density
Grant 10,937,793 - Anderson , et al. March 2, 2 | 2021-03-02 |
Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices
Grant 10,910,312 - Rubin , et al. February 2, 2 | 2021-02-02 |
Prevention of charging damage in full-depletion devices
Grant 10,910,282 - Hook February 2, 2 | 2021-02-02 |
Fully depleted SOI transistor with a buried ferroelectric layer in back-gate
Grant 10,903,332 - Cheng , et al. January 26, 2 | 2021-01-26 |
Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices
Grant 10,903,165 - Rubin , et al. January 26, 2 | 2021-01-26 |
Integration of input/output device in vertical field-effect transistor technology
Grant 10,840,373 - Liu , et al. November 17, 2 | 2020-11-17 |
Logic gate designs for 3D monolithic direct stacked VTFET
Grant 10,833,069 - Zhang , et al. November 10, 2 | 2020-11-10 |
Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices
Grant 10,748,901 - Rubin , et al. A | 2020-08-18 |
Checking Wafer-level Integrated Designs For Rule Compliance
App 20200257846 - A1 | 2020-08-13 |
Integration of electrostatic discharge protection into vertical fin technology
Grant 10,741,544 - Anderson , et al. A | 2020-08-11 |
Independent gate FinFET with backside gate contact
Grant 10,700,209 - Hook , et al. | 2020-06-30 |
Stack Viabar Structures
App 20200203156 - FAN; Su Chen ; et al. | 2020-06-25 |
Checking wafer-level integrated designs for rule compliance
Grant 10,691,870 - Hook , et al. | 2020-06-23 |
Semiconductor Device And Method Of Forming The Semiconductor Device
App 20200168608 - ANDERSON; Brent Alan ; et al. | 2020-05-28 |
Vertical Transistor Contact For Cross-coupling In A Memory Cell
App 20200161472 - Anderson; Brent A. ; et al. | 2020-05-21 |
Integration Of Electrostatic Discharge Protection Into Vertical Fin Technology
App 20200152619 - Anderson; Brent A. ; et al. | 2020-05-14 |
Vertical Field-effect Transistor With A Bottom Contact That Exhibits Low Electrical Resistance
App 20200144416 - Zhang; Chen ; et al. | 2020-05-07 |
Power Distribution Networks For Monolithic Three-dimensional Semiconductor Integrated Circuit Devices
App 20200135646 - Rubin; Joshua M. ; et al. | 2020-04-30 |
Stack Viabar Structures
App 20200135457 - FAN; Su Chen ; et al. | 2020-04-30 |
Power Distribution Networks For Monolithic Three-dimensional Semiconductor Integrated Circuit Devices
App 20200135645 - Rubin; Joshua M. ; et al. | 2020-04-30 |
Interlayer Via Contacts For Monolithic Three-dimensional Semiconductor Integrated Circuit Devices
App 20200126987 - Rubin; Joshua M. ; et al. | 2020-04-23 |
Bottom source/drain silicidation for vertical field-effect transistor (FET)
Grant 10,629,443 - Anderson , et al. | 2020-04-21 |
Integration of input/output device in vertical field-effect transistor technology
Grant 10,615,276 - Liu , et al. | 2020-04-07 |
Stack viabar structures
Grant 10,615,027 - Fan , et al. | 2020-04-07 |
Vertical Transistor Contact For A Memory Cell With Increased Density
App 20200105769 - Anderson; Brent A. ; et al. | 2020-04-02 |
Bulk to silicon on insulator device
Grant 10,608,080 - Hook , et al. | 2020-03-31 |
Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices
Grant 10,607,938 - Rubin , et al. | 2020-03-31 |
Semiconductor device and method of forming the semiconductor device
Grant 10,607,992 - Anderson , et al. | 2020-03-31 |
Nanosheet Field Effect Transistors With Partial Inside Spacers
App 20200098893 - Guillorn; Michael A. ; et al. | 2020-03-26 |
Integration Of Input/output Device In Vertical Field-effect Transistor Technology
App 20200066906 - Liu; Xuefeng ; et al. | 2020-02-27 |
Fully Depleted Soi Transistor With A Buried Ferroelectric Layer In Back-gate
App 20200066867 - Cheng; Kangguo ; et al. | 2020-02-27 |
Integrating A Junction Field Effect Transistor Into A Vertical Field Effect Transistor
App 20200066711 - Anderson; Brent A. ; et al. | 2020-02-27 |
Vertical transistor contact for cross-coupling in a memory cell
Grant 10,566,453 - Anderson , et al. Feb | 2020-02-18 |
Vertical transistor contact for a memory cell with increased density
Grant 10,559,572 - Anderson , et al. Feb | 2020-02-11 |
Nanosheet field effect transistors with partial inside spacers
Grant 10,559,670 - Guillorn , et al. Feb | 2020-02-11 |
Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device
Grant 10,546,787 - Bao , et al. Ja | 2020-01-28 |
FinFETs with various fin height
Grant 10,541,253 - Cheng , et al. Ja | 2020-01-21 |
Multi-metal Dipole Doping To Offer Multi-threshold Voltage Pairs Without Channel Doping For Highly Scaling Cmos Device
App 20200020595 - Bao; Ruqiang ; et al. | 2020-01-16 |
Multi-metal Dipole Doping To Offer Multi-threshold Voltage Pairs Without Channel Doping For Highly Scaling Cmos Device
App 20200020594 - Bao; Ruqiang ; et al. | 2020-01-16 |
Integration Of Input/output Device In Vertical Field-effect Transistor Technology
App 20200013891 - Liu; Xuefeng ; et al. | 2020-01-09 |
Vertical Transistor Contact For Cross-coupling In A Memory Cell
App 20200006552 - Anderson; Brent A. ; et al. | 2020-01-02 |
Vertical Transistor Contact For A Memory Cell With Increased Density
App 20200006353 - Anderson; Brent A. ; et al. | 2020-01-02 |
Extra gate device for nanosheet
Grant 10,515,859 - Doris , et al. Dec | 2019-12-24 |
Integrating a junction field effect transistor into a vertical field effect transistor
Grant 10,504,889 - Anderson , et al. Dec | 2019-12-10 |
Multi-metal Dipole Doping To Offer Multi-threshold Voltage Pairs Without Channel Doping For Highly Scaling Cmos Device
App 20190371676 - Bao; Ruqiang ; et al. | 2019-12-05 |
Logic Gate Designs for 3D Monolithic Direct Stacked VTFET
App 20190326279 - Zhang; Chen ; et al. | 2019-10-24 |
Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process
Grant 10,418,462 - Anderson , et al. Sept | 2019-09-17 |
Improved Fully-depleted Cmos Transistors With U-shaped Channel
App 20190267490 - Cheng; Kangguo ; et al. | 2019-08-29 |
Checking Wafer-level Integrated Designs For Rule Compliance
App 20190258771 - Hook; Terence B. ; et al. | 2019-08-22 |
Multiple-threshold Nanosheet Transistors
App 20190252495 - Bao; Ruqiang ; et al. | 2019-08-15 |
Logic gate designs for 3D monolithic direct stacked VTFET
Grant 10,381,346 - Zhang , et al. A | 2019-08-13 |
Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
Grant 10,366,897 - Ando , et al. July 30, 2 | 2019-07-30 |
Logic Gate Designs for 3D Monolithic Direct Stacked VTFET
App 20190229117 - Zhang; Chen ; et al. | 2019-07-25 |
Checking wafer-level integrated designs for rule compliance
Grant 10,346,580 - Hook , et al. July 9, 2 | 2019-07-09 |
Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
Grant 10,347,494 - Ando , et al. July 9, 2 | 2019-07-09 |
Multiple-threshold nanosheet transistors
Grant 10,340,340 - Bao , et al. | 2019-07-02 |
Integration Of Input/output Device In Vertical Field-effect Transistor Technology
App 20190198667 - Liu; Xuefeng ; et al. | 2019-06-27 |
Bulk to silicon on insulator device
Grant 10,332,959 - Hook , et al. | 2019-06-25 |
Fully-depleted CMOS transistors with U-shaped channel
Grant 10,326,019 - Cheng , et al. | 2019-06-18 |
Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
Grant 10,319,596 - Ando , et al. | 2019-06-11 |
Stacked vertical transistor device for three-dimensional monolithic integration
Grant 10,283,411 - Hook , et al. | 2019-05-07 |
Electrostatic Discharge Protection Using Vertical Fin Cmos Technology
App 20190131292 - Anderson; Brent A. ; et al. | 2019-05-02 |
Electrostatic discharge protection using vertical fin CMOS technology
Grant 10,276,558 - Anderson , et al. | 2019-04-30 |
Independently driving built-in self test circuitry over a range of operating conditions
Grant 10,254,340 - DeForge , et al. | 2019-04-09 |
Semiconductor device with low band-to-band tunneling
Grant 10,249,743 - Degors , et al. | 2019-04-02 |
Checking wafer-level integrated designs for antenna rule compliance
Grant 10,248,755 - Hook , et al. | 2019-04-02 |
Nanosheet MOSFET with partial release and source/drain epitaxy
Grant 10,249,739 - Guillorn , et al. | 2019-04-02 |
Mirror contact capacitor
Grant 10,229,915 - Hook , et al. | 2019-03-12 |
Semiconductor device with different fin pitches
Grant 10,224,327 - Doris , et al. | 2019-03-05 |
Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process
Grant 10,211,316 - Anderson , et al. Feb | 2019-02-19 |
Prevention of charging damage in full-depletion devices
Grant 10,204,839 - Hook Feb | 2019-02-12 |
Finfets With Various Fin Height
App 20190035816 - Cheng; Kangguo ; et al. | 2019-01-31 |
Bipolar transistor compatible with vertical FET fabrication
Grant 10,170,463 - Anderson , et al. J | 2019-01-01 |
Nanosheet field effect transistors with partial inside spacers
Grant 10,170,584 - Guillorn , et al. J | 2019-01-01 |
Stable work function for narrow-pitch devices
Grant 10,170,576 - Ando , et al. J | 2019-01-01 |
Fully-depleted silicon-on-insulator transistors
Grant 10,163,934 - Hook , et al. Dec | 2018-12-25 |
Lateral Non-volatile Storage Cell
App 20180358366 - DeForge; John B. ; et al. | 2018-12-13 |
Lateral non-volatile storage cell
Grant 10,153,291 - DeForge , et al. Dec | 2018-12-11 |
FinFETs with various fin height
Grant 10,134,760 - Cheng , et al. November 20, 2 | 2018-11-20 |
Independent gate FinFET with backside gate contact
Grant 10,128,377 - Hook , et al. November 13, 2 | 2018-11-13 |
Vertical field effect transistor with metallic bottom region
Grant 10,121,877 - Hook , et al. November 6, 2 | 2018-11-06 |
Lateral non-volatile storage cell
Grant 10,109,639 - DeForge , et al. October 23, 2 | 2018-10-23 |
Structure and method for fully depleted silicon on insulator structure for threshold voltage modification
Grant 10,090,330 - Ellis-Monaghan , et al. October 2, 2 | 2018-10-02 |
Nanosheet Mosfet With Partial Release And Source/drain Epitaxy
App 20180254329 - Guillorn; Michael A. ; et al. | 2018-09-06 |
Independent Gate Finfet With Backside Gate Contact
App 20180248042 - Hook; Terence B. ; et al. | 2018-08-30 |
Independent Gate Finfet With Backside Gate Contact
App 20180248041 - Hook; Terence B. ; et al. | 2018-08-30 |
Fully-depleted Silicon-on-insulator Transistors
App 20180240815 - HOOK; Terence B. ; et al. | 2018-08-23 |
Devices With Multiple Threshold Voltages Formed On A Single Wafer Using Strain In The High-k Layer
App 20180226257 - Ando; Takashi ; et al. | 2018-08-09 |
Semiconductor Device With Low Band-to-band Tunneling
App 20180226499 - Degors; Nicolas ; et al. | 2018-08-09 |
Nanosheet Field Effect Transistors With Partial Inside Spacers
App 20180219082 - Guillorn; Michael A. ; et al. | 2018-08-02 |
Nanosheet Field Effect Transistors With Partial Inside Spacers
App 20180219083 - Guillorn; Michael A. ; et al. | 2018-08-02 |
Semiconductor device with low band-to-band tunneling
Grant 10,038,083 - Degors , et al. July 31, 2 | 2018-07-31 |
Prevention Of Charging Damage In Full-depletion Devices
App 20180211892 - Hook; Terence B. | 2018-07-26 |
Method And Structures For Personalizing Lithography
App 20180203341 - Deforge; John B. ; et al. | 2018-07-19 |
Finfets With Various Fin Height
App 20180197886 - Cheng; Kangguo ; et al. | 2018-07-12 |
Checking Wafer-level Integrated Designs For Antenna Rule Compliance
App 20180189441 - Hook; Terence B. ; et al. | 2018-07-05 |
Structure And Method For Fully Depleted Silicon On Insulator Structure For Threshold Voltage Modification
App 20180182778 - Ellis-Monaghan; John J. ; et al. | 2018-06-28 |
Prevention of charging damage in full-depletion devices
Grant 10,002,800 - Hook June 19, 2 | 2018-06-19 |
Fully-depleted silicon-on-insulator transistors
Grant 9,997,539 - Hook , et al. June 12, 2 | 2018-06-12 |
Mirrored contact CMOS with self-aligned source, drain, and back-gate
Grant 9,997,607 - Hook , et al. June 12, 2 | 2018-06-12 |
Bulk to silicon on insulator device
Grant 9,991,339 - Hook , et al. June 5, 2 | 2018-06-05 |
Checking wafer-level integrated designs for antenna rule compliance
Grant 9,990,459 - Hook , et al. June 5, 2 | 2018-06-05 |
Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
Grant 9,984,883 - Ando , et al. May 29, 2 | 2018-05-29 |
Semiconductor device with low band-to-band tunneling
Grant 9,985,099 - Degors , et al. May 29, 2 | 2018-05-29 |
Bulk to silicon on insulator device
Grant 9,978,871 - Hook , et al. May 22, 2 | 2018-05-22 |
Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
Grant 9,972,497 - Ando , et al. May 15, 2 | 2018-05-15 |
Semiconductor Device And Method Of Forming The Semiconductor Device
App 20180122807 - ANDERSON; Brent Alan ; et al. | 2018-05-03 |
Vertical Transistors With Merged Active Area Regions
App 20180122792 - Anderson; Brent A. ; et al. | 2018-05-03 |
Vertical Transistors With Merged Active Area Regions
App 20180121593 - Anderson; Brent A. ; et al. | 2018-05-03 |
Multiple-threshold Nanosheet Transistors
App 20180114833 - Bao; Ruqiang ; et al. | 2018-04-26 |
Semiconductor Device And Method Of Forming The Semiconductor Device
App 20180108659 - ANDERSON; Brent Alan ; et al. | 2018-04-19 |
Structures and methods for long-channel devices in nanosheet technology
Grant 9,947,743 - Doris , et al. April 17, 2 | 2018-04-17 |
Extra gate device for nanosheet
Grant 9,947,593 - Doris , et al. April 17, 2 | 2018-04-17 |
Semiconductor device and method of forming the semiconductor device
Grant 9,947,664 - Anderson , et al. April 17, 2 | 2018-04-17 |
Mirror Contact Capacitor
App 20180102367 - HOOK; Terence B. ; et al. | 2018-04-12 |
Structure and method for fully depleted silicon on insulator structure for threshold voltage modification
Grant 9,941,300 - Ellis-Monaghan , et al. April 10, 2 | 2018-04-10 |
Devices With Multiple Threshold Voltages Formed On A Single Wafer Using Strain In The High-k Layer
App 20180096851 - Ando; Takashi ; et al. | 2018-04-05 |
Bipolar Transistor Compatible With Vertical Fet Fabrication
App 20180090485 - Anderson; Brent A. ; et al. | 2018-03-29 |
Bipolar Transistor Compatible With Vertical Fet Fabrication
App 20180090380 - Anderson; Brent A. ; et al. | 2018-03-29 |
Fully-depleted Cmos Transistors With U-shaped Channel
App 20180090614 - Cheng; Kangguo ; et al. | 2018-03-29 |
Bipolar transistor compatible with vertical FET fabrication
Grant 9,929,145 - Anderson , et al. March 27, 2 | 2018-03-27 |
Bulk To Silicon On Insulator Device
App 20180083134 - Hook; Terence B. ; et al. | 2018-03-22 |
Stable Work Function For Narrow-pitch Devices
App 20180083116 - Ando; Takashi ; et al. | 2018-03-22 |
Robust Built-in Self Test Circuitry
App 20180080986 - DeForge; John B. ; et al. | 2018-03-22 |
Silicidation Of Bottom Source/drain Sheet Using Pinch-off Sacrificial Spacer Process
App 20180033868 - ANDERSON; Brent A. ; et al. | 2018-02-01 |
Mirror contact capacitor
Grant 9,881,925 - Hook , et al. January 30, 2 | 2018-01-30 |
Silicidation Of Bottom Source/drain Sheet Using Pinch-off Sacrificial Spacer Process
App 20180019323 - ANDERSON; Brent A. ; et al. | 2018-01-18 |
Mirrored Contact Cmos With Self-aligned Source, Drain, And Back-gate
App 20180006126 - Hook; Terence B. ; et al. | 2018-01-04 |
Long Channel And Short Channel Vertical Fet Co-integration For Vertical Fet Vtfet
App 20180006025 - Hook; Terence B. ; et al. | 2018-01-04 |
Bipolar transistor compatible with vertical FET fabrication
Grant 9,859,172 - Anderson , et al. January 2, 2 | 2018-01-02 |
Silicidation Of Bottom Source/drain Sheet Using Pinch-off Sacrificial Spacer Process
App 20170373170 - ANDERSON; Brent A. ; et al. | 2017-12-28 |
Mirror Contact Capacitor
App 20170373070 - HOOK; Terence B. ; et al. | 2017-12-28 |
Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process
Grant 9,853,127 - Anderson , et al. December 26, 2 | 2017-12-26 |
Structures and Methods for Long-Channel Devices in Nanosheet Technology
App 20170365661 - Doris; Bruce B. ; et al. | 2017-12-21 |
Semiconductor Device With Different Fin Pitches
App 20170365601 - Doris; Bruce B. ; et al. | 2017-12-21 |
Prevention Of Charging Damage In Full-depletion Devices
App 20170330807 - Hook; Terence B. | 2017-11-16 |
Prevention Of Charging Damage In Full-depletion Devices
App 20170330804 - Hook; Terence B. | 2017-11-16 |
Extra gate device for nanosheet
Grant 9,818,650 - Doris , et al. November 14, 2 | 2017-11-14 |
Bottom Source/drain Silicidation For Vertical Field-effect Transistor (fet)
App 20170323794 - Anderson; Brent A. ; et al. | 2017-11-09 |
Semiconductor Device With Different Fin Pitches
App 20170317077 - Doris; Bruce B. ; et al. | 2017-11-02 |
Bottom Source/drain Silicidation For Vertical Field-effect Transistor (fet)
App 20170316945 - ANDERSON; BRENT A. ; et al. | 2017-11-02 |
Bottom source/drain silicidation for vertical field-effect transistor (FET)
Grant 9,805,935 - Anderson , et al. October 31, 2 | 2017-10-31 |
Semiconductor device with different fin pitches
Grant 9,793,271 - Doris , et al. October 17, 2 | 2017-10-17 |
Bulk To Silicon On Insulator Device
App 20170294340 - Hook; Terence B. ; et al. | 2017-10-12 |
Bulk To Silicon On Insulator Device
App 20170294507 - Hook; Terence B. ; et al. | 2017-10-12 |
Bulk To Silicon On Insulator Device
App 20170294533 - Hook; Terence B. ; et al. | 2017-10-12 |
Bulk To Silicon On Insulator Device
App 20170294534 - Hook; Terence B. ; et al. | 2017-10-12 |
Bulk to silicon on insulator device
Grant 9,786,546 - Hook , et al. October 10, 2 | 2017-10-10 |
Extra Gate Device For Nanosheet
App 20170287788 - Doris; Bruce B. ; et al. | 2017-10-05 |
Devices With Multiple Threshold Voltages Formed On A Single Wafer Using Strain In The High-k Layer
App 20170278713 - Ando; Takashi ; et al. | 2017-09-28 |
Checking Wafer-level Integrated Designs For Rule Compliance
App 20170277821 - Hook; Terence B. ; et al. | 2017-09-28 |
Checking Wafer-level Integrated Designs For Antenna Rule Compliance
App 20170270233 - Hook; Terence B. ; et al. | 2017-09-21 |
Extra gate device for nanosheet
Grant 9,768,079 - Doris , et al. September 19, 2 | 2017-09-19 |
Vertical transistors with merged active area regions
Grant 9,761,712 - Anderson , et al. September 12, 2 | 2017-09-12 |
Multiple back gate transistor
Grant 9,761,525 - Hook , et al. September 12, 2 | 2017-09-12 |
Immunity to inline charging damage in circuit designs
Grant 9,741,706 - Henderson , et al. August 22, 2 | 2017-08-22 |
Immunity to inline charging damage in circuit designs
Grant 9,741,707 - Henderson , et al. August 22, 2 | 2017-08-22 |
Stable work function for narrow-pitch devices
Grant 9,735,250 - Ando , et al. August 15, 2 | 2017-08-15 |
Interlayer via
Grant 9,711,501 - Basker , et al. July 18, 2 | 2017-07-18 |
Bottom Source/drain Silicidation For Vertical Field-effect Transistor (fet)
App 20170194155 - Anderson; Brent A. ; et al. | 2017-07-06 |
Extra Gate Device For Nanosheet
App 20170194216 - Doris; Bruce B. ; et al. | 2017-07-06 |
Extra Gate Device For Nanosheet
App 20170194208 - Doris; Bruce B. ; et al. | 2017-07-06 |
Extra Gate Device For Nanosheet
App 20170194214 - Doris; Bruce B. ; et al. | 2017-07-06 |
Structure And Method For Fully Depleted Silicon On Insulator Structure For Threshold Voltage Modification
App 20170179156 - Ellis-Monaghan; John Joseph ; et al. | 2017-06-22 |
Structure And Method To Minimize Junction Capacitance In Nano Sheets
App 20170170294 - Doris; Bruce B. ; et al. | 2017-06-15 |
Semiconductor device with low band-to-band tunneling
Grant 9,673,221 - Degors , et al. June 6, 2 | 2017-06-06 |
ESD device compatible with bulk bias capability
Grant 9,673,190 - Cheng , et al. June 6, 2 | 2017-06-06 |
Structure and method to minimize junction capacitance in NANO sheets
Grant 9,666,693 - Doris , et al. May 30, 2 | 2017-05-30 |
Stable Work Function For Narrow-pitch Devices
App 20170148890 - Ando; Takashi ; et al. | 2017-05-25 |
Stable Work Function For Narrow-pitch Devices
App 20170148892 - Ando; Takashi ; et al. | 2017-05-25 |
Semiconductor device with different fin pitches
Grant 9,653,463 - Doris , et al. May 16, 2 | 2017-05-16 |
Semiconductor Device With Low Band-to-band Tunneling
App 20170133494 - Degors; Nicolas ; et al. | 2017-05-11 |
Semiconductor Device With Low Band-to-band Tunneling
App 20170133464 - Degors; Nicolas ; et al. | 2017-05-11 |
Devices with multiple threshold voltages formed on a single wafer using strain in the high-K layer
Grant 9,627,484 - Ando , et al. April 18, 2 | 2017-04-18 |
Devices With Multiple Threshold Voltages Formed On A Single Wafer Using Strain In The High-k Layer
App 20170104066 - Ando; Takashi ; et al. | 2017-04-13 |
Devices With Multiple Threshold Voltages Formed On A Single Wafer Using Strain In The High-k Layer
App 20170103897 - Ando; Takashi ; et al. | 2017-04-13 |
Devices With Multiple Threshold Voltages Formed On A Single Wafer Using Strain In The High-k Layer
App 20170103982 - Ando; Takashi ; et al. | 2017-04-13 |
Esd Device Compatible With Bulk Bias Capability
App 20170098646 - Cheng; Kangguo ; et al. | 2017-04-06 |
Subsurface wires of integrated chip and methods of forming
Grant 9,601,513 - Hook , et al. March 21, 2 | 2017-03-21 |
Semiconductor device with different fin pitches
Grant 9,589,956 - Doris , et al. March 7, 2 | 2017-03-07 |
Stable work function for narrow-pitch devices
Grant 9,583,486 - Ando , et al. February 28, 2 | 2017-02-28 |
Structure and method to minimize junction capacitance in nano sheets
Grant 9,577,038 - Doris , et al. February 21, 2 | 2017-02-21 |
Fully-depleted Silicon-on-insulator Transistors
App 20160372485 - HOOK; Terence B. ; et al. | 2016-12-22 |
Contact-first Field-effect Transistors
App 20160372600 - Hook; Terence B. ; et al. | 2016-12-22 |
Field effect transistor having delay element with back gate
Grant 9,520,391 - Anderson , et al. December 13, 2 | 2016-12-13 |
Fully-depleted silicon-on-insulator transistors
Grant 9,520,329 - Hook , et al. December 13, 2 | 2016-12-13 |
Structure and method to minimize junction capacitance in nano sheets
Grant 9,515,138 - Doris , et al. December 6, 2 | 2016-12-06 |
Immunity To Inline Charging Damage In Circuit Designs
App 20160329317 - Henderson; Zachary ; et al. | 2016-11-10 |
Immunity To Inline Charging Damage In Circuit Designs
App 20160328513 - Henderson; Zachary ; et al. | 2016-11-10 |
Extra gate device for nanosheet
Grant 9,490,335 - Doris , et al. November 8, 2 | 2016-11-08 |
Fully-depleted silicon-on-insulator transistors
Grant 9,484,270 - Hook , et al. November 1, 2 | 2016-11-01 |
Semiconductor Device With Low Band-to-band Tunneling
App 20160260740 - Degors; Nicolas ; et al. | 2016-09-08 |
Series-connected nanowire structures
Grant 9,431,388 - Gauthier, Jr. , et al. August 30, 2 | 2016-08-30 |
Immunity to inline charging damage in circuit designs
Grant 9,378,329 - Henderson , et al. June 28, 2 | 2016-06-28 |
Partial Fin On Oxide For Improved Electrical Isolation Of Raised Active Regions
App 20160079397 - Cheng; Kangguo ; et al. | 2016-03-17 |
Fully-depleted Silicon-on-insulator Transistors
App 20160079127 - HOOK; Terence B. ; et al. | 2016-03-17 |
Fully-depleted Silicon-on-insulator Transistors
App 20160079277 - HOOK; Terence B. ; et al. | 2016-03-17 |
Establishing A Thermal Profile Across A Semiconductor Chip
App 20160027713 - HOOK; TERENCE B. ; et al. | 2016-01-28 |
Passive devices for FinFET integrated circuit technologies
Grant 9,236,398 - Clark, Jr. , et al. January 12, 2 | 2016-01-12 |
Partial FIN on oxide for improved electrical isolation of raised active regions
Grant 9,219,114 - Cheng , et al. December 22, 2 | 2015-12-22 |
Establishing a thermal profile across a semiconductor chip
Grant 9,178,495 - Hook , et al. November 3, 2 | 2015-11-03 |
Low gate-to-drain capacitance fully merged finFET
Grant 9,171,952 - Hook , et al. October 27, 2 | 2015-10-27 |
Establishing A Thermal Profile Across A Semiconductor Chip
App 20150270828 - Hook; Terence B. ; et al. | 2015-09-24 |
Pseudo butted junction structure for back plane connection
Grant 9,142,564 - Hook September 22, 2 | 2015-09-22 |
Modeling charge distribution on FinFET sidewalls
Grant 9,064,976 - Agarwal , et al. June 23, 2 | 2015-06-23 |
In-situ annealing for extending the lifetime of CMOS products
Grant 9,064,824 - Hook , et al. June 23, 2 | 2015-06-23 |
Electrostatic discharge resistant diodes
Grant 9,064,885 - Bu , et al. June 23, 2 | 2015-06-23 |
In-situ relaxation for improved CMOS product lifetime
Grant 9,059,120 - Hook , et al. June 16, 2 | 2015-06-16 |
Electrostatic discharge resistant diodes
Grant 9,054,124 - Bu , et al. June 9, 2 | 2015-06-09 |
Transistors Having Multiple Lateral Channel Dimensions
App 20150145042 - Bu; Huiming ; et al. | 2015-05-28 |
In-situ Annealing For Extending The Lifetime Of Cmos Products
App 20150129898 - Hook; Terence B. ; et al. | 2015-05-14 |
In-situ Relaxation For Improved Cmos Product Lifetime
App 20150132862 - Hook; Terence B. ; et al. | 2015-05-14 |
Integrated circuit including DRAM and SRAM/logic
Grant 9,018,052 - Basker , et al. April 28, 2 | 2015-04-28 |
Semiconductor device including ESD protection device
Grant 9,012,997 - Yamashita , et al. April 21, 2 | 2015-04-21 |
Estimating transistor characteristics and tolerances for compact modeling
Grant 9,009,638 - Hook , et al. April 14, 2 | 2015-04-14 |
Integrated circuit including DRAM and SRAM/logic
Grant 8,994,085 - Basker , et al. March 31, 2 | 2015-03-31 |
Integrated Circuit Including Dram And Sram/logic
App 20150064853 - Basker; Veeraraghavan S. ; et al. | 2015-03-05 |
Passive Devices For Finfet Integrated Circuit Technologies
App 20150054027 - Clark, JR.; William F. ; et al. | 2015-02-26 |
Method for dynamically switching analyses and for dynamically switching models in circuit simulators
Grant 8,959,008 - Olsen , et al. February 17, 2 | 2015-02-17 |
Partial FIN On Oxide For Improved Electrical Isolation Of Raised Active Regions
App 20150014773 - Cheng; Kangguo ; et al. | 2015-01-15 |
Passive devices for FinFET integrated circuit technologies
Grant 8,916,426 - Clark, Jr. , et al. December 23, 2 | 2014-12-23 |
Low Gate-to-drain Capacitance Fully Merged Finfet
App 20140353730 - Hook; Terence B. ; et al. | 2014-12-04 |
Method of making heat sink for integrated circuit devices
Grant 8,881,379 - Coolbaugh , et al. November 11, 2 | 2014-11-11 |
Integrated circuit including DRAM and SRAM/logic
Grant 8,835,330 - Chen , et al. September 16, 2 | 2014-09-16 |
Electrostatic Discharge Resistant Diodes
App 20140167203 - Bu; Huiming ; et al. | 2014-06-19 |
Electrostatic Discharge Resistant Diodes
App 20140167202 - Bu; Huiming ; et al. | 2014-06-19 |
Static noise margin monitoring circuit and method
Grant 8,729,908 - Cranford, Jr. , et al. May 20, 2 | 2014-05-20 |
Semiconductor Device Including Esd Protection Device
App 20140117490 - Yamashita; Tenko ; et al. | 2014-05-01 |
Field Effect Transistor Devices With Recessed Gates
App 20140061792 - Bu; Huiming ; et al. | 2014-03-06 |
Integrated circuit including DRAM and SRAM/logic
Grant 8,653,596 - Cheng , et al. February 18, 2 | 2014-02-18 |
Solutions for controlling bulk bias voltage in an extremely thin silicon-on-insulator (ETSOI) integrated circuit chip
Grant 8,653,597 - Cranford, Jr. , et al. February 18, 2 | 2014-02-18 |
Physically unclonable function implemented through threshold voltage comparison
Grant 08619979 - | 2013-12-31 |
Physically unclonable function implemented through threshold voltage comparison
Grant 8,619,979 - Ficke , et al. December 31, 2 | 2013-12-31 |
Self-limiting oxygen seal for high-K dielectric and design structure
Grant 8,564,074 - Hook , et al. October 22, 2 | 2013-10-22 |
Pseudo Butted Junction Structure for Back Plane Connection
App 20130270642 - Hook; Terence B. | 2013-10-17 |
Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability
Grant 8,552,500 - Dennard , et al. October 8, 2 | 2013-10-08 |
Passive Devices For Finfet Integrated Circuit Technologies
App 20130256748 - Clark, JR.; William F. ; et al. | 2013-10-03 |
Static Noise Margin Monitoring Circuit And Method
App 20130221987 - Cranford, JR.; Hayden C. ; et al. | 2013-08-29 |
Pseudo butted junction structure for back plane connection
Grant 8,513,106 - Hook August 20, 2 | 2013-08-20 |
Trench Isolation And Method Of Fabricating Trench Isolation
App 20130189818 - Hook; Terence B. ; et al. | 2013-07-25 |
Integrated Circuit Including Dram And Sram/logic
App 20130175595 - Cheng; Kangguo ; et al. | 2013-07-11 |
Integrated Circuit Including Dram And Sram/logic
App 20130175594 - Basker; Veeraraghavan S. ; et al. | 2013-07-11 |
Integrated Circuit Including DRAM and SRAM/Logic
App 20130178043 - Cheng; Kangguo ; et al. | 2013-07-11 |
Self-limiting Oxygen Seal For High-k Dielectric, Related Method And Design Structure
App 20130134545 - Hook; Terence B. ; et al. | 2013-05-30 |
Solutions For Controlling Bulk Bias Voltage In An Extremely Thin Silicon-on-insulator (etsoi) Integrated Circuit Chip
App 20130120055 - Cranford, Jr.; Hayden C. ; et al. | 2013-05-16 |
Method and structure for balancing power and performance using fluorine and nitrogen doped substrates
Grant 8,431,955 - Anderson , et al. April 30, 2 | 2013-04-30 |
Solutions for controlling bulk bias voltage in an extremely thin silicon-on-insulator (ETSOI) integrated circuit chip
Grant 8,416,009 - Cranford, Jr. , et al. April 9, 2 | 2013-04-09 |
Method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range
Grant 8,407,656 - Hook , et al. March 26, 2 | 2013-03-26 |
Solutions For Controlling Bulk Bias Voltage In An Extremely Thin Silicon-on-insulator (etsoi) Integrated Circuit Chip
App 20130015911 - Cranford, JR.; Hayden C. ; et al. | 2013-01-17 |
Design Method And Structure For A Transistor Having A Relatively Large Threshold Voltage Variation Range And For A Random Number Generator Incorporating Multiple Essentially Identical Transistors Having Such A Large Threshold Voltage Variation Range
App 20120326752 - Hook; Terence B. ; et al. | 2012-12-27 |
Structure For Cmos Etsoi With Multiple Threshold Voltages And Active Well Bias Capability
App 20120299080 - Dennard; Robert H. ; et al. | 2012-11-29 |
Heat Sink For Integrated Circuit Devices
App 20120214280 - COOLBAUGH; Douglas D. ; et al. | 2012-08-23 |
Method for Dynamically Switching Analyses and For Dynamically Switching Models in Circuit Simulators
App 20120203532 - Olsen; Michael Claus ; et al. | 2012-08-09 |
Method of cooling a resistor
Grant 8,230,586 - Coolbaugh , et al. July 31, 2 | 2012-07-31 |
Methods and Structures Involving Terminal Connections
App 20120168210 - Hook; Terence B. ; et al. | 2012-07-05 |
Pseudo Butted Junction Structure for Back Plane Connection
App 20120146147 - Hook; Terence B. | 2012-06-14 |
Method And Structure For Balancing Power And Performance Using Fluorine And Nitrogen Doped Substrates
App 20120018812 - Anderson; Brent A. ; et al. | 2012-01-26 |
Physically Unclonable Function Implemented Through Threshold Voltage Comparison
App 20110317829 - Ficke; Joel T. ; et al. | 2011-12-29 |
Heat sink for integrated circuit devices
Grant 7,994,895 - Coolbaugh , et al. August 9, 2 | 2011-08-09 |
Isolated high performance FET with a controllable body resistance
Grant 7,939,894 - Hook , et al. May 10, 2 | 2011-05-10 |
Protection against charging damage in hybrid orientation transistors
Grant 7,928,513 - Hook , et al. April 19, 2 | 2011-04-19 |
Method of providing protection against charging damage in hybrid orientation transistors
Grant 7,879,650 - Hook , et al. February 1, 2 | 2011-02-01 |
Method and structure to protect FETs from plasma damage during FEOL processing
Grant 7,863,112 - Nair , et al. January 4, 2 | 2011-01-04 |
Method of determining n-well scattering effects on FETs
Grant 7,824,933 - Galland , et al. November 2, 2 | 2010-11-02 |
Integrated circuits comprising resistors having different sheet resistances and methods of fabricating the same
Grant 7,785,979 - Booth, Jr. , et al. August 31, 2 | 2010-08-31 |
CMOS well structure and method of forming the same
Grant 7,709,365 - Haensch , et al. May 4, 2 | 2010-05-04 |
Determining allowance antenna area as function of total gate insulator area for SOI technology
Grant 7,712,057 - Bonges , et al. May 4, 2 | 2010-05-04 |
Method of selectively adjusting ion implantation dose on semiconductor devices
Grant 7,682,910 - Hook , et al. March 23, 2 | 2010-03-23 |
Isolated High Performance Fet With A Controllable Body Resistance
App 20100025769 - Hook; Terence B. ; et al. | 2010-02-04 |
Integrated Circuits Comprising Resistors Having Different Sheet Resistances And Methods Of Fabricating The Same
App 20100013026 - Booth, JR.; Roger Allen ; et al. | 2010-01-21 |
Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing
Grant 7,649,262 - Chapple-Sokol , et al. January 19, 2 | 2010-01-19 |
Suppression Of Localized Metal Precipitate Formation And Corresponding Metallization Depletion In Semiconductor Processing
App 20090294968 - Chapple-Sokol; Jonathan D. ; et al. | 2009-12-03 |
Dual gate dielectric thickness devices and circuits using dual gate dielectric thickness devices
Grant 7,615,827 - Anderson , et al. November 10, 2 | 2009-11-10 |
Method Of Selectively Adjusting Ion Implantation Dose On Semiconductor Devices
App 20090258480 - Hook; Terence B. ; et al. | 2009-10-15 |
Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing
Grant 7,572,650 - Chapple-Sokol , et al. August 11, 2 | 2009-08-11 |
Precision passive circuit structure
Grant 7,566,946 - Coolbaugh , et al. July 28, 2 | 2009-07-28 |
Protection against charging damage in hybrid orientation transistors
App 20090179269 - Hook; Terence B. ; et al. | 2009-07-16 |
Method of assessing potential for charging damage in integrated circuit designs and structures for preventing charging damage
Grant 7,560,345 - Hook , et al. July 14, 2 | 2009-07-14 |
METHOD AND STRUCTURE TO PROTECT FETs FROM PLASMA DAMAGE DURING FEOL PROCESSING
App 20090174008 - Nair; Deleep R. ; et al. | 2009-07-09 |
Determining Allowable Antenna Area As Function Of Total Gate Insulator Area For Soi Technology
App 20090158230 - Bonges, III; Henry A. ; et al. | 2009-06-18 |
Immunity To Charging Damage In Silicon-on-insulator Devices
App 20090094567 - Eng; Chung-Ping ; et al. | 2009-04-09 |
Methods of improving operational parameters of pair of matched transistors and set of transistors
Grant 7,516,426 - Hook , et al. April 7, 2 | 2009-04-07 |
Protection against charging damage in hybrid orientation transistors
Grant 7,492,016 - Hook , et al. February 17, 2 | 2009-02-17 |
Highly Tunable Metal-on-semiconductor Varactor
App 20080157159 - Hook; Terence B. ; et al. | 2008-07-03 |
Methods Of Improving Operational Parameters Of Pair Of Matched Transistors And Set Of Transistors
App 20080116527 - Hook; Terence B. ; et al. | 2008-05-22 |
Method of providing protection against charging damage in hybrid orientation transistors
App 20080108186 - Hook; Terence B. ; et al. | 2008-05-08 |
Heat Sink For Integrated Circuit Devices
App 20080042798 - Coolbaugh; Douglas D. ; et al. | 2008-02-21 |
Device Modeling For Proximity Effects
App 20080022237 - Adler; Eric ; et al. | 2008-01-24 |
Heat Sink For Integrated Circuit Devices
App 20080019101 - COOLBAUGH; Douglas D. ; et al. | 2008-01-24 |
Structure And Method For Providing Precision Passive Elements
App 20080018378 - Coolbaugh; Douglas D. ; et al. | 2008-01-24 |
Heat sink for integrated circuit devices
Grant 7,310,036 - Coolbaugh , et al. December 18, 2 | 2007-12-18 |
Device modeling for proximity effects
Grant 7,302,376 - Adler , et al. November 27, 2 | 2007-11-27 |
Structure and method for providing precision passive elements
Grant 7,300,807 - Coolbaugh , et al. November 27, 2 | 2007-11-27 |
Structure And Method For Reducing Susceptibility To Charging Damage In Soi Designs
App 20070271540 - Eng; Chung-Ping ; et al. | 2007-11-22 |
Protection Against Charging Damage In Hybrid Orientation Transistors
App 20070228479 - Hook; Terence B. ; et al. | 2007-10-04 |
Method of Assessing Potential for Charging Damage in Integrated Circuit Designs and Structures for Preventing Charging Damage
App 20070212799 - Hook; Terence B. ; et al. | 2007-09-13 |
Cmos Well Structure And Method Of Forming The Same
App 20070045749 - Haensch; Wilfried ; et al. | 2007-03-01 |
Suppression Of Localized Metal Precipitate Formation And Corresponding Metallization Depletion In Semiconductor Processing
App 20070040277 - Chapple-Sokol; Jonathan D. ; et al. | 2007-02-22 |
Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing
Grant 7,173,338 - Chapple-Sokol , et al. February 6, 2 | 2007-02-06 |
Structure and method for local resistor element in integrated circuit technology
Grant 7,166,904 - Gill , et al. January 23, 2 | 2007-01-23 |
Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage
Grant 7,132,318 - Bonges, III , et al. November 7, 2 | 2006-11-07 |
CMOS well structure and method of forming the same
Grant 7,132,323 - Haensch , et al. November 7, 2 | 2006-11-07 |
Dual gate dielectric thickness devices
App 20060208323 - Anderson; Brent A. ; et al. | 2006-09-21 |
Method Of Determining N-well Scattering Effects On Fets
App 20060205098 - Galland; Micah ; et al. | 2006-09-14 |
Low trigger voltage, low leakage ESD NFET
Grant 7,098,513 - Chatty , et al. August 29, 2 | 2006-08-29 |
Dual gate dielectric thickness devices
Grant 7,087,470 - Anderson , et al. August 8, 2 | 2006-08-08 |
Low Trigger Voltage, Low Leakage Esd Nfet
App 20060157799 - Chatty; Kiran V. ; et al. | 2006-07-20 |
Heat Sink For Integrated Circuit Devices
App 20060152333 - Coolbaugh; Douglas D. ; et al. | 2006-07-13 |
Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage
Grant 7,067,886 - Bonges, III , et al. June 27, 2 | 2006-06-27 |
Dual gate dielectric thickness devices
App 20050280097 - Anderson, Brent A. ; et al. | 2005-12-22 |
Structure And Method For Providing Precision Passive Elements
App 20050233478 - Coolbaugh, Douglas D. ; et al. | 2005-10-20 |
Leakage compensation circuit
Grant 6,956,417 - Bernstein , et al. October 18, 2 | 2005-10-18 |
Suppression Of Localized Metal Precipitate Formation And Corresponding Metallization Depletion In Semiconductor Processing
App 20050194689 - Chapple-Sokol, Jonathan D. ; et al. | 2005-09-08 |
Structure And Method For Local Resistor Element In Integrated Circuit Technology
App 20050167786 - Gill, Jason P. ; et al. | 2005-08-04 |
Leakage Compensation Circuit
App 20050110535 - Bernstein, Kerry ; et al. | 2005-05-26 |
CMOS well structure and method of forming the same
App 20050106800 - Haensch, Wilfried ; et al. | 2005-05-19 |
Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage
App 20050098799 - Bonges, Henry A. III ; et al. | 2005-05-12 |
Method Of Assessing Potential For Charging Damage In Soi Designs And Structures For Eliminating Potential For Damage
App 20050093072 - Bonges, Henry A. III ; et al. | 2005-05-05 |
Selective silicide blocking
Grant 6,881,672 - Breitwisch , et al. April 19, 2 | 2005-04-19 |
On chip resistor calibration structure and method
Grant 6,825,490 - Hook , et al. November 30, 2 | 2004-11-30 |
Method for forming a retrograde implant
Grant 6,797,592 - Brown , et al. September 28, 2 | 2004-09-28 |
Selective silicide blocking
App 20040110371 - Breitwisch, Matthew J. ; et al. | 2004-06-10 |
Selective silicide blocking
Grant 6,700,163 - Breitwisch , et al. March 2, 2 | 2004-03-02 |
Device Modeling For Proximity Effects
App 20040034517 - Adler, Eric ; et al. | 2004-02-19 |
Method for forming a retrograde implant
App 20030211715 - Brown, Jeffrey S. ; et al. | 2003-11-13 |
Method For Forming A Retrograde Implant
App 20030162374 - Brown, Jeffrey S. ; et al. | 2003-08-28 |
Method for forming a retrograde implant
Grant 6,610,585 - Brown , et al. August 26, 2 | 2003-08-26 |
Selective silicide blocking
App 20030107091 - Breitwisch, Matthew J. ; et al. | 2003-06-12 |
Angled Implant Process
App 20030008484 - Hook, Terence B. | 2003-01-09 |
Angled implant process
Grant 6,489,223 - Hook , et al. December 3, 2 | 2002-12-03 |
Dual EPI active pixel cell design and method of making the same
Grant 6,333,204 - Hook , et al. December 25, 2 | 2001-12-25 |
High performance semiconductor memory device with low power consumption
Grant 6,307,805 - Andersen , et al. October 23, 2 | 2001-10-23 |
Asymmetrical field effect transistor
Grant 6,271,565 - Hook , et al. August 7, 2 | 2001-08-07 |
Apparatus and method for detecting defective NVRAM cells
Grant 6,256,755 - Hook , et al. July 3, 2 | 2001-07-03 |
Method of forming a complementary active pixel sensor cell
Grant 6,194,702 - Hook , et al. February 27, 2 | 2001-02-27 |
Method to perform selective drain engineering with a non-critical mask
Grant 6,083,794 - Hook , et al. July 4, 2 | 2000-07-04 |
Active pixel sensor cell and method of using
Grant 6,026,964 - Hook , et al. February 22, 2 | 2000-02-22 |
NVRAM utilizing high voltage TFT device and method for making the same
Grant 6,022,770 - Hook , et al. February 8, 2 | 2000-02-08 |
Use of deuterated materials in semiconductor processing
Grant 5,972,765 - Clark , et al. October 26, 1 | 1999-10-26 |
Dual EPI active pixel cell design and method of making the same
Grant 5,898,196 - Hook , et al. April 27, 1 | 1999-04-27 |
Semiconductor manufacturing process for low dislocation defects
Grant 5,562,770 - Chen , et al. October 8, 1 | 1996-10-08 |
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